VX8PFFA-828L8E-7中文资料

Ultralow V F Hyperfast Rectifierfor Discontinuous Mode PFC, 8 A FRED Pt ®FEATURES•Hyperfast recovery time•Benchmark ultralow forward voltage drop •175 °C operating junction temperature•Low leakage current•Fully isolated package (V INS = 2500 V RMS )•UL E78996 pending•Compliant to RoHS Directive 2002/95/EC•Designed and qualified according to JEDEC-JESD47•Halogen-free according to I EC 61249-2-21 definition (-N3 only)DESCRIPTIONState of the art, ultralow V F , soft-switching hyperfast rectifiers optimized for Discontinuous (Critical) Mode (DCM)Power Factor Correction (PFC).The minimized conduction loss, optimized stored charge and low recovery current minimize the switching losses and reduce over dissipation in the switching element and snubbers.The device is also intended for use as a freewheeling diode in power supplies and other power switching applications.APPLICATIONSAC/DC SMPS 70 W to 400 We.g. laptop and printer AC adaptors, desktop PC, TV and monitor, games units and DVD AC/DC power supplies.PRODUCT SUMMARYPackage TO-220AC, TO-220FPI F(AV)8 A V R 600 V V F at I F 1.05 V t rr typ.60 ns T J max.175 °C Diode variationSingle dieTO-220ACTO-220 FULL-PAKABSOLUTE MAXIMUM RATINGSPARAME ER SYMBOL T ES T CONDI T IONS VALUES UNI T S Repetitive peak reverse voltage V RRM 600VAverage rectified forward current I F(AV)T C = 160 °C 8A FULL-PAKT C = 142 °C Non-repetitive peak surge current I FSM T J = 25 °C175Repetitive peak forward currentI FM 16Operating junction and storage temperaturesT J , T Stg- 65 to 175°C ELECTRICAL SPECIFICATIONS (T J = 25 °C unless otherwise specified)PARAME T ER SYMBOLT ES T CONDI T IONS MIN. T YP. MAX. UNI T S Breakdown voltage,blocking voltage V BR ,V R I R = 100 μA 600--VForward voltage V F I F = 8 A-0.96 1.05I F = 8 A, T J = 150 °C -0.810.86Reverse leakage current I R V R = V R rated-0.055μA T J = 150 °C, V R = V R rated -20100Junction capacitance C T V R = 600 V-17-pF Series inductance L SMeasured lead to lead 5 mm from package body-8.0-nHFig. 1 - Typical Forward Voltage Drop CharacteristicsReverse VoltageDYNAMIC RECOVERY CHARACTERISTICS (T C = 25 °C unless otherwise specified)PARAME T ER SYMBOL T ES T CONDI T IONS MIN. T YP. MAX. UNI T SReverse recovery timet rrI F = 1 A, dI F /dt = 100 A/μs, V R = 30 V-60100nsI F = 8 A, dI F /dt = 100 A/μs, V R = 30 V -150250T J = 25 °C I F = 8 AdI F /dt = 200 A/μs V R = 390 V-170-T J = 125 °C-250-Peak recovery current I RRM T J = 25 °C -15-A T J = 125 °C -20-Reverse recovery chargeQ rrT J = 25 °C - 1.3-μC T J = 125 °C- 2.6-THERMAL - MECHANICAL SPECIFICATIONSPARAME ER SYMBOL T ES T CONDI T IONS MIN. T YP. MAX. UNI T S Maximum junction and storage temperature range T J , T Stg - 65-175°CThermal resistance,junction to caseR thJC - 1.42°C/W (FULL-PAK)- 3.4 4.3Thermal resistance,junction to ambient per leg R thJA Typical socket mount--70Thermal resistance,case to heatsink R thCSMounting surface, flat, smooth and greased-0.5-Weight- 2.0-g -0.07-oz.Mounting torque 6.0(5.0)-12(10)kgf · cm (lbf · in)Marking deviceCase style TO-220AC 8ETL06Case style TO-220 FULL-PAK8ETL06FPFig. 3 - Typical Junction Capacitance vs. Reverse VoltageFig. 4 - Maximum Thermal Impedance Z thJC CharacteristicsFig. 5 - Maximum Thermal Impedance Z thJC Characteristics (FULL-PAK)Fig. 6 - Maximum Allowable Case Temperature vs.Average Forward CurrentFig. 7 - Maximum Allowable Case Temperature vs.Average Forward Current (FULL-PAK)Fig. 8 - Forward Power Loss CharacteristicsFig. 9 - Typical Reverse Recovery Time vs. dI F /dtFig. 10 - Typical Stored Charge vs. dI F /dtNote(1)Formula used: T C = T J - (Pd + Pd REV ) x R thJC ;Pd = Forward power loss = I F(AV) x V FM at (I F(AV)/D) (see fig. 8); Pd REV = Inverse power loss = V R1 x I R (1 - D); I R at V R1 = Rated V RFig. 11 - Reverse Recovery Parameter Test CircuitFig. 12 - Reverse Recovery Waveform and DefinitionsORDERING INFORMATION TABLEORDERING INFORMATION (Example)PREFERRED P/N QUANTITY PER T/R MINIMUM ORDER QUANTITY PACKAGING DESCRIPTION VS-8ETL06PbF501000Antistatic plastic tubeVS-8ETL06-N3501000Antistatic plastic tubeVS-8ETL06FPPbF501000Antistatic plastic tubeVS-8ETL06FP-N3501000Antistatic plastic tubeLINKS TO RELATED DOCUMENTSDimensions TO-220AC /doc?95221 TO-220FP /doc?95005Part marking information TO-220ACPbF /doc?95224 /doc?95068 TO-220FPPbF /doc?95009 /doc?95440Outline Dimensions Vishay SemiconductorsDIMENSIONS in millimetersDocument Number: 95221For technical questions within your region, please contact one of the following:Revision: 07-Mar-11DiodesAmericas@ , DiodesAsia@ , DiodesEurope@1TO-220ACOutline DimensionsVishay SemiconductorsDIMENSIONS in millimeters and inchesNotes(1)Dimensioning and tolerancing as per ASME Y14.5M-1994(2)Lead dimension and finish uncontrolled in L1(3)Dimension D, D1 and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body(4)Dimension b1, b3 and c1 apply to base metal only (5)Controlling dimension: inches(6)Thermal pad contour optional within dimensions E, H1, D2 and E1(7)Dimension E2 x H1 define a zone where stamping and singulation irregularities are allowed(8)Outline conforms to JEDEC TO-220, D2 (minimum) where dimensions are derived from the actual package outlineSYMBOLMILLIMETERS INCHES NOTES SYMBOLMILLIMETERS INCHES NOTES MIN.MAX.MIN.MAX.MIN.MAX.MIN.MAX.A 4.25 4.650.1670.183E1 6.868.890.2700.3506A1 1.14 1.400.0450.055E2-0.76-0.0307A2 2.56 2.920.1010.115e 2.41 2.670.0950.105b 0.69 1.010.0270.040e14.885.280.1920.208b10.380.970.0150.0384H16.09 6.480.2400.2556, 7b2 1.20 1.730.0470.068L 13.5214.020.5320.552b3 1.14 1.730.0450.0684L1 3.32 3.820.1310.1502c 0.360.610.0140.024L3 1.78 2.130.0700.084c10.360.560.0140.0224L40.76 1.270.0300.0502D 14.8515.250.5850.6003Ø P 3.54 3.730.1390.147D18.389.020.3300.355Q 2.603.000.1020.118D211.6812.880.4600.507690° to 93°90° to 93°E10.1110.510.3980.4143, 6Legal Disclaimer Notice VishayDisclaimerALL PRODU CT, PRODU CT SPECIFICATIONS AND DATA ARE SU BJECT TO CHANGE WITHOU T NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.Material Category PolicyVishay Intertechnology, Inc. hereb y certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant.Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.Revision: 12-Mar-121Document Number: 91000分销商库存信息:VISHAY8ETL06FPPBF8ETL068ETL06FP。

7Series FPGAs Package FilesAbout ASCII Package FilesThe ASCII files for each package include a comma-separated-values (CSV) version and a text version optimized for a browser or text editor. Each of the files consists of the following:•Device/Package name (FPGA Family—Device—Package), date and time of creation•Eight columns containing data for each pin:°Pin—Pin location on the package.°Pin Name—The name of the assigned pin.°Memory Byte Group—Memory byte group between 0 and 3. For more information on the memory byte group, see the 7Series FPGAs Memory Interface Solutions UserGuide (UG586).°Bank—Bank number.°V CCAUX Group—Number corresponding to the V CCAUX_IO power supply for the given pin. V CCAUX is shown for packages with only one V CCAUX group.°Super Logic Region—Number corresponding to the super logic region (SLR) in the devices implemented with stacked silicon interconnect (SSI) technology.°I/O Type—CONFIG, HR, HP, or GT (GTP, GTX, GTH) depending on theI/O type. For more information on the I/O type, see the 7Series FPGAs SelectIOResources User Guide (UG471).°No-Connect—This list of devices is used for migration between devices that have the same package size and are not connected at that specific pin.•Total number of pins in the package.•The package file links for the ruggedized packages have the same pinouts are as the equivalent BGA packages.°RS pinouts use the SBG/SBV files (Artix®-7 devices)°RB pinouts use the FBG/FBV files (Artix-7 devices)°RF pinouts use the FFG/FFV files (Kintex®-7 and Virtex®-7 devices)Table 2-1:Spartan-7 FPGAs Package/Device Pinout FilesDevice CPGA196CSGA225CSGA324FTGB196FGGA484FGGA676XC7S6 XA7S6CPGA196ProductionCSGA225ProductionFTGB196ProductionXC7S15 XA7S15CPGA196ProductionCSGA225ProductionFTGB196ProductionXC7S25 XA7S25CSGA225ProductionCSGA324ProductionFTGB196ProductionXC7S50 XA7S50CSGA324ProductionFTGB196ProductionFGGA484ProductionXC7S75 XA7S75FGGA484ProductionFGGA676ProductionXC7S100 XA7S100FGGA484ProductionFGGA676ProductionTo download all available Virtex-7 FPGAs package/device/pinout files click here:Note:Only the available files listed in Table2-4 and Table2-5 are linked and consolidated in the above ZIP file.Table 2-4:Virtex-7T FPGAs Package/Device Pinout FilesDevice FF1157/FFG1157FF1761/FFG1761FL1925/FLG1925FH1761/FHG1761RF1157RF1761 XC7V585T FFG1157FFG1761XC7V2000T FLG1925FHG1761XQ7V585T RF1157RF1761 Table 2-5:Virtex-7XT FPGAs Package/Device Pinout FilesDeviceFF1157FFG1157FFV1157RF1157FF1158FFG1158FFV1158RF1158FF1761FFG1761FFV1761RF1761FF1926FFG1926FF1927FFG1927FFV1927FF1928FFG1928FF1930FFG1930RF1930FL1926FLG1926FL1928FLG1928FL1930FLG1930XC7VX330T FFG1157FFG1761XC7VX415T FFG1157FFG1158FFG1927XC7VX485T FFG1157FFG1158FFG1761FFG1927FFG1930XC7VX550T FFG1158FFG1927XC7VX690T FFG1157FFG1158FFG1761FFG1926FFG1927FFG1930XC7VX980T FFG1926FFG1928FFG1930XC7VX1140T FLG1926FLG1928FLG1930 XQ7VX330T RF1157RF1761XQ7VX485T RF1761RF1930XQ7VX690T RF1157RF1158RF1761RF1930XQ7VX980T RF1930CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T CPG236 Package (only)—XA7A15T, XA7A35T, and XA7A50TCPG236 Packages (only)—XA7A15T, XA7A35T, and XA7A50T Pinout DiagramFigure 3-42:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T I/O BanksFigure 3-43:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T CPG236 Packages (only)—XA7A15T, XA7A35T, and XA7A50T Memory GroupingsFigure 3-44:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T CPG236 Packages (only)—XA7A15T, XA7A35T, and XA7A50T Power and GND Placement。

SummaryThe Xilinx ® Kintex ® UltraScale+™ FPGAs are available in -3, -2, -1 speed grades, with -3E devices having the highest performance. The -2LE and -1LI devices can operate at a V CCINT voltage at 0.85V or 0.72V and provide lower maximum static power. When operated at V CCINT = 0.85V, using -2LE and -1LI devices, the speedspecification for the L devices is the same as the -2I or -1I speed grades. When operated at V CCINT = 0.72V, the -2LE and -1LI performance and static and dynamic power is reduced.DC and AC characteristics are specified in extended (E), industrial (I), and military (M) temperature ranges.Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade extended device are the same as for a -1 speed grade industrial device). However, only selected speed grades and/or devices are available in each temperature range.The XQ references in this data sheet are specific to the devices available in XQ Ruggedized packages. See the Defense-Grade UltraScale Architecture Data Sheet: Overview (DS895) for further information on XQ Defense-grade part numbers, packages, and ordering information.All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.This data sheet, part of an overall set of documentation on the Kintex UltraScale+ FPGAs, is available on the Xilinx.DC CharacteristicsAbsolute Maximum RatingsKintex UltraScale+ FPGAs Data Sheet:DC and AC Switching CharacteristicsTable 12: Differential SelectIO DC Input and Output LevelsI/O StandardV ICM (V)1V ID (V)2V ILHS3V IHHS3V OCM (V)4V OD (V)5 Min Typ Max Min Typ Max Min Max Min Typ Max Min Typ MaxSUB_LVDS80.5000.900 1.3000.070––––0.7000.900 1.1000.1000.1500.200 LVPECL0.300 1.200 1.4250.1000.3500.600––––––––SLVS_400_180.0700.2000.3300.140–0.450––––––––SLVS_400_250.0700.2000.3300.140–0.450––––––––MIPI_DPHY_DCI_HS90.070–0.3300.070–––0.0400.4600.1500.2000.2500.1400.2000.270Table 27: Maximum Physical Interface (PHY) Rate for Memory InterfacesMemoryStandard Packages DRAM Type Speed Grade and V CCINT Operating VoltagesUnits 0.90V0.85V0.72V-3-2-1-2-1DDR4All FFV and FFRpackages Single rank component26662666240024002133Mb/s1 rank DIMM1, 2, 324002400213321331866Mb/s2 rank DIMM1, 421332133186618661600Mb/s 4 rank DIMM1, 51600160013331333N/A Mb/sSFVB784 and SFRB784Single rank component24002400213321331866Mb/s1 rank DIMM1, 221332133186618661600Mb/s2 rank DIMM1, 418661866160016001600Mb/sTable 27: Maximum Physical Interface (PHY) Rate for Memory Interfaces (cont'd)MemoryStandard Packages DRAM Type Speed Grade and V CCINT Operating VoltagesUnits 0.90V0.85V0.72V-3-2-1-2-1DDR3All FFV and FFRpackages Single rank component21332133213321331866Mb/s1 rank DIMM1, 218661866186618661600Mb/s2 rank DIMM1, 416001600160016001333Mb/s 4 rank DIMM1, 51066106610661066800Mb/sSFVB784 and SFRB784Single rank component18661866186618661600Mb/s1 rank DIMM1, 216001600160016001600Mb/s2 rank DIMM1, 416001600160016001333Mb/s4 rank DIMM1, 51066106610661066800Mb/sDDR3L All FFV and FFRpackages Single rank component18661866186618661600Mb/s1 rank DIMM1, 216001600160016001333Mb/s2 rank DIMM1, 413331333133313331066Mb/s 4 rank DIMM1, 5800800800800606Mb/sSFVB784 and SFRB784Single rank component16001600160016001600Mb/s1 rank DIMM1, 216001600160016001333Mb/s2 rank DIMM1, 413331333133313331066Mb/s4 rank DIMM1, 5800800800800606Mb/s QDR II+All Single rank component6633633600600550MHz RLDRAM 3All FFV and FFRpackagesSingle rank component1200120010661066933MHz SFVB784 and SFRB784Single rank component10661066933933800MHz QDR IV XP All Single rank component106610661066933933MHz LPDDR3All Single rank component16001600160016001600Mb/s Notes:1.Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.2.Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.3.For the DDR4 DDP components at -3 and -2 (V CCINT = 0.85V) speed grades, the maximum data rate is 2133 Mb/s for six or more DDPdevices. For five or less DDP devices, use the single rank DIMM data rates for the -3 and -2 (V CCINT = 0.85V) speed grades.4.Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.5.Includes: 2 rank 2 slot, 4 rank 1 slot.6.The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.FPGA Logic Switching CharacteristicsThe following IOB high-density (HD) and IOB high-performance (HP) tables summarize the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.•T INBUF_DELAY_PAD_I is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.•T OUTBUF_DELAY_O_PAD is the delay from the O pin to the IOB pad through the output buffer of an IOB pad.The delay varies depending on the capability of the SelectIO output buffer.Table 29: IOB High Performance (HP) Switching Characteristics (cont'd)I/O StandardsT INBUF_DELAY_PAD_I T OUTBUF_DELAY_O_PAD T OUTBUF_DELAY_TD_PADUnits 0.90V0.85V0.72V0.90V0.85V0.72V0.90V0.85V0.72V-3-2-1-2-1-3-2-1-2-1-3-2-1-2-1SSTL15_DCI_S0.3190.4020.4170.4020.4170.7680.7680.8220.7680.8220.8470.8470.9120.8470.912ns SSTL15_F0.3200.3710.4000.3710.4000.3930.4080.4280.4080.4280.4940.5300.5560.5300.556ns SSTL15_M0.3200.3710.4000.3710.4000.5470.5540.5850.5540.5850.6240.6390.6770.6390.677ns SSTL15_S0.3200.3710.4000.3710.4000.7670.7670.8170.7670.8170.8130.8130.8670.8130.867ns SSTL18_I_DCI_F0.2560.3290.3360.3290.3360.4220.4450.4610.4450.4610.5400.5660.5950.5660.595ns SSTL18_I_DCI_M0.2560.3290.3360.3290.3360.5520.5540.5850.5540.5850.6290.6440.6830.6440.683ns SSTL18_I_DCI_S0.2560.3290.3360.3290.3360.7620.7620.8180.7620.8180.8370.8370.8990.8370.899ns SSTL18_I_F0.2590.3160.3370.3160.3370.4390.4540.4760.4540.4760.5490.5780.6080.5780.608ns SSTL18_I_M0.2590.3160.3370.3160.3370.5670.5710.6030.5710.6030.5350.6520.6920.6520.692ns SSTL18_I_S0.2590.3160.3370.3160.3370.7820.7820.8350.7820.8350.8160.8160.8700.8160.870ns SUB_LVDS0.5080.5390.6200.5390.6200.6580.6600.6920.6600.692907.4969.863nsSymbol Description Speed Grade and V CCINT Operating VoltagesUnits 0.90V0.85V0.72V-3-2-1-2-1T OUTBUF_DELAY_TE_PAD T input to pad high-impedance for HD I/Obanks6.167 6.318 6.369 6.699 6.752nsT input to pad high-impedance for HP I/Obanks5.330 5.330 5.341 5.330 5.341nsT INBUF_DELAY_IBUFDIS_O IBUF turn-on time from IBUFDISABLE to Ooutput for HD I/O banks2.266 2.266 2.430 2.266 2.430nsIBUF turn-on time from IBUFDISABLE to Ooutput for HP I/O banks0.8730.936 1.0370.936 1.037ns。

元器件交易网
M25P128
128 Mbit (Multilevel), low-voltage, Serial Flash memory with 50-MHz SPI bus interface
Feature summary
■ 128 Mbit of Flash memory ■ 2.7 to 3.6 V single supply voltage ■ SPI bus compatible Serial interface ■ 50 MHz clock rate (maximum) ■ VPP = 9 V for fast Program/Erase mode
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.5 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13