74F652SC中文资料

© 1999 Fairchild Semiconductor CorporationDS009581

www.fairchildsemi.comMarch 1988Revised August 199974F651

• 74F652 Transceivers/Registers74F651 • 74F652Transceivers/Registers

General DescriptionThese devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexedtransmission of data directly from the input bus or frominternal registers. Data on the A or B bus will be clockedinto the registers as the appropriate clock pin goes to HIGHlogic level. Output Enable pins (OEAB, OEBA) are pro-vided to control the transceiver function.FeaturessIndependent registers for A and B busessMultiplexed real-time and stored datasChoice of non-inverting and inverting data paths74F651 inverting74F652 non-inverting Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Connection DiagramOrder NumberPackage NumberPackage Description74F651SC M24B24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide74F651SPCN24C24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide74F652SC M24B24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide74F652SPCN24C24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide元器件交易网www.cecb2b.comwww.fairchildsemi.com274F651 • 74F652Logic Symbols74F651

IEEE/IEC74F65174F652

IEEE/IEC74F652

Unit Loading/Fan Out

Function Table

H = HIGH Voltage LevelX = ImmaterialL = LOW Voltage Level󰀑 = LOW-to-HIGH Clock TransitionNote 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.Pin NamesDescriptionU.L.Input IIH/IILHIGH/LOWOutput IOH/IOLA0–A7, B0–B7A and B Inputs/1.0/1.020 µA/−0.6 mA3-STATE Outputs600/106.6 (80)−12 mA/64 mA (48 mA)CPAB, CPBAClock Inputs1.0/1.020 µA/−0.6 mASAB, SBASelect Inputs1.0/1.020 µA/−0.6 mAOEAB, OEBAOutput Enable Inputs1.0/1.020 µA/−0.6 mA

InputsInputs/Outputs (Note 1)Operating ModeOEABOEBACPABCPBASABSBAA0 thru A7B0 thru B7LHH or LH or LXXInputInputIsolationLH󰀑󰀑XXStore A and B DataXH󰀑H or LXXInputNot SpecifiedStore A, Hold BHH󰀑󰀑XXInputOutputStore A in Both RegistersLXH

or

L󰀑XXNot SpecifiedInputHold A, Store BLL󰀑󰀑XXOutputInputStore B in Both RegistersLLXXXLOutputInputReal-Time B Data to A BusLLXH or LXHStore B Data to A BusHHXXLXInputOutputReal-Time A Data to B BusHHH or LXHXStored A Data to B BusHLH or LH or LHHOutputOutputStored A Data to B Bus andStored B Data to A Bus元器件交易网www.cecb2b.com3www.fairchildsemi.com74F651

• 74F652Functional DescriptionIn the transceiver mode, data present at the HIGH imped-ance port may be stored in either the A or B register orboth.The select (SAB, SBA) controls can multiplex stored andreal-time.The examples in Figure 1 demonstrate the four fundamen-tal bus-management functions that can be performed withthe Octal bus transceivers and receivers.Data on the A or B data bus, or both can be stored in theinternal D flip-flop by LOW-to-HIGH transitions at theappropriate Clock Inputs (CPAB, CPBA) regardless of theSelect or Output Enable Inputs. When SAB and SBA are inthe real time transfer mode, it is also possible to store datawithout using the internal D flip-flops by simultaneouslyenabling OEAB and OEBA. In this configuration each Out-put reinforces its Input. Thus when all other data sources tothe two sets of bus lines are in a HIGH impedance state,each set of bus lines will remain at its last state.

Note A: Real-TimeTransfer Bus B to Bus ANote B: Real-TimeTransfer Bus A to Bus B

Note C: StorageNote D: Transfer StorageData to A or B

FIGURE 1. OEABOEBACPABCPBASABSBALLXXXLOEABOEBACPABCPBASABSBAHHXXLX

OEABOEBACPABCPBASABSBAXH󰀑XXXLXX󰀑XXLH󰀑󰀑XXOEABOEBACPABCPBASABSBAHLH or LH or LHX元器件交易网www.cecb2b.comwww.fairchildsemi.com474F651 • 74F652Logic Diagrams74F652Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.74F651

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.元器件交易网www.cecb2b.com5www.fairchildsemi.com74F651

• 74F652Absolute Maximum Ratings(Note 2)Recommended OperatingConditions

Note 2: Absolute maximum ratings are values beyond which the devicemay be damaged or have its useful life impaired. Functional operationunder these conditions is not implied.Note 3: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical CharacteristicsStorage Temperature−65°C to +150°CAmbient Temperature under Bias−55°C to +125°CJunction Temperature under Bias−55°C to +150°CVCC Pin Potential to Ground Pin−0.5V to +7.0VInput Voltage (Note 3)−0.5V to +7.0VInput Current (Note 3)−30 mA to +5.0 mAVoltage Applied to Outputin HIGH State (with VCC = 0V)Standard Output−0.5V to VCC3-STATE Output−0.5V to +5.5VCurrent Applied to Outputin LOW State (Max)twice the rated IOL (mA)ESD Last Passing Voltage (Min)4000VFree Air Ambient Temperature0°C to +70°CSupply Voltage+4.5V to +5.5V