633478Nand_Flash(samsung)

K9XXG08UXAINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document Title1G x 8 Bit / 2G x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.00.1RemarkAdvance PreliminaryHistory1. Initial issue1. Leaded part is eliminated2. tRHW is definedDraft DateNov. 09. 2005Jan. 10. 2006GENERAL DESCRIPTIONFEATURES• Voltage Supply - 2.70V ~ 3.60V • Organization- Memory Cell Array : (1G + 32M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 25µs(Max.) - Serial Access : 25ns(Min.)1G x 8 Bit / 2G x 8 Bit NAND Flash Memory• Fast Write Cycle Time- Page Program time : 200µs(Typ.) - Block Erase Time : 1.5ms(Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology- Endurance : 100K Program/Erase Cycles (with 1bit/512Byte ECC)- Data Retention : 10 Years • Command Driven Operation• Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package :- K9K8G08U0A-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1A-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1A-ICB0/IIB052 - Pin TLGA (12 x 17 / 1.0 mm pitch)Offered in 1G x 8bit, the K9K8G08U0A is a 8G-bit NAND Flash Memory with spare 256M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K8G08U0A ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K8G08U0A is an optimum solu-tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. An ultra high density solution having two 8Gb stacked with two chip selects is also available in standard TSOPI package.PRODUCT LISTPart NumberVcc RangeOrganizationPKG Type K9K8G08U0A-P 2.70 ~ 3.60VX8TSOP1 K9WA G08U1A-P K9WA G08U1A-I52TLGA1.001.001.001.002.007 6 5 4 3 2 11.001.001.0012.00±0.10#A117.00±0.1017.00±0.10BA12.00±0.10(Datum B)(Datum A)12.0010.002.502.502.000.501.30A B C DEF GHJ K L M N12-∅1.00±0.0541-∅0.70±0.05Side View1.0(M a x .)0.10 C17.00±0.10Top ViewBottom ViewABC D EF G H J KL M N7654321K9WAG08U1A - ICB0 / IIB052-TLGA (measured in millimeters)NCNCNCNCNCNCNCNCNC NCNCNCNCNCNC NCVccVcc VssVssVss /RE1/RE2/CE1/CE2CLE1CLE2ALE1ALE2/WE1/WE2/WP1/WP2R/B1R/B2VssIO0-1IO0-2IO1-1IO1-2IO2-1IO3-1IO2-2IO3-2IO4-1IO4-2IO5-1IO5-2IO6-1IO6-2IO7-1IO7-2∅ABC M 0.1∅ABC M 0.1PACKAGE DIMENSIONSPIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CE / CE1CHIP ENABLEThe CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase operation.Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation. CE2CHIP ENABLEThe CE2 input enables the second K9K8G08U0AREREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/B / R/B1READY/BUSY OUTPUTThe R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.Product IntroductionThe K9K8G08U0A is a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-sists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0A. The K9K8G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1056M byte physical space requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K8G08U0A.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.The K9WAG08U1A is composed of two K9K8G08U0A chips which are selected separately by each CE1 and CE2. Therefore, in terms of each CE, the basic operation of K9WAG08U1A is same with K9K8G08U0A except some AC/DC charateristics.Table 1. Command SetsFunction1st Cycle2nd Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hTwo-Plane Page Program(4)80h---11h81h---10hCopy-Back Program85h10hTwo-Plane Copy-Back Program(4)85h---11h81h---10hBlock Erase60h D0hTwo-Plane Block Erase60h---60h D0hRandom Data Input(1)85h-Random Data Output(1)05h E0hRead Status70h ORead EDC Status(2)7Bh OChip1 Status(3)F1h OChip2 Status(3)F2h ONOTE : 1. Random Data Input/Output can be executed in a page.2. Read EDC Status is only available on Copy Back operation.3. Interleave-operation between two chips is allowed.It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.4.Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .Caution : Any undefined command inputs are prohibited except for above command set of Table 1.DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.3. The typical value of the K9WAG08U1A’s I SB 2 is 40µA and the maximum value is 200µA.4. The maximum value of K9WAG08U1A-P’s I LI and I LO is ±40µA , the maximum value of K9WAG08U1A-I’s I LI and I LO is ±20µA .ParameterSymbol Test ConditionsMinTypMaxUnitOperating CurrentPage Read withSerial Access I CC 1tRC=25nsCE=V IL, I OUT =0mA-2535mAProgramI CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -20100µAInput Leakage Current I LI V IN =0 to Vcc(max)--±20Output Leakage Current I LO V OUT =0 to Vcc(max)--±20Input High VoltageV IH (1)-0.8xVcc -Vcc+0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH I OH =-400µA 2.4--Output Low Voltage Level V OL I OL =2.1mA --0.4Output Low Current(R/B)I OL (R/B)V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9XXG08UXA-XCB0 :T A =0 to 70°C, K9XXG08UXA-XIB0:T A =-40 to 85°C)ParameterSymbol Min Typ.Max Unit Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSVABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit Voltage on any pin relative to VSSV CC -0.6 to +4.6VV IN -0.6 to +4.6V I/O-0.6 to Vcc+0.3 (<4.6V)Temperature Under Bias K9XXG08UXA-XCB0T BIAS -10 to +125°C K9XXG08UXA-XIB0-40 to +125Storage Temperature K9XXG08UXA-XCB0T STG-65 to +150°CK9XXG08UXA-XIB0Short Circuit CurrentI OS5mACAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested. K9WAG08U1A-IXB0’s capacitance(I/O, Input) is 20pF.ItemSymbol Test ConditionMin MaxUnit K9K8G08U0AK9WAG08U1A*Input/Output Capacitance C I/O V IL =0V -2040pF Input CapacitanceC INV IN =0V-2040pFVALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.* : Each K9K8G08U0A chip in the K9WAG08U1A has Maximun 160 invalid blocks.ParameterSymbol Min Typ.Max Unit K9K8G08U0A N VB 8,032-8,192Blocks K9WAG08U1AN VB16,064*-16,384*BlocksAC TEST CONDITION(K9XXG08UXA-XCB0: T A =0 to 70°C, K9XXG08UXA-XIB0:T A =-40 to 85°C ,K9XXG08UXA: Vcc=2.7V~3.6V unless otherwise noted)ParameterK9XXG08UXA Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pF (K9K8G08U0A-P/K9WAG08U1A-I) 1 TTL GATE and CL=30pF (K9WAG08U1A-P)MODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(5clock)H L L H H Write Mode Command Input L H L H H Address Input(5clock)L L L HH Data Input L L L H X Data Output X X X X H X During Read(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-byProgram / Erase CharacteristicsParameter Symbol Min Typ Max Unit Program Time t PROG-200700µs Dummy Busy Time for Two-Plane Page Program t DBSY-0.51µs Number of Partial Program Cycles Nop--4cycles Block Erase Time t BERS- 1.52msNOTE : 1. Typical value is measured at Vcc=3.3V, T A=25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C tempera-ture.AC Timing Characteristics for Command / Address / Data InputParameter Symbol Min Max UnitCLE Setup Time t CLS(1)12-nsCLE Hold Time t CLH5-nsCE Setup Time t CS(1)20-nsCE Hold Time t CH5-nsWE Pulse Width t WP12-nsALE Setup Time t ALS(1)12-nsALE Hold Time t ALH5-nsData Setup Time t DS(1)12-nsData Hold Time t DH5-nsWrite Cycle Time t WC25-nsWE High Hold Time t WH10-nsAddress to Data Loading Time t ADL(2)70-nsNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycleAC Characteristics for OperationParameter Symbol Min Max Unit Data Transfer from Cell to Register t R-25µs ALE to RE Delay t AR10-ns CLE to RE Delay t CLR10-ns Ready to RE Low t RR20-ns RE Pulse Width t RP12-ns WE High to Busy t WB-100ns Read Cycle Time t RC25-ns RE Access Time t REA-20ns CE Access Time t CEA-25ns RE High to Output Hi-Z t RHZ-100ns CE High to Output Hi-Z t CHZ-30ns RE High to Output hold t RHOH15-ns RE Low to Output hold t RLOH5-ns CE High to Output hold t COH15-ns RE High Hold Time t REH10-ns Output Hi-Z to RE Low t IR0-ns RE High to WE Low t RHW100-ns WE High to RE Low t WHR60-ns Device Resetting Time(Read/Program/Erase)t RST-5/10/500(1)µs NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.NAND Flash Technical NotesIdentifying Initial Invalid Block(s)Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /512Byte ECC.All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2048 Figure 3. Flow chart to create initial invalid block table.StartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableNAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionNAND Flash Technical Notes (Continued)Copy-Back Operation with EDC & Sector Definition for EDCGenerally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors.K9K8G08U0A supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area."A" area 512 Byte(1’st sector)"H" area (4’th sector)Main Field (2,048 Byte)16 Byte"G" area (3’rd sector)16 Byte "F" area (2’nd sector)16 Byte "E" area (1’st sector)16 Byte "B" area 512 Byte(2’nd sector)"C" area 512 Byte(3’rd sector)"D" area 512 Byte(4’th sector)Spare Field (64 Byte)Table 2. Definition of the 528-Byte SectorSector Main Field (Column 0~2,047)Spare Field (Column 2,048~2,111)Area NameColumn AddressArea NameColumn Address 1’st 528-Byte Sector "A"0 ~ 511"E"2,048 ~ 2,0632’nd 528-Byte Sector "B"512 ~ 1,023"F"2,064 ~ 2,0793’rd 528-Byte Sector "C"1,024 ~ 1,535"G"2,080 ~ 2,0954’th 528-Byte Sector"D"1,536 ~ 2,047"H"2,096 ~ 2,111Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-nificant bit) pages of the block. Random page address programming is prohibited.From the LSB page to MSB page DATA IN: Data (1)Data (64)(1)(2)(3)(32)(64)Data register Page 0Page 1Page 2Page 31Page 63Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)(2)(32)(3)(1)(64)Data registerPage 0Page 1Page 2Page 31Page 63Addressing for program operation::::Interleave Page ProgramK9K8G08U0A is composed of two K9F4G08U0As. K9K8G08U0A provides interleaving operation between two K9F4G08U0As.This interleaving page program improves the system throughput almost twice compared to non-interleaving page program.At first, the host issues page program command to one of the K9F4G08U0A chips, say K9F4G08U0A(chip #1). Due to this K9K8G08U0A goes into busy state. During this time, K9F4G08U0A(chip #2) is in ready state. So it can execute the page program command issued by the host.After the execution of page program by K9F4G08U0A(chip #1), it can execute another page program regardless of the K9F4G08U0A(chip #2). Before that the host needs to check the status of K9F4G08U0A(chip #1) by issuing F1h command. Only when the status of K9F4G08U0A(chip #1) becomes ready status, host can issue another page program command. If the K9F4G08U0A(chip #1) is in busy state, the host has to wait for the K9F4G08U0A(chip #1) to get into ready state.Similarly, K9F4G08U0A chip(chip #2) can execute another page program after the completion of the previous program. The host can monitor the status of K9F4G08U0A(chip #2) by issuing F2h command. When the K9F4G08U0A(chip #2) shows ready state, host can issue another page program command to K9F4G08U0A(chip #2).This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip individually. This reduces the time lag for the completion of operation.NOTES : During interleave operations, 70h command is prohibited.R / B (#1)b u s y o f C h i p #1I /O X80h10h C o m m a n d A 30 : L o w A d d & D a t a80h 10h A 30 : H i g h A d d & D a t ab u s y o f C h i p #2i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /BI n t e r l e a v e P a g e P r o g r a m≈≈≈F 1h o r F 2h A B CDa n o t h e r p a g e p r o g r a m o n C h i p #1S t a t e A : C h i p #1 i s e x e c u t i n g a p a g e p r o g r a m o p e r a t i o n a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a p a g e p r o g r a m c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g p a g e p r o g r a m o p e r a t i o n .S t a t e C : P a g e p r o g r a m o n c h i p #1 i s t e r m i n a t e d , b u t p a g e p r o g r a m o n c h i p #2 i s s t i l l o p e r a t i n g . A n d t h e s y s t e m s h o u l d i s s u e F 1h c o m m a n d t o d e t e c t t h e s t a t u s o f c h i p #1. I f c h i p #1 i s r e a d y , s t a t u s I /O 6 i s "1" a n d t h e s y s t e m c a n i s s u e a n o t h e r p a g e p r o g r a m c o m m a n d t o c h i p #1.S t a t e D : C h i p #1 a n d C h i p #2 a r e r e a d y .A c c o r d i n g t o t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e p a g e p r o g r a m o n c h i p #1 a n d c h i p #2 a l t e r n a t e l y .S t a t u sO p e r a t i o nS t a t u s C o m m a n d / D a t aF 1hF 2hAC h i p 1 : B u s y , C h i p 2 : R e a d y8x hC x hBC h i p 1 : B u s y , C h i p 2 : B u s y8x h8x hCC h i p 1 : R e a d y , C h i p 2 : B u s yC x h8x hDC h i p 1 : R e a d y , C h i p 2 : R e a d yC x hC x hR / B (#1)b u s y o f C h i p #1I /O X60hD 0h C o m m a n d A 30 : L o w A d d60h D 0h A 30 : H i g h A d db u s y o f C h i p #2i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /BI n t e r l e a v e B l o c k E r a s e≈≈≈F 1h o r F 2h A B CDa n o t h e r B l o c k E r a s e o n C h i p #1S t a t e A : C h i p #1 i s e x e c u t i n g a b l o c k e r a s e o p e r a t i o n , a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a b l o c k e r a s e c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g b l o c k e r a s e o p e r a t i o n .S t a t e C : B l o c k e r a s e o n c h i p #1 i s t e r m i n a t e d , b u t b l o c k e r a s e o n c h i p #2 i s s t i l l o p e r a t i n g . A n d t h e s y s t e m s h o u l d i s s u e F 1h c o m m a n d t o d e t e c t t h e s t a t u s o f c h i p #1. I f c h i p #1 i s r e a d y , s t a t u s I /O 6 i s "1" a n d t h e s y s t e m c a n i s s u e a n o t h e r b l o c k e r a s e c o m m a n d t o c h i p #1.S t a t e D : C h i p #1 a n d C h i p #2 a r e r e a d y .A c c o r d i n g t o t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e b l o c k e r a s e o n c h i p #1 a n d c h i p #2 a l t e r n a t e l y .S t a t u sO p e r a t i o nS t a t u s C o m m a n d / D a t aF 1hF 2hAC h i p 1 : B u s y , C h i p 2 : R e a d y8x hC x hBC h i p 1 : B u s y , C h i p 2 : B u s y8x h8x hCC h i p 1 : R e a d y , C h i p 2 : B u s yC x h8x hDC h i p 1 : R e a d y , C h i p 2 : R e a d yC x hC x h。

1Nandflash工作原理Nand flash工作原理S3C2410板的Nand Flash支持由两部分组成：Nand Flash控制器(集成在S3C2410 CPU)和Nand Flash存储芯片(K9F1208U0B)两大部分组成。

当要访问Nand Flash中的数据时,必须通过Nand Flash控制器发送命令才能完成。

所以, Nand Flash相当于S3C2410的一个外设,而不位于它的内存地址区.1.1 Nand flash芯片工作原理Nand flash芯片型号为Samsung K9F1208U0B，数据存储容量为64MB，采用块页式存储管理。

8个I/O引脚充当数据、地址、命令的复用端口。

1.1.1 芯片内部存储布局及存储操作特点一片Nand flash为一个设备(device), 其数据存储分层为：1设备(Device) = 4096 块(Blocks)1块(Block) = 32页/行(Pages/rows) ;页与行是相同的意思,叫法不一样1块(Page) = 528字节(Bytes) = 数据块大小(512Bytes) + OOB 块大小(16Bytes)在每一页中，最后16个字节（又称OOB）用于Nand Flash命令执行完后设置状态用，剩余512个字节又分为前半部分和后半部分。

可以通过Nand Flash命令00h/01h/50h分别对前半部、后半部、OOB进行定位通过Nand Flash内置的指针指向各自的首地址。

存储操作特点：1. 擦除操作的最小单位是块。

2. Nand Flash芯片每一位(bit)只能从1变为0，而不能从0变为1，所以在对其进行写入操作之前要一定将相应块擦除(擦除即是将相应块得位全部变为1).3. OOB部分的第六字节(即517字节)标志是否是坏块，如果不是坏块该值为FF，否则为坏块。

4. 除OOB第六字节外，通常至少把OOB的前3个字节存放Nand Flash硬件ECC码(关于硬件ECC 码请参看Nandflash 控制器一节).1.1.2 重要芯片引脚功能I/O0I/O7：复用引脚。

君正Nand Flash烧录器手册Revision: 1.0Date: June 2008君正Nand Flash烧录器手册Copyright © Ingenic Semiconductor Co. Ltd 2006. All rights reserved.Release historyDate Revision ChangeJune 2008 1.0 First releaseDisclaimerThis documentation is provided for use with Ingenic products. No license to Ingenic property rights is granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to the usage, or intellectual property right infringement except as provided for by Ingenic Terms and Conditions of Sale.Ingenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment.All information in this document should be treated as preliminary. Ingenic may make changes to this document without notice. Anyone relying on this documentation should contact Ingenic for the current documentation and errata.Ingenic Semiconductor Co. LtdE801C, Power Creative Building,No.1, Shangdi East Road,Haidian District, Beijing 100085, ChinaTel: 86-10-58851002Fax: 86-10-58851005Http: //容君正NAND Flash烧录器手册Copyright® 2005-2008 Ingenic Semiconductor Co., Ltd. All rights reserved. i内容1概述 (1)2烧录器硬件说明 (3)3烧录器软件使用说明 (5)3.1功能说明 (5)3.2使用准备 (5)3.3命令行用法 (6)3.4配置文件详解 (7)3.5将配置编译在内部 (8)3.6错误处理 (9)3.7边缘情况的考虑 (9)概述君正NAND Flash烧录器手册Copyright® 2005-2008 Ingenic Semiconductor Co., Ltd. All rights reserved. 11 概述北京君正提供Nand Flash烧录器的参考设计，主要用于产品阶段的Nand Flash烧录。

N S S D(NAND Flash-based Solid State Drive)Module TypeProduct Data sheetVersion 1.0July 2007INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or sim-ilar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document TitleSAMSUNG NAND Flash-based Solid State Drive Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. And SAMSUNG Electronics has the right to change all the specifications in data sheets. SAMSUNG Electronics will evaluate and reply to any dear customer‘s requests and questions on the parameters of this device. If dear customer has any questions, please call or fax to Memory Product Planning Team, or contact the SAMSUNG branch office near your officeRevision No0.00.11.01.1History Initial issueInterface information(ATA7->ATA5) was temporarily changed before updating (6 page,11 page)Performance information was updatedSustained Data Read : 56MB/s -> 57MB/s (6 page)Sustained Data Write : 40MB/s -> 38MB/s (6 page)Sequential Read Sector : 56MB/s -> 57MB/s (11 page)Sequentail Write Sector : 40MB/s -> 38MB/s (11 page)Random Read Sector : 56MB/s -> 57MB/s(11 page)Identify Device Data was updated according to current FW ver-sion(57 page)Part number of Slim 48GB is set as TBD (63page)At 6 page- Performance : Sandra2007-> HD Bench- Active : typical 200mA -> Active : typical 150mA - Idle : typical 20mA -> Standby : typical 10mA - Standby : typical 20mA -> Sleep : typical 10mA - MTBF 1,000,000 Hours -> MTBF 2,000,000 Hours - Maxium Weight was added : 19g(8/16/32/48/64GB)At 11 page- Performace : Sandra2007-> HD Bench - Random Read Sector : 57MB/s -> 52MB/s - Random Write Sector : 17MB/s -> 13MB/s - Active 200mA -> Active 150mA - Idle : 20mA -> Standby : 10mA - Standby : 20mA -> Sleep : 10mA- MTBF 1,000,000 Hours -> 2,000,000 Hours - Non-Operating : -40’C ~ 85’C -> -55’C ~ 95’C At 60 pageThere was a misprintD1HR1 : Set_status -> D0SR2 : Sample_PDIAG-t=31ms -> t=6sAt page 6- NSSD Functional Block Diagram is modified.Draft Date Mar.29.2007Apr.07.2007Jul.06.2007Jul.31.2007Remark Preliminary PreliminaryFinalTABLE OF CONTENTS1. General Description2. Physical Specifications2.1 Slim Type Physical Dimensions(16/32GB)2.2 Slim Type Physical Dimensions(48/64GB)3. Product Specifications3.1 System Interface and Configuration3.2 System Performance3.3 System Power Consumption3.4 System Reliability3.5 Environmental Specifications4. Electrical Specifications4.1 ZIF Connector Dimensions4.2 Pin Assignment4.3 Signal Descriptions4.4 DC Characteristics4.4.1 Absolute Maximum Ratings4.4.2 Recommended Operating Conditions4.4.3 Electrical Characteristics4.5 AC Characteristics4.5.1 Register Transfers4.5.2 PIO Data Transfers4.5.3 Multiword DMA Data Transfer4.5.3.1 Initiating a Multiword DMA data burst4.5.3.2 Sustaining a Multiword DMA data burst4.5.3.3 Device terminating a Multiword DMA data burst 4.5.3.4 Host terminating a Multiword DMA data burst4.5.4 Ultra DMA Data Transfer4.5.4.1 Initiating an Ultra DMA data-in burst4.5.4.2 Sustained Ultra DMA data-in burst4.5.4.3 Host pausing an Ultra DMA data-in burst4.5.4.4 Device terminating an Ultra DMA data-in burst 4.5.4.5 Host terminating an Ultra DMA data-in burst4.5.4.6 Initiating an Ultra DMA data-out burst4.5.4.7 Sustained Ultra DMA data-out burst4.5.4.8 Device pausing an Ultra DMA data-out burst4.5.4.9 Host terminating an Ultra DMA data-out burst4.5.4.10 Device terminating an Ultra DMA data-out burst5. ATA Registers5.1 I/O Register Descriptions5.2 Alternate Status Register5.2.1 Address5.2.2 Direction5.2.3 Access Restrictions5.2.4. Effect5.2.5 Functional Description5.3 Command Register5.3.1 Address5.3.2 Direction5.3.3 Access Restrictions5.3.4 Effect5.3.5 Functional description5.3.6 Field/bit description5.4 Cylinder High Register5.4.1 Address5.4.2 Direction5.4.3 Access Restrictions5.4.4 Effect67 7 911 11 11 11 11 11 12 12 12 13 14 14 14 14 15 15 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 35 35 35 35 35 35 35 36 36 36 36 36 36 36 37 37 37 37 37TABLE OF CONTENTS5.4.5 Functional description5.5 Cylinder Low Register5.5.1 Address5.5.2 Direction5.5.3 Access Restrictions5.5.4 Effect5.5.5 Functional description5.6 Data Port5.6.1 Address5.6.2 Direction5.6.3 Access Restrictions5.6.4 Effect5.6.5 Functional description5.6.6 Field/bit description5.7 Data Register5.7.1 Address5.7.2 Direction5.7.3 Access Restrictions5.7.4 Effect5.7.5 Functional description5.7.6 Field/bit description5.8 Device Control Register5.8.1 Address5.8.2 Direction5.8.3 Access Restrictions5.8.4 Effect5.8.5 Functional description5.8.6 Field/bit description5.9 Device/Head Register5.9.1 Address5.9.2 Direction5.9.3 Access Restrictions5.9.4 Effect5.9.5 Functional description5.9.6 Field/bit description5.10 Error Register5.10.1 Address5.10.2 Direction5.10.3 Access Restrictions5.10.4 Effect5.10.5 Functional description 5.10.6 Field/bit description5.11 Features Register5.11.1 Address5.11.2 Direction5.11.3 Access Restrictions5.11.4 Effect5.11.5 Functional description 5.12 Sector Count Register5.12.1 Address5.12.2 Direction5.12.3 Access Restrictions5.12.4 Effect5.12.5 Functional description 5.13 Sector Number Register5.13.1 Address5.13.2 Direction5.13.3 Access Restrictions5.13.4 Effect5.13.5 Functional description 5.14 Status Register 37 38 38 38 38 38 38 38 38 38 39 39 39 39 40 40 40 40 40 40 40 41 41 41 41 41 41 41 42 42 42 42 42 42 42 43 43 43 43 43 43 43 44 44 44 44 44 44 45 45 45 45 45 45 46 46 46 46 46 46 47TABLE OF CONTENTS5.14.1 Address5.14.2 Direction5.14.3 Access Restrictions5.14.4 Effect5.14.5 Functional description5.14.6 Field/bit description5.14.6.1 BSY(Busy)5.14.6.2 DRDY(Device ready)5.14.6.3 Command dependent5.14.6.4 DRQ(Data request)5.14.6.5 Obsolete bits5.14.6.6 ERR(Error)6. Command Descriptions6.1 Supporting ATA Command Set6.2 Security Feature Set6.2.1 Securtity mode default setting6.2.2 Initial setting of the user password6.2.3 Security mode operation from power-on6.2.4 Password lost6.3 SMART Feature Set6.3.1 Sub Command Set6.3.2 SMART Data Structure(READ DATA(Doh)) 6.3.3 Threshold Sector Size6.4 R/B Status in SLEEP command6.5 SET FEATURES6.5.1 SET FEATURES Register Value6.6 SET MAX6.6.1 SET MAX FEATURES Register Value6.7 Identify Device Data6.8 Hardware Reset State Diagram6.9 Software Reset State Diagram7. Ordering Information8. Product Line-up 47 47 47 47 47 47 48 49 49 49 49 50 51 51 52 52 52 52 52 53 53 53 54 54 55 55 56 56 57 59 60 62 63The NSSD(Nand Flash-based Solid State Drive) of Samsung Electronics is fully consist of semiconductor device and using NAND Flash Memory which has a high reliability and a high technology for a storage media.As the NSSD doesn't have a moving parts such as platter(disk) and head media, it gives a good solution in a sub. note PC and Tablet PC for a storage device with a high performance and a power consumption and a small form factor.Also it gives rugged features in industrial PC with an extreme environment and an increased MTBF.For an easy adoption, the NSSD has a same host interface with HDD and has a same physical dimension.•Density− 16GB,32GB,48GB,64GB NSSD are available•Form Factor− Slim Type (53.60 x 70.60 x 3.00mm) :32/48/64GB (53.60 x 70.60 x 2.50mm) : 16GB•Host interface − PIO Mode 0 to 4. − Multiword DMA− Up to ATA5 UDMA Mode4 (66MHz)•Performance− Host Interface : Max 66MB/s− Sustained Data Read : Max 57MB/s ※ − Sustained Data Write : Max 38MB/s ※(※HD-Bench )•Power consumption− Active : Typical 150mA − Standby : Typical 10mA − Sleep : Typical 10mA •Temperature− Operating : -25'C ~ 85'C•Shock− Operating : 1500G, duration 0.5ms, Half Sine Wave− Vibration : 20G Peak, 10~2000Hz,(12Cycle/Axis)x3 Axis •MTBF− 2,000,000 Hours •Maxium Weight− 19g (16/32/48/64GB)1. General Description•NSSD Functional Block DiagramHOSTFlash Memory Controllerx16x16Flash Memory Flash Memory Flash MemoryFlash Memory Flash MemoryFlash Memory Flash MemoryFlash Memory x8x8x8x8x1653.60Figure 2. Slim Type(16/32) Bottom70.60R 0.5Figure 3. Slim Type(16GB) SideIC ChipNAND2.50±0.150.681.20PCBNAND5.55.55.55.55.52.53.08.52.01.051.75Figure 4. Slim Type(32GB) SideNAND 2.35PCBNANDConnector3.00±0.150.6853.60Figure 6. Slim Type(48/64GB) Bottom70.60R 0.5Figure 7. Slim Type(48/64GB) SideNAND 2.35PCBNAND5.55.55.55.55.52.53.08.52.01.05Connector3.00±0.150.68(HD BENCH, 64GB)Read / Write Performance(MB/s)Random Read Sector Max 52Random Write Sector Max 13Sequential Read Sector Max 57Sequential Write SectorMax 38(64GB)Current Typical(mA)Active 150Standby 10Sleep10• PIO 0~4 mode,•Up to ATA5 and UDMA mode4(Ultra DMA66)• Fully compatible with ATA5 SpecificationMTBF2,000,000 Hours3.1 System Interface and Configuration3.2 System Performance 3.4 System Reliability3.3 System Power Consumption 3. Product SpecificationsFeatures Operating Non-Operating Temperature -25’C ~ 85’C-55’C ~ 95’CHumidity 0’C to 55’C / 90~98% RH, 10cyclesVibration 20G Peak, 10 ~ 2000Hz, (12cycle / Axis) x3 Axis Shock1500G, duration 0.5ms, Half Sine Wave3.5 Environmental Specifications4.1 ZIF Connector Dimensions4.2 Pin AssignmentPin No Signals Pin No Signals 1Reserved 21GROUND 2Reserved 22DMARQ 3RESET 23GROUND 4GROUND 24DIOW 5DD725DIOR 6DD826GROUND 7DD627IORDY 8DD928GROUND 9DD529DMACK 10DD1030INTRQ 11DD431DA112DD1132PDIAG 13DD333DA014DD1234DA215DD235CS016DD1336CS117DD137DASP 18DD1438 3.3V 19DD039 3.3V 20DD1540Reserved0.5±0.1019.5022.004.002.071.174.930.9±0.10Contact No. 1Figure 8. Connector Top Figure 9. Connector Side*ZIF: Zero Insertion Force4. Electrical SpecificationSignal name Pin NO Type DescriptionRESET3I This is a reset signal output from the host system and to be used for inter-face logic circuit.DD0 - DD155-20I/O This is a 16bit bi-directional data bus. The lover 8 bits are used for register acess other that data register.DIOW24I This rising edge of this Write Strobe signal clocks data from the host data bus into a register on the device.STOP*Assertion of this signal by the host during an Ultra DMA burst signals the termination of the Ultra DMA burst.DIOR25I Activating this Read Strobe signal enables data from a register on the device to be clocked onto the host data bus. The rising edge of this signal latches data at the host.HDMARDY*This signal is a flow control signal for Ultra DMA Read. Host asserts this signal, and indicates that the host is ready to receive Ultra DMA read data.HSTROBE*This signal is Write data strobe signal from the host for an Ultra DMA Write. Both the rising and falling edge latch the data from DD(15:0) into the device.IORDY27O This signal is used to temporarily stop the host register access(read or write) when the device is not ready to respond to a data transfer request.DDMARDY*This signal is flow control signal for Ultra DMA Write. Device asserts this signal, and indicates that the device is ready to receive Ultra DMA Write data.DSTROBE*This signal is the data in strobe signal from the device for an Ultra DMA Read. Both the rising and falling edge latch the data from DD(15:0) into the host.INTRQ30O This is an interrupt signal for the host system. This signal is asserted by a selected device when the nIEN bit in the Device Control Register is "0". In other cases, this signal should be a high impedance state.DA0-231,33,34I This is a register address signal from the host system.PDIAG:CBLID*32I/O The host shall wait until the power on or hardware reset sequence is com-plete for all devices on the cable;CS035I This device chip selection signal is used to select the Control Block Regis-ters from the host system.CS136I This device chip selection signal is used to select the Command Block Registers from the host system.DASP37I/O This signal indicates that a device is active when the power is turned on. Upon receipt of a command from the host, the device asserts this signal. At command completion, the device de-asserts this signal.DMARQ22O The device shall assert this signal, used for DMA data transfers between host and device, when it is ready to transfer data.DMACK29I The host in response to DMARQ to either acknowledge that data has been accepted, or that data is available shall use this signal.DEVADR40I The device is configured as either Device 0(Master) or Device 1(Slave) depending upon the signal level of 40 pin DEVADR signal.- When used as Device 1(Master), DEVADR is open- When used as Device 1(Slave), the host shall have pull-up resistor. Rec-ommended pull-up register is 10K ohm based on +3.3Vcc."I" of I/O type represents an input signal from the device and "O" represents an output signal from the device.4.3 Signal Descriptions4.4.1 Absolute Maximum RatingsCharacteristicsSymbol Rating Unit DC Supply Voltage V DD -0.3 to 4.6V Input/Output Voltage V IN /V OUT3.8V DC Input Current I IN +/- 200mAStorage TemperatureT STG-40 to 85°C4.4.2 Recommended Operating ConditionsCharacteristicsSymbol Rating Unit DC Supply Voltage V DD 3.0 to 3.6V Input/Output Voltage V IN /V OUT 3.0 to 3.6VOperating TemperatureT OPR-25 to 85°C4.4.3 Electrical Characteristics - Normal I/OVdd = 3.0 to 3.6(V), Ta = 25(°C), Vext = 5V ± 0.25VNOTE :* Schmitt Trigger test condition : V DD = 3.0 to 3.6(V), Ta = 25(°C)Characteristic :These DC parameters guarantee the I/O cell characteristic at the static state only, not at the dynamic state.CharacteristicsSymbol Test ConditionMin Typ Max Unit Input High Current I IH V IN = V DD Pull - Down Normal Down -1010--1060uA uA Input Low Current I IL V IN = V SS Pull - UpNormal Up-10-60--10-10uA uA Input High Voltage V IH CMOS 2.0--V Input Low Voltage V IL CMOS--0.8V Output High Voltage V OH 6mA Buffer, I OH = -6mA 2.4--V Output Low VoltageV OL 6mA Buffer, I OL = 6mA --0.4V Tri-state Output Leakage CurrentI OZV OUT = V DD or V SS-10-10uA4.4 DC CharacteristicsFigure 1 defines the relationships between the interface signals for register transfers. Peripherals reporting support for PIO mode 3 or 4 shall power-up in a PIO mode 0,1, or 2.For PIO modes 3 and above, the minimum value of t 0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 1defines the minimum value that shall be placed in word 68.Both hosts and devices shall support IORDY when PIO mode 3 or 4 are the currently selected mode of operation.DIOR-/DIOW-WRITE DD(7:0)READ DD(7:0)IORDYt 1ADDR valid t 2(See note 1)(See note 2)(See note 2)(See note 3,3-2)IORDY(See note 3,3-1)IORDY(See note 3,3-3)t 9t 0t 3t 4t 5t 6t 6Zt At Ct RDt Bt CNOTE:1. Device address consists of signals CS0-, CS1- and DA(2:0)2. Data consists of DD(7:0)3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after t A from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases: 3-1. Device never negates IORDY , devices keeps IORDY released: no wait is generated. 3-2. Device negates IORDY before t A , but causes IORDY to be asserted before t A .IORDY is released prior to negation and may be asserted for no more than 5ns before release: no wait generated.3-3. Device negates IORDY before t A . IORDY is released prior to negation and may be asserted for no more than 5ns before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on DD(7:0) for t RD before asserting IORDY .4. DMACK- shall remain negated during a register transfer.Figure 1. Register transfer to/from device.t 2i4.5.1 Register Transfers4.5 AC CharacteristicsTable 1 - Register transfer to/from deviceNOTE :1. t 0 is the minimum total cycle time, t 2 is the minimum DIOR-/DIOW- assertion time, and A host implementation shall lengthen t 2 and/or t 2i to ensure that t 0 is equal to or greater than the value reported in the devices INDENTIFY DEVICE data. A device implementation shall support any legal host implementation.2. This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is released by the device.3. The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY negated at the t A after the activation of DIOR- or DIOW-, then t 5 shall be met and t RD is not applicable. If the device is driving IORDY negated at the time t A after the activation of DIOR- or DIOW-, then t RD shall be met and t 5 is not applicable.4. ATA/ATAPI standards prior to ATA/ATAPI-5 inadvertently specified an incorrect value for mode2 time t0 by utilizing the 16-bit PIO value.5. Mode shall be selected no faster than the highest mode supported by the slowest device.Register transfer timing parametersMode 0ns Mode 1ns Mode 2ns Mode 3ns Mode 4ns Note t 0Cycle time min 6003833301801201,4,5t 1Address valid to DIOR-/DIOW- setup min 7050303025t 2DIOR-/DIOW- pulse width 8bit min 29029029080701t 2i DIOR-/DIOW- recovery time min ---70251t 3DIOW- data setup min 6045303020t 4DIOW- data hold min 3020151010t 5DIOR- data setup min 5035202020t 6DIOR- data hold min 55555t 6Z DIOR- data tristate max 30303030302t 9DIOR-/DIOW- to address valid hold min 2015101010t RD Read Data Valid to IORDY active(if IORDY initially low after t A ) min00000t A IORDY setup time35353535353t B IORDY pulse width max 12501250125012501250t CIORDY assertion to releasemax 55555Figure 2 defines the relationships between the interface signals for PIO data transfers. Peripherals reporting support for PIO mode 3or 4 shall power-up in a PIO mode 0,1, or 2.For PIO modes 3 and above, the minimum value of t 0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 2defines the minimum value that shall be placed in word 68.IORDY shall be supported when PIO mode 3 or 4 are the current mode of operation.DIOR-/DIOW-WRITE DD(15:0)IORDYt 1ADDR valid t 2(See note 1)(See note 2)(See note 3,3-2)IORDY(See note 3,3-1)IORDY(See note 3,3-3)t 9t 0t 3t 4t 5t 6t 6Zt At C t RDt B t CNOTE:1. Device address consists of signals CS0-, CS1- and DA(2:0)2. Data consists of DD(15:0) for all devices except devices implementing the CFA feature set when 8-bit transfers is enabled. In that case, data consists of DD(7:0)3. The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle is to be extended is made by the host after t A from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases: 3-1. Device never negates IORDY , devices keeps IORDY released: no wait is generated. 3-2. Device negates IORDY before t A , but causes IORDY to be asserted before t A .IORDY is released prior to negation and may be asserted for no more than 5ns before release: no wait generated.3-3. Device negates IORDY before t A . IORDY is released prior to negation and may be asserted for no more than 5ns before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on DD(7:0) for t RD before asserting IORDY .4. DMACK- shall be negated during a PIO data transfer.Figure 2. PIO data transfer to/from device.DD(7:0)t 2iREAD DD(15:0)(See note 2)DD(7:0)4.5.2 PIO Data TransfersTable 2 - PIO data transfer to/from deviceNOTE :1. t 0 is the minimum total cycle time, t 2 is the minimum DIOR-/DIOW- assertion time, and t 21 is the minimum DIOR-/DIOW- negation time. A host imple-mentation shall lengthen t 2 and/or t 2i to ensure that t 0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.2. This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is released by the device.3. The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle is completed. If the device is not driving IORDY negated at the t A after the activation of DIOR- or DIOW-, then t 5 shall be met and t RD is not applicable. If the device is driving IORDY negated at the time t A after the activation of DIOR- or DIOW-, then t RD shall be met and t 5 is not applicable.4. Mode may be selected at the highest mode for the device if CS(1:0) and AD(2:0) do not change between read or write cycles or selected at the high-est mode supported by the slowest device if CS(1:0) or AD(2:0) do change between read or write cycles.PIO timing parametersMode 0ns Mode 1ns Mode 2ns Mode 3ns Mode 4ns Note t 0Cycle time min 6003832401801201,4t 1Address valid to DIOR-/DIOW- setup min 7050303025t 2DIOR-/DIOW- min 16512510080701t 2i DIOR-/DIOW- recovery time min ---70251t 3DIOW- data setup min 6045303020t 4DIOW- data hold min 3020151010t 5DIOR- data setup min 5035202020t 6DIOR- data hold min 55555t 6Z DIOR- data tristate max 30303030302t 9DIOR-/DIOW- to address valid hold min 2015101010t RD Read Data Valid to IORDY active(if IORDY initially low after t A ) min00000t A IORDY setup time35353535353t B IORDY pulse width max 12501250125012501250t CIORDY assertion to releasemax 555554.5.3 Multiword DMA Data TransfersFigure 3 through Figure 6 define the timing associated with Multiword DMA transfers.For Multiword DMA modes 1 and above, the minimum value of t0 is specified by word 65 in the IDENTIFY DEVICE parameter list. Table 3 defines the minimum value that shall be placed in word 65.Devices shall power-up with mode 0 as the default Multiword DMA mode.Table 3 - Multiword DMA data transferMultiword DMA timing parameters Mode 0ns Mode 1ns Mode 2ns Note t0Cycle time min480150120see note t D DIOR-/DIOW- asserted pulse width min2158070see note t E DIOR- data access max1506050t F DIOR- data hold min555t G DIOR-/DIOW-data setup min1003020t H DIOW- data hold min201510t I DMACK to DIOR-/DIOW- data setup min000t J DIOR-/DIOW- to DMACK hold min2055t KR DIOR- negated pulse width min505025see note t KW DIOW- negated pulse width min2155025see note t LR DIOR- to DMARQ delay max1204035t LW DIOW- to DMARQ delay max404035t M CS(1:0) valid to DIOR-/DIOW- min503025t N CS(1:0) hold min151010t Z DMACK- to read data released max202525NOTE:> t0 is the minimum total cycle time, t D is the minimum DIOR-/DIOW- assertion time, and t K (t KR or t Kw, as appropriate) is the minimum DIOR-/DIOW-negation time. A host shall lengthen t D and/or t K to ensure that t0 is equal to the value reported in the devices IDENTIFY DEVICE data.The values for the timings for each of the Multiword DMA modes are contained in Table 50.DMARQWRITE CS0-/CS1-DD(15:0)READ DD(15:0)t MFigure 3. Initiating a Multiword DMA data transferDIOR-/DIOW-DMACK-See noteSee notet Et Dt Gt Gt Ft HNOTE:The host shall not assert DMACK- or negate both CS0 and CS1 until the assertion of DMARQ is detected. The maxium time from the assertion of DMARQ to the assertion of DMACK- or the negation of both CS0 and CS1 is not defined.4.5.3.1 Initiating a Multiword DMA data burstThe values for the timings for each of the Multiword DMA modes are contained in Table 50.DMARQ WRITE CS0-/CS1-DD(15:0)READ DD(15:0)Figure 4. Sustaining a Multiword DMA data transferDIOR-/DIOW-DMACK-t Dt 0t Kt Et Gt Ft Et Gt Ft Gt Ht Gt H4.5.3.2 Sustaining a Multiword DMA data burstThe values for the timings for each of the Multiword DMA modes are contained in Table 50.DMARQ WRITE CS0-/CS1-DD(15:0)READ DD(15:0)Figure 5. Device terminating a Multiword DMA data transferDIOR-/DIOW-DMACK-t 0t Kt Et Gt Ft Gt H (See note)t Nt Lt D t Jt ZNOTE:To terminate the data burst, the Host shall negate DMARQ within the tL of the assertion of the current DIOR- or DIOW- pulse. The last data word for the burst shall then be transferred by the negation of the current DIOR- or DIOW- pulse. If all data for the command has not been transferred, the Host shall reassert DMARQ again at any later time to resume the DMA operation.4.5.3.3 Device terminating a Multiword DMA data burstThe values for the timings for each of the Multiword DMA modes are contained in Table 50.DMARQ WRITE CS0-/CS1-DD(15:0)READ DD(15:0)Figure 6. Host terminating a Multiword DMA data transferDIOR-/DIOW-DMACK-t 0t Kt Et Gt Ft Gt H (See note 2)t Nt Dt J t ZNOTE:1. To terminate the transmission of a data burst, the host shall negate DMACK- within the specified time after a DIOR- or DIOW- pulse. No further DIOR- or DIOW- pulses shall be asserted for this burst.2. If the device is able to continue the transfer of data, the Host may leave DMARQ asserted and wait for the host to reassert DMACK- or may negate DMARQ at any time after detecting that DMACK- has been negated.(See note 1)4.5.3.4 Host terminating a Multiword DMA data burstFigure 7 through Figure 16 define the timings associated with all phases of Ultra DMA bursts.Table 4 contains the values for the timings for each of the Ultra DMA modes.Table 4 - Ultra DMA data burst timing requirements NOTE :1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies. For example, the sender shall stop generating STROBE edges t RFS after the negation of DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the sender.2. All timing measurement switching points(low to high and high to low) shall be taken at 1.5V.3. t UI , t MLI , and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the other to respond with a signal before proceeding. t UI is an inlimited interlock that has no maximum time value. t MLI is a limited time-out that has a defined minimum. t LI is a lim-ited time-out that has a defined maximum.4. The test load for t DVS and t DVH shall be a lumped capacitor load with no cable or receivers. Timing for t DVS and t DVH shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.5. t ZIORDY may be greater than t ENV since the device has a pull up on IORDY- giving it a known state when released.NameMode 0Mode 1Mode 2Mode 3Mode 4Comment(See Notes 1 and 2)minmaxmin maxmin maxmin maxmin maxt 2CYCTYP 2401601209060Typical sustained average two cycle timet CYC 11273543925Cycle time allowing for asymmetry and clock varia-tions (from STROBE edge to STROBE edge)t 2CYC 2301541158657Two cycle time allowing for clock variations (from ris-ing edge to next rising edge or from falling edge to next falling edge of STROBE)t DS 1510775Data setup time at recipient t DH 55555Data hold time at recipientt DVS 704830206Data valid setup time at sender (from data valid until STROBE edge) (See Note 4)t DVH 66666Data valid hold time at sender (from STROBE edge until data may become invalid) (See Note 4)t FS 02300200017001300120First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)t LI 01500150015001000100Limited interlock time (See Note 3)t MLI 2020202020Interlock time with minimum(See Note 3)t UI 0Unlimited interlock time (See Note 3)t AZ 1010101010Maximum time allowed for output drivers to release (from asserted or negated)t ZAH 2020202020Minimum delay time required for output t ZAD 00000Drivers to assert or negate (from released)t ENV20702070207020552055Envelope time (from DMACK- to STOP and HDMARDY- during data in burst initiation and from DMACK to STOP during data out burst initiation)t SR 503020NA NA STROBE-to-DMARDY- time (if DMARDY- is negated before this long after STROBE edge, the recipientshall receive no more than one additional data word)t RFS 7570606060Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY-)t RP 160125100100100Minimum time to assert STOP or negate DMARQ t IORDYZ 2020202020Maximum time before releasing IORDYt ZIORDY 00000Minimum time before driving STROBE (See Note 5)t ACK 2020202020Setup and hold times for DMACK- (before assertion or negation)t SS5050505050Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst)4.5.4 Ultra DMA data burst。

执行nand probe 0 提示找不到NAND flash device . 解决办法> halttarget state: haltedtarget halted in ARM state due to debug-request, current mode: Abortcpsr: 0x400001d7 pc: 0x00000010> nand probe 0unknown NAND flash device found, manufacturer id: 0x18 device id: 0x18in procedure nand上述提示错误信息为找不到NAND flash 器件。

解决办法如下：：：> arm mcr 15 0 1 0 0 0> step 0target state: haltedtarget halted in ARM state due to single-step, current mode: Abortcpsr: 0x400001d7 pc: 0x00000004> nand probe 0unknown NAND flash device found, manufacturer id: 0x0c device id: 0x0cin procedure nand> step 1target state: haltedtarget halted in ARM state due to single-step, current mode: Abortcpsr: 0x400001d7 pc: 0x00000004> step 4target state: haltedtarget halted in ARM state due to single-step, current mode: Abortcpsr: 0x400001d7 pc: 0x00000008> step 8target state: haltedtarget halted in ARM state due to single-step, current mode: Abortcpsr: 0x400001d7 pc: 0x0000000c> step 88target state: haltedtarget halted in ARM state due to single-step, current mode: Abortcpsr: 0x400001d7 pc: 0x000000b0> step 999target state: haltedtarget halted in ARM state due to single-step, current mode: Abortcpsr: 0x400001d7 pc: 0x00000410> step 111111target state: haltedtarget halted in ARM state due to single-step, current mode: Abortcpsr: 0x400001d7 pc: 0x0001b208> nand probe 0NAND flash device K9GAG08 2GB NAND 3.3V x8 MLC 2b/cell (Samsung) found> nand erase 0 0 0x100000s3c2440_read_block_data: reading data: 0x8a2f268, 0xbfdc5efa, 6erased blocks 0 to 1 on NAND flash device #0 K9GAG08 2GB NAND 3.3V x8 MLC 2b/cell这种命令的目的是要关闭MMU，关掉后才能访问里面的寄存器tips:感谢大家的阅读，本文由我司收集整编。

FLASH型号容量对照表FLASH型号容量对照表各品牌 FLASH型号容量对照表三星（SAMSUNG）FLASH： 8M K9F6408UOC-TCBO16M K9F2808UOB/C-YC/IBO32M K9F5608UOA/B/C-YC/IBO64M K9F1208UOM/A-YCIBO128M K9K1G08UOM/A-YC/IBOK9F1G08UOM-YC/IBO256M K9F2G08UOM-YC/IBOK9K2G08UOM-YC/IBO512M K9W4G08U1M-YC/IBOK9K4G08UOM-YC/IBO东芝（TOSHIBA）FLASH：16M TC58128AFT/TC58DVM72A1FTOO32MTC58256FT/TC58DVM82A1FT00 64MTC58512FT/TC58DVM92A1FT00 128MTH58100FT/TC58DVG02A1FT00 TC58NVGOS3AFT05 256M TC58NVG1S3AFT05sandiak sdtnfbh-1024 128m -512 64 K9F2808U0C-YCB0 16MBK9F2808U0C-VCB0 16MBKM29U128(I)T 16MBK9F5608U0B-YCB0 32MBK9F5608U0C-YCB0 32MBK9F5608U0C-YIB0 32MBSmall K9F5608U0C-VCB0 32MBBlock K9F1208U0M-YCB0 64MBK9F1208U0A-YCB0 64MBK9F1208U0A-YIB0 64MBK9F1208U0A-VCB0 64MBK9K1G08U0A-YCB0 128MBK9K1G08U0M-YCB0 128MBK9K1G08U0M-VIB0 128MBK9T1G08U0A-YCB0 128MBK9T1G08U0M-YCB0 128MBSamsung SLC K9T1G08U0M-VIB0 128MBK9F1G08U0M-YCB0 128MBK9F1G08U0A-YCB0 128MBK9F1G08U0M-VCB0 128MBK9F1G08U0M-VIB0 128MBK9F1G08U0M-FIB0 128MBK9K2G08U0M-YCB0 256MBK9K2G08U0A-FIB0(90nm) 256MBK9K2G08U0M-VCB0 256MBK9K2G08U0M-VIB0 256MB Large K9K2G08U0A-VIB0(90nm) 256MBBlock K9F2G08U0M-YCB0(90nm) 256MBK9K4G08U0M-YCBO(90nm) 512MBK9K4G08U0M-PIB0(90nm) 512MBK9W4G08U1M-YCB0(90nm) 512MBK9W4G08U1M-YIB0(90nm) 512MBK9W8G08U1M-YCB0(90nm) 1GBK9W8G08U1M-YIB0(90nm) 1GBTC58128FT 16MBTC58DVM72A1FT00/05 16MBTC58DVM72A1FTI0 16MBTC58256FT 32MBSmall TC58DVM82A1FT00/05 32MBBlock TC58DVM82A1FTI0 32MBSLC TC58512FT 64MBTC58DVM92A1FT00/05 64MBToshiba TH58100FT 128MBTC58DVG02A1FT00/05 128MBTC58DVG04B1FT00/05 128MBTC58DVG04B1FTI0 128MBSmall TC58DVG14B1FT00/05 256MBMLC Block TC58DVG14B1FTI0 256MBTH58DVG24B1FT00/05 512MBTH58DVG24B1FTI0 512MBHY27US08561M 32MBSmall HY27US08121M 64MBBlock HY27UA081G1M 128MBHynix SLC HY27UB082G4M 256MBLarge HY27UF081G2M 128MBBlock HY27UG082G2M 256MBHY27UH084G2M 512MBInfineon HYF33DS512800ATC 64MBNAND128W3A 16MB Small NAND256W3A 32MBBlock NAND512W3A 64MBNAND01GW3A 128MBNAND128W3B 16MBST SLC NAND256W3B 32MBLarge NAND512W3B 64MBBlock NAND01GW3B 128MBNAND02GW3B 256MBNAND04GW3B 512MBNAND08GW3B 1GBMicron SLC Large MT29F2G08A 256MBBlock MT29F4G08B 256MBSanDisk MLC Small SDTNFCH-512 64MBBlock SDTNGCHE0-1024 128MBHN29V1G91T-30 128MBAG-AND HN29V2G74WT-30 256MBHN29V25691BT 32MB Renesas R1FVH04G13R 512MBSUPER HN29V51211T-50H 64MBAND HN29V51211T-50 64MB补充一下，大家只要记住，最常见的，在MP3中应用的，就是SAMSUNG | HYNIXK9K/K9F 128M 1G08；| HY 1G1M/1G2M，有一个共同的特征，1G代表128M, 如果是2GXX就代表256M,以此类推。

Flash Flash Flash Flash Flash Flash Flash Flash Part Number SM321U SM325SM3251SM3252SM3253SM3254SM3255SM3257SM3255EN SM3257EN SM3260VendorCapacityTypeDateCodePart#ID#CE#ECC IC revision CC AC BB BB AE AE ABAA AA AA AD MP Tool version V2.03.20V2.03.20V2.03.20 v4V2.03.20 v4V2.03.36 v16V2.03.36 v16V2.03.46 v4 V2.03.68 v9V2.03.54 v8V 2.3.72 V1 V 2.3.70 v8F/W version J1015J1015J1015J1015K0222K0222K0823L0403K1216L0425 v2L0504Samsung 16Gbit TLC-8K K9AAGD8U0A EC D5 98 CE 74 C41CE 60b/1KB 21nm Testing Testing Samsung 32Gbit TLC-8K K9ABGD8U0C EC D7 98 CE 74 C41CE 60b/1KB 21nm Y Testing Samsung 64Gbit TLC-8K K9ACGD8U0A EC DE 98 CE 74 C41CE 60b/1KB 21nm Y TestingSamsung 64Gbit MLC-8K K9GCGD8U0M EC DE A4 7E 78 C41CE 60b/1KB 21nm N N N N N N N N Y YSamsung 64Gbit MLC-8K K9GCGD8U0A EC DE A4 7A 68 C41CE 40b/1KB 21nm Testing Y Y Samsung 32Gbit MLC-8K K9GBGD8U0B EC D7 94 7E 64 C41CE 40b/1KB 21nm Testing YSamsung 32Gbit MLC-8K K9GBG08U0B EC D7 94 7E 64 441CE 40b/1KB 21nm Y Y Y Samsung 32Gbit TLC-8K K9ABGD8U0B EC D7 98 CE 1CE 60b/1KB 27nm N N N N N N N N Y Y Y Samsung 64Gbit TLC-8K K9ACGD8U0M EC DE 98 CE 1CE 68b/1KB 27nm N N N N N N N N Y Y Y Samsung 128Gbit TLC-8K K9BDGD8U0M EC 3A D9 CE 1CE 68b/1KB 27nm N N N N N N N N Y Y Samsung 256Gbit TLC-8K K9CFGD8U1M EC 3A D9 CE 2CE 68b/1KB 27nm N N N N N N N N Y YSamsung 16Gbit MLC-8K K9GAGD8U0F EC D5 94 76 541CE 24b/1KB 27nm Y YSamsung 32Gbit MLC-8K K9GBGD8U0A EC D7 94 7A 54 C31CE 24b/1KB 27nm N N N N N N N N Y Y Y Samsung 16Gbit MLC-8K K9GAG08U0F EC D5 94 76 54 431CE 24b/1KB 27nm Y Y Y Testing Samsung 32Gbit MLC-8K K9GBG08U0A EC D7 94 761CE 24b/1KB 27nm N N N N N N Y Y Y Y Samsung 64Gbit MLC-8K K9LCG08U0A EC DE 95 762CE 40b/1KB 27nm N N N N N N N YSamsung 128Gbit MLC-8K K9HDG08U5A EC D7 94 7A 54 432CE 24b/1KB 27nm Y Y Samsung 256Gbit MLC-8K K9PFG08U5A EC DE D5 7A 58 434CE 24b/1KB 27nm Y YSamsung 32Gbit TLC-8K K9ABG08U0A EC D7 98 CA 1CE 24b/1KB 32nm N N N N N N Y Y Y Samsung 64Gbit TLC-8K K9BCG08U1A EC D7 98 CA 2CE 24b/1KB 32nm N N N N N N Y Y Samsung 128Gbit TLC-8K K9CDG08U5A EC D7 98 CA 4CE 24b/1KB 32nm N N N N N N Y Y Samsung 8Gbit MLC-8K K9G8G08U0C EC D3 84 721CE 24b/1KB 32nm N N N N N N Y Y Samsung 16Gbit MLC-8K K9GAG08U0E EC D5 84 721CE 24b/1KB 32nm N N N N N N Y Y Samsung 32Gbit MLC-8K K9LBG08U1E EC D5 84 722CE 24b/1KB 32nm N N N N Y Y Y Y Samsung 64Gbit MLC-8K K9HCG08U2E EC D5 84 724CE 24b/1KB 32nm N N N N Y Y Y Y Samsung 128Gbit MLC-8K K9PDG08U2E EC D7 C5 724CE 24b/1KB 32nm N N N N Y Y Y Y Samsung 16Gbit SLC-8K K9FAGD8U0M EC D5 10 6A 1CE 24b/1KB 32nm N N N N N N N N Testing Y Samsung 32Gbit SLC-8K K9KBGD8U1M EC D5 10 6A 2CE 24b/1KB 32nm N N N N N N N N Testing Y Samsung 32Gbit MLC-8K K9GBG08U0M EC D7 94 721CE 24b/1KB 35nm N N N N Y Y Y Y Samsung 64Gbit MLC-8K K9LCG08U1M EC D7 94 722CE 24b/1KB 35nm N N N N Y Y Y Y Samsung 128Gbit MLC-8K K9HDG08U5M EC D7 94 724CE 24b/1KB 35nm N N N N Y Y Y Y Samsung 32GB MLC-8K K9PFG08U5M EC DE D5 724CE 24b/1KB 35nm N N N N Y Y Y Y Samsung 32Gbit TLC-8K K9ABG08U0M EC D7 98 C61CE 24b/1KB 42nm N N N N N N N N Samsung 64Gbit TLC-8K K9BCG08U1M EC D7 98 C62CE 24b/1KB 42nm N N N N N N N NSamsung 16Gbit MLC-4K K9GAG08U0D EC D5 94 291CE 8b/512B 42nm Y Y Y Y Samsung 32Gbit MLC-4K K9LBG08U0D EC D7 D5 291CE 4b/512B 42nm Y Y Y Y Samsung 64Gbit MLC-4K K9HCG08U1D EC D7 D5 292CE 4b/512B 42nm Y Y Y Y Samsung 1Gbit SLC-2K K9F1G08U0D EC F1 00 151CE 1b/512B 42nm Y Y Y Y N N N N N N Samsung 4Gbit SLC-2K K9F4G08U0D EC DC 10 951CE 1b/512B 42nm Y Y Y Y N N N N N NSamsung 16Gbit TLC-4K K9AAG08U0M EC D5 98 711CE 48b/1KB 51nm N N N N N N N NSamsung 8Gbit MLC-2K K9G8G08U0A EC D3 14 A51CE 4b/512B 51nm Y Y Y Y Samsung 16Gbit MLC-4K K9GAG08U0M EC D5 14 B6 1CE 4b/512B 51nm Y Y Y Y Samsung 16Gbit MLC-4K K9GAG08U0A EC D3 14 A51CE 4b/512B 51nm Y Y Y Y Samsung 16Gbit MLC-4K K9LAG08U0A EC D5 55 A51CE 4b/512B 51nm Y Y Y Y Samsung 32Gbit MLC-4K K9HBG08U1A EC D5 55 A52CE 4b/512B 51nm Y Y Y Y Samsung 32Gbit MLC-4K K9LBG08U0M EC D7 55 B61CE 4b/512B 51nm Y Y Y Y YSamsung 32Gbit MLC-4K K9LBG08U1M EC D3 14 A52CE 4b/512B 51nm Y Y Y Y Samsung 64Gbit MLC-4K K9HCG08U5M EC D3 14 A54CE 4b/512B 51nm Y Y Y Y Samsung 64Gbit MLC-4K K9HCG08U1M EC D7 55 B62CE 4b/512B 51nm Y Y Y Y Samsung 64Gbit MLC-4KK9LE8G4ZUMM EC D5 98 352CE Error Free 51nm N N N NDyna Flash Support List Updated on 05/04/2012Flash Flash Flash Flash Flash Flash Flash Flash Part Number SM321U SM325SM3251SM3252SM3253SM3254SM3255SM3257SM3255EN SM3257EN SM3260VendorCapacityTypeDateCodePart#ID#CE#ECC IC revision CC AC BB BB AE AE ABAA AA AA AD MP Tool version V2.03.20V2.03.20V2.03.20 v4V2.03.20 v4V2.03.36 v16V2.03.36 v16V2.03.46 v4 V2.03.68 v9V2.03.54 v8V 2.3.72 V1 V 2.3.70 v8F/W version J1015J1015J1015J1015K0222K0222K0823L0403K1216L0425 v2L0504Dyna Flash Support List Updated on 05/04/2012Samsung128Gbit MLC-4K K9LEAG8ZUMM EC D7 99 354CE Error Free 51nm N N N N Samsung 128Gbit MLC-4K K9MDG08U5M EC D7 55 B64CE 4b/512B 51nm Y Y Y Y Samsung 8Gbit SLC-4K K9F8G08U0M EC D3 10 A61CE 1b/512B 51nm Y Y Y Y Samsung 16Gbit SLC-4K K9KAG08U0M EC D5 51 A6 1CE 1b/512B 51nm Y Y Y Y Samsung 32Gbit SLC-4K K9WBG08U1M EC D5 51 A6 2CE 1b/512B 51nm Y Y Y Y TestingSamsung 64Gbit SLC-4K K9NCG08U5M EC D5 51 A6 4CE 1b/512B 51nm Y Y Y Y Samsung 8Gbit MLC-2K 819 laterK9G8G08U0B EC D3 14 A51CE 4b/512B 59nm Y Y Y Y Samsung 2Gbit MLC-2K K9G2G08U0M EC DA 14 25 1CE 4b/512B 60nm Y Y Y Y Samsung 4Gbit MLC-2K K9G4G08U0A EC DC 14 251CE 4b/512B 60nm Y Y Y Y Samsung 4Gbit MLC-2K K9G4G08U0B EC DC 14 A51CE 4b/512B 60nm Y Y Y Y Samsung 8Gbit MLC-2K K9G8G08U0M EC D3 14 251CE 4b/512B 60nm Y Y Y Y Samsung 8Gbit MLC-2K K9L8G08U0A EC D3 55 251CE 4b/512B 60nm Y Y Y Y Samsung 16Gbit MLC-2K K9LAG08U0M EC D5 55 251CE 4b/512B 60nm Y Y Y Y Samsung 16Gbit MLC-4K K9LAG08U0B EC D5 14 B51CE 4b/512B 60nm Y Y Y Y Samsung 32Gbit MLC-2K K9HBG08U1M EC D5 55 252CE 4b/512B 60nm Y Y Y Y Samsung 64Gbit MLC-2K K9MCG08U5M EC D5 55 254CE 4b/512B 60nm Y Y Y Y Samsung 1Gbit SLC-2K K9F1G08U0B EC F1 00 951CE 1b/512B 60nm Y Y Y Y Samsung 2Gbit SLC-2K K9F2G08U0A EC DA 10 951CE 1b/512B 60nm Y Y Y Y Samsung 4Gbit SLC-2K K9F4G08U0A EC DC 10 95 1CE 1b/512B 60nm Y Y Y Y Samsung 4Gbit SLC-2K 822 laterK9F4G08U0B EC DC 10 95 1CE 1b/512B 60nm Y Y Y Y Samsung 8Gbit SLC-2K K9K8G08U0A EC D3 51 951CE 1b/512B 60nm Y Y Y Y Samsung 8Gbit SLC-2K K9K8G08U1A EC DC 10 95 2CE 1b/512B 60nm Y Y Y Y Samsung 8Gbit SLC-2K 822 later K9K8G08U0B EC D3 51 951CE 1b/512B 60nm Y Y Y Y Samsung 16Gbit SLC-2K K9WAG08U1A EC D3 51 952CE 1b/512B 60nm Y Y Y Y Samsung 16Gbit SLC-2K 822 laterK9WAG08U1B EC D3 51 952CE 1b/512B 60nm Y Y Y Y Samsung 32Gbit SLC-2K K9NBG08U5A EC D3 51 954CE 1b/512B 60nm Y Y Y Y Samsung 4Gbit SLC-2K K9F4G08U0M EC DC 10 95 1CE 1b/512B 70nm Y Y Y Y Samsung 8Gbit SLC-2K K9W8G08U1M EC DC C1 152CE 1b/512B 70nm Y Y Y Y Samsung 8Gbit SLC-2K K9K8G08U1M EC DC 10 95 2CE 1b/512B 70nm Y Y Y Y Samsung 8Gbit SLC-2K K9K8G08U0M EC D3 51 951CE 1b/512B 70nm Y Y Y Y Samsung 16Gbit SLC-2K K9WAG08U1M EC D3 51 952CE 1b/512B 70nm Y Y Y Y Samsung 32Gbit SLC-2K K9NBG08U5M EC D3 51 954CE 1b/512B 70nm Y Y Y Y Samsung 1Gbit SLC-2K K9F1G08U0A EC F1 80 151CE 1b/512B 90nm Y Y Y Y Samsung 2Gbit SLC-2K K9F2G08U0M EC DA 80 151CE 1b/512B 90nm Y Y Y Y Samsung 2Gbit SLC-2K K9K2G08U0M EC DA C1 151CE 1b/512B 90nm Y Y Y Y Samsung 4Gbit SLC-2K K9K4G08U0M EC DA 80 151CE 1b/512B 90nm Y Y Y Y Samsung 4Gbit SLC-2K K9W4G08U1M EC DA C1 152CE 1b/512B 90nm Y Y Y Y Samsung 4Gbit MLC-2K K9G4G08U0M EC DC 14 25 1CE 4b/512B 90nm Y Y Y Y Samsung 8Gbit MLC-2K K9L8G08U0M EC D3 55 251CE 4b/512B 90nm Y Y Y Y Samsung 16Gbit MLC-2K K9HAG08U1M EC D3 55 252CE 4b/512B 90nm Y Y Y Y Samsung 32Gbit MLC-2K K9MBG08U5M EC D3 55 254CE 4b/512B 90nm Y Y Y Y Samsung 16Gbit SLC-2K K9WAG08U1D EC D3 51 952CE 1b/512B Y Y Y Y N N N N N NSamsung 2Gbit SLC-2K K9F2G08U0B EC DA 10 951CE 1b/528B Y Y Y Y Samsung 1Gbit SLC-2K K9F1G08U0C EC F1 00 951CE 1b/512B Y Y Y Y Samsung 1Gbit SLC-2K K9F1G08U0M EC F1 80 151CE 1b/512B Y Y Y Y Samsung 1Gbit SLC-512K9K1G08U0A EC 79 A5 C01CE 1b/512B Y Y Y Y Samsung 1Gbit SLC-512K9K1G08U0M EC 79 A5 C01CE 1b/512B Y Y Y Y Samsung 512Mbit SLC-512K9F1208U0C EC 76 5A 3F 1CE 1b/512B N N N N Samsung 512Mbit SLC-512K9K1208U0C EC 76 A5 BD 1CE 1b/512B N N N N Samsung 512Mbit SLC-512K9F1208U0B EC 76 A5 C01CE 1b/512B N N N NFlash Flash Flash Flash Flash Flash Flash Flash Part Number SM321U SM325SM3251SM3252SM3253SM3254SM3255SM3257SM3255EN SM3257EN SM3260VendorCapacityTypeDateCodePart#ID#CE#ECC IC revision CC AC BB BB AE AE ABAA AA AA AD MP Tool version V2.03.20V2.03.20V2.03.20 v4V2.03.20 v4V2.03.36 v16V2.03.36 v16V2.03.46 v4 V2.03.68 v9V2.03.54 v8V 2.3.72 V1 V 2.3.70 v8F/W version J1015J1015J1015J1015K0222K0222K0823L0403K1216L0425 v2L0504Dyna Flash Support List Updated on 05/04/2012Samsung 512MbitSLC-512K9F1208U0A EC 76 A5 C01CE 1b/512B N N N N Samsung 512Mbit SLC-512K9F1208U0M EC 76 A5 C01CE 1b/512B N N N N Samsung 256Mbit SLC-512K9F5608U0C EC 75 A5 BD 1CE 1b/512B N N N N Samsung 256Mbit SLC-512K9F5608U0B EC 75 A5 BD 1CE 1b/512B N N N N Samsung 256Mbit SLC-512K9F5608U0A EC 75 A5 BD 1CE 1b/512B N N N N Samsung 128Mbit SLC-512K9F2808U0C EC 73 A5 EC 1CE 1b/512B N N N N Samsung 128Mbit SLC-512K9F2808U0B EC 73 A5 EC 1CE 1b/512B N N N NSanDsik 64Gbit TLC-8K SDTNQCAMA-008G 45 DE 98 92 72 571CE 64b/1KB19nm Y Y SanDsik 128Gbit TLC-16K SDTNQCAMA-016G 45 4C A8 92 76 571CE 64b/1KB19nm Y Y SanDsik 64Gbit MLC-8K SDTNQBAMA-008G 45 DE A4 82 76 571CE 24b/1KB19nm Y Testing SanDsik 64Gbit MLC-16K SDTNQFAMA-008G 45 DE 84 93 72 571CE 24b/1KB19nm (HBL)Y TestingSanDisk 32Gbit TLC-8K SDTNPNAHEM-004G 45 D7 98 92 72 D61CE 64b/1KB 24nm N N N Y SanDisk 64Gbit TLC-8K SDTNPNAHSM-008G 45 DE 98 921CE 64b/1KB 24nm N N N N N N N N N Y SanDisk 64Gbit TLC-8K SDTNPNAHEM-008G 45 DE 98 921CE 64b/1KB 24nm N N N N N N N N N Y YSanDisk 16Gbit MLC-8K SDTNPMAHEM-002G 45 D5 84 32 72 561CE 24b/1KB 24nm Y Testing Y SanDisk 64Gbit MLC-8K SDTNOQAHER-008G 45 DE 94 821CE 24b/1KB 24nm N N N N N N N YTesting Y SanDisk 64Gbit MLC-8K SDTNPMAHSM-008G 45 DE 94 82 76 561CE 24b/1KB 24nm Y Y Y SanDisk 64Gbit MLC-8K SDTNPQAHEM-008G 45 DE 94 82 76 561CE 24b/1KB 24nm TestingSanDisk 16Gbit TLC-8K SDTNNMAHSM-002G 45 D5 88 821CE 64b/1KB 32nm (eX3)N N N N N N NN N Y SanDisk 16Gbit TLC-8K SDTNNNAHSM-45 DE 94 82 761CE 64b/1KB 32nm Y SanDisk 32Gbit TLC-8K SDTNNNAHEM-45 D7 98 B21CE 64b/1KB 32nm (eX3)N N N N N N N N N Y SanDisk 32Gbit TLC-8K SDTNNNAHSM-45 C7 98 821CE 64b/1KB 32nm (eX3)N N N N N N N N N Y SanDisk 32Gbit TLC-8K SDTNMMBHSM-45 C7 98 B21CE 64b/1KB 32nm (X3)N N N N N N N N N Y SanDisk 64Gbit TLC-8K SDTNNNAHSM-008G 45 CE A8 821CE 64b/1KB 32nm (eX3)N N N N N N NN N Y SanDisk 64Gbit TLC-8K SDTNNNAHEM-008G 45 DE A8 821CE 64b/1KB 32nm (eX3)N N N N N N N N NYSanDisk 32Gbit MLC-8K SDTNNMAHEM-004G 98 D7 94 321CE 24b/1KB 32nm N N N N N N Y Y SanDisk 32GB MLC-8K SDZNNMDHER-032G 45 68 95 324CE 24b/1KB 32nm N N N N N N Y Y SanDisk 16Gbit TLC-8K SDTNMNAHEM-002G 45 C5 98 B21CE 24b/1KB 43nm N N N N N N Y Y SanDisk 16Gbit TLC-8K SDTNMNAHSM-002G 45 C5 98 B21CE 24b/1KB 43nm N N N N N N Y Y SanDisk 32Gbit TLC-8K SDTNMNAHEM-004G 45 C7 98 B21CE 24b/1KB 43nm N N N N N N Y Y SanDisk 32Gbit TLC-8K SDTNMNAHSM-004G 45 C7 98 B21CE 24b/1KB 43nm N N N N N N Y Y SanDisk 64Gbit TLC-8K SDTNMNBHSM-008G 45 CE 99 B21CE 24b/1KB 43nm N N N N N N Y Y SanDisk 128Gbit TLC-8K SDTNMNCHSM-016G45 4A 9A B21CE 24b/1KB 43nm N N N N N N Y Y SanDisk 32GB MLC-8K SDZNMMDHER-032G45 DE 95 324CE 24b/1KB 43nm N N N N N N Y Y SanDisk 32GB MLC-8K SDZNMMDHER-032G45 CE 95 322CE 24b/1KB 43nm N N N N N N YY SanDisk 16Gbit MLC-4K SDTNLMAHSM - 204845 C5 98 831CE 12b/1KB 56nm N N N N N N Y YToshiba 32Git TLC-8K TC58NVG5T2JTA0098 D7 98 92 72 571CE 64b/1KB19nm Testing Testing Toshiba 64Git TLC-8K TC58NVG6T2JTA0098 DE 98 92 72 571CE 64b/1KB19nm Y Y Toshiba 128Gbit TLC-16K TC58NVG7T2JTA0098 3A A8 92 76 571CE 60b/1KB19nm Y Y Toshiba 32Gbit TLC-8K TC58TVG5T2JTA0098 D7 98 92 72 D71CE 60b/1KB19nm Y Testing Toshiba 64Gbit TLC-8K TC58TVG6T2JTA0098 DE 98 92 72 D71CE 60b/1KB19nm Y Y Toshiba 128Gbit TLC-16K TC58TVG7T2JTA0098 3A A8 92 76 D71CE 60b/1KB19nm Y Y Toshiba 64Gbit MLC-8K TC58NVG6D2JTA0098 DE A4 82 76 571CE 40b/1KB19nm Testing TestingY Testing Toshiba 64Gbit MLC-16K TC58NVG6DCJTA0098 DE 84 93 72 571CE 40b/1KB 19nm (TypeB)Testing Testing Toshiba 64Gbit MLC-16K TC58TEG6DCJTA0098 DE 84 93 72 D71CE 40b/1KB 19nm (TypeB)Testing Testing Toshiba 64Gbit MLC-16K TC58TEG6DDJTA0098 DE 94 93 76 D71CE 40b/1KB 19nm (TypeC)Testing Testing Toshiba 32GbitTLC-8K TC58NVG5T2HTA0098 D7 98 92 72 561CE 64b/1KB24nm Y Toshiba64Gbit TLC-8K TC58NVG6T2HTA0098 DE 98 921CE 64b/1KB 24nm N N N N N N N N NY Y Toshiba 32Gbit TLC-8K TC58TVG5T2HTA0098 D7 98 92 72 D61CE 60b/1KB24nm Y YToshiba 64Gbit TLC-8KTC58TVG6T2GTA0098 DE 98 92 72 D61CE 60b/1KB24nm YFlash Flash Flash Flash Flash Flash Flash Flash Part Number SM321U SM325SM3251SM3252SM3253SM3254SM3255SM3257SM3255EN SM3257EN SM3260VendorCapacityTypeDateCodePart#ID#CE#ECC IC revision CC AC BB BB AE AE ABAA AA AA AD MP Tool version V2.03.20V2.03.20V2.03.20 v4V2.03.20 v4V2.03.36 v16V2.03.36 v16V2.03.46 v4 V2.03.68 v9V2.03.54 v8V 2.3.72 V1 V 2.3.70 v8F/W version J1015J1015J1015J1015K0222K0222K0823L0403K1216L0425 v2L0504Dyna Flash Support List Updated on 05/04/2012Toshiba 64Gbit TLC-8K TC58TVG6T2HTA0098 DE 98 92 72 D61CE 60b/1KB24nm Y Y Toshiba 64Gbit TLC-8K TH58TVG6T2HBA4C 98 DE 98 92 72 D62CE 60b/1KB24nm Y Toshiba 128Gbit TLC-8K TH58NVG7T2HTA2098 DE 98 92 722CE 60b/1KB 24nm YToshiba 128Gbit TLC-8K TH58TVG7T2HBA4C 98 DE 98 922CE 64b/1KB 24nm N N N N N N N N N YToshiba 256Gbit TLC-8K TH58NVG8T2HTA2098 3A 99 92 76 562CE 60b/1KB 24nm YToshiba 16Gbit MLC-8K TC58NVG4D2HTA0098 D5 84 32 76 561CE 24b/1KB24nm Y Toshiba 32Gbit MLC-8K TC58TVG5D2HTA0098 D7 94 32 76 561CE 24b/1KB24nm Y Y Toshiba 32Gbit MLC-8K TC58NVG5D2HTA0098 D7 94 32 76 562CE 24b/1KB24nm Y YToshiba 64Gbit MLC-8K TC58TEG6D2HTA0098 DE A4 82 76 D61CE 24b/1KB24nm YToshiba 64Gbit MLC-8K TH58TEG6D2HBA4C 98 D7 94 32 76 D62CE 24b/1KB24nm Y YToshiba 64Gbit MLC-8K TC58NVG6D2HTA0098 DE A4 82 76 561CE 24b/1KB24nm YToshiba 64Gbit MLC-8K TC58NVG6D2GTA0098 DE 94 821CE 24b/1KB 24nm N N N N N N Y Y Testing Y YToshiba 128Gbit MLC-8K TH58NVG7D2GTA2098 DE 94 82 76 D61CE 24b/1KB24nm Y YToshiba 16Gbit TLC-8K TC58NVG4T2FTA0098 D5 88 821CE 64b/1KB 32nm (ED3)N N N N N N N N N Y Toshiba 32Gbit TLC-8K TC58NVG5T7FLA1998 D7 98 821CE 64b/1KB 32nm (ED3)N N N N N N N N N Y Toshiba 32Gbit TLC-8K TC58NVG5T2FTA0098 97 98 821CE 64b/1KB 32nm (ED3)N N N N N N N N N Y Toshiba 64Gbit TLC-8K TC58NVG6T7FLA1998 DE A8 821CE 64b/1KB 32nm (ED3)N N N N N N N N N Y Toshiba 64Gbit TLC-8K TC58NVG6T2FTA0098 DE A8 821CE 64b/1KB 32nm (ED3)N N N N N N N N N Y Toshiba 8Gbit MLC-8K TC58NVG3D2FTA0098 D3 94 321CE 24b/1KB 32nm N N N N Y Y Y Y Toshiba 16Gbit MLC-8K TC58NVG4D2FTA0098 D5 94 321CE 24b/1KB 32nm N N N N Y Y Y Y Toshiba 32Gbit MLC-8K TC58NVG5D2FTA1098 D7 94 321CE 24b/1KB 32nm N N N N Y Y Y Y Toshiba 64Gbit MLC-8K TH58NVG6D2FTA2098 D7 94 322CE 24b/1KB 32nm N N N N Y Y Y Y Toshiba 128Gbit MLC-8K TH58NVG7D2FTA2098 DE 95 322CE 24b/1KB 32nm N N N N Y Y Y Y Toshiba 256Gbit MLC-8K TH58NVG8D2FLA8998 EE 95 324CE 24b/1KB 32nm N N N N N N Y Y Toshiba 16Gbit TLC-8K TC58NVG4T2ETA0098 D5 98 B21CE 24b/1KB 43nm N N N N Y Y Toshiba 32Gbit TLC-8K TH58NVG5T2ETA2098 D7 98 B21CE 24b/1KB 43nm N N N N Y Y Toshiba 64Gbit TLC-8K TH58NVG6T2ETA2A 98 D7 99 B22CE 24b/1KB 43nm N N N N Y Y Toshiba 16Gbit MLC-8K TC58NVG4D2ETA0098 D5 94 321CE 24b/1KB 43nm N N N N Y Y Y Y Toshiba 32Gbit MLC-8K TH58NVG5D2ETA2098 D5 94 322CE 24b/1KB 43nm N N N N Y Y Y Y Toshiba 64Gbit MLC-8K TH58NVG6D2ETA2098 D7 95 322CE 24b/1KB 43nm N N N N Y Y Y Y Toshiba 128Gbit MLC-8K TH58NVG7D2ELA4898 D7 94 324CE 24b/1KB 43nm N N N N Y Y Y Y Toshiba 256Gbit MLC-8K TH58NVG8D2ELA8998 DE 95 321CE 24b/1KB 43nm N N N N Y Y Y YToshiba 1Gbit SLC-8K TC58NVG0S3ETA0098 D1 90 151CE 1bit/512B 43nm Y Y N N Toshiba 2Gbit SLC-8K TC58NVG1S3ETA0098 DA 90 151CE 1bit/512B 43nm Y Y N N Toshiba 4Gbit SLC-8K TC58NVG2S3ETA0098 DC 90 151CE 1bit/512B 43nm Y Y N N Toshiba 8Gbit MLC-4K TC58NVG3D1DTG0098 D3 94 BA 1CE 8b/512B 56nm Y Y Y Y Toshiba 16Gbit MLC-4K TC58NVG4D1DTG0098 D5 94 BA 1CE 8b/512B 56nm Y Y Y Y Toshiba 32Gbit MLC-4K TH58NVG5D1DTG2098 D5 94 BA 2CE 8b/512B 56nm Y Y Y Y Toshiba 64Gbit MLC-4K TH58NVG6D1DTG2098 D7 95 BA 2CE 8b/512B 56nm Y Y Y Y Toshiba 64Gbit MLC-4K TH58NVG6D1DTG8098 D5 94 BA 4CE 8b/512B 56nm Y Y Y Y Toshiba 64MB SLC-512TC58NVM9S3CTA0098 F0 80 951CE 1b/512B 70nm N N N N Toshiba 4Gbit MLC-2K TC58NVG2D4CTGI0 98 D3 85 A5 1CE 4b/512B 70nm Y Y Y Y Toshiba 8Gbit MLC-2K TC58NVG3D4CFT00 98 D5 85 A51CE 4b/512B 70nm Y Y Y Y Toshiba 16Gbit MLC-2K TH58NVG4D4CTG0098 D5 85 A52CE 4b/512B 70nm Y Y Y Y Toshiba 32Gbit MLC-2K TH58NVG5D4CTG20 98 D5 85 A52CE 4b/512B 70nm Y Y Y Y Toshiba 2Gbit MLC-2K TC58NVG1D4BTG0098 DA 84 A51CE 4b/512B 90nm Y Y Y Y Toshiba 4Gbit MLC-2K TC58NVG2D4BFT0098 DC 84 A51CE 4b/512B 90nm Y Y Y Y Toshiba 8Gbit MLC-2K TH58NVG3D4BTG00 98 D3 84 A52CE 4b/512B 90nm Y Y Y Y Toshiba 64MB SLC-512TC58DVM92A3TA0098 F1 80 951CE 1b/512B N N N N Toshiba 2Gbit MLC-512TC58DVG14B1FT00 98 DA 80 951CE 4b/512B Y Y Y YFlash Flash Flash Flash Flash Flash Flash Flash Part Number SM321U SM325SM3251SM3252SM3253SM3254SM3255SM3257SM3255EN SM3257EN SM3260VendorCapacityTypeDateCodePart#ID#CE#ECC IC revision CCAC BB BB AE AE ABAA AA AA AD MP Tool version V2.03.20V2.03.20V2.03.20 v4V2.03.20 v4V2.03.36 v16V2.03.36 v16V2.03.46 v4 V2.03.68 v9V2.03.54 v8V 2.3.72 V1 V 2.3.70 v8F/W version J1015J1015J1015J1015K0222K0222K0823L0403K1216L0425 v2L0504Dyna Flash Support List Updated on 05/04/2012Toshiba1Gbit MLC-512TC58DVG04B1FT00 98 79 A5 C01CE 4b/512B Y Y Y Y Toshiba 4Gbit SLC-2K TH58NVG2S3BTG 98 DC 81 95 2CE 1b/512B Y Y Y Y Toshiba 2Gbit SLC-2K TC58NVG1S3BFT 98 DA 81 951CE 1b/512B Y Y Y Y Toshiba 2Gbit SLC-2K TH58NVG1S3AFT 98 DA 81 952CE 1b/512B Y Y Y Y Toshiba 1Gbit SLC-2K TC58NVG0S3BFT 98 F1 80 951CE 1b/512B Y Y Y Y Toshiba 1Gbit SLC-2K TC58NVG0S3AFT 98 F1 80 951CE 1b/512B Y Y Y Y Toshiba 512Mbit SLC-512TC58DVM92A1FT 98 76 A5 C01CE 1b/512B Y Y Y YHynix 32Gbit MLC-8K H27UBG8T2CTR AD D7 94 91 60 441CE 40b/1KB 20nm Y Y Testing Testing Hynix 64Gbit MLC-8K H27UCG8T2ATR AD DE 94 DA 74 C41CE 40b/1KB 20nm Y Y Testing TestingHynix 32Gbit MLC-8K H27UBG8T2BTR AD D7 94 DA 1CE 24b/1KB 26nm N N N N N N Y Y Y Y Hynix 64Gbit MLC-8K H27UCG8T2MYR AD DE 94 D21CE 24b/1KB 26nm N N N N N N Y Y Y Y Hynix 32Gbit TLC-4K H27UBG8M2ADA AD D7 18 8D 1CE 24b/1KB 32nm N N N N N N Y Y Hynix 16Gbit MLC-8K H27UAG8T2BTR AD D5 94 9A 1CE 24b/1KB 32nm N N N N Y Y Y Y Y Hynix 32Gbit MLC-8K H27UBG8T2ATR AD D7 94 9A 1CE 24b/1KB 32nm N N N N Y Y Y Y Y Hynix 64Gbit MLC-8K H27UCG8U5ATR AD D7 95 252CE 24b/1KB 32nm N N N N Y Y Y Y Y Hynix 128Gbit MLC-8K H27UDG8V5ATR AD DE 95 9A 4CE 24b/1KB 32nm N N N N Y Y Y Y YHynix 256Gbit MLC-8K HY27UEG8YEA AD DE 95 9A 4CE 24b/1KB 32nm N N N N Y Y Y Y Hynix 16Gbit TLC-4K H27UAG8M2MYR AD D5 18 2D 1CE 24b/1KB 41nm N N N N N N YYHynix 16Gbit MLC-4K 912A H27UAG8T2ATR AD D5 94 251CE 12b/512B 41nm N N Y Y Hynix 32Gbit MLC-4K 912A H27UBG8T2MYR AD D7 94 251CE 12b/512B 41nm N N Y Y Hynix 32Gbit MLC-4K 925A H27UBG8T5ATR AD D5 94 252CE 12b/512B 41nm N N Y Y Hynix 64Gbit MLC-4K 911A H27UCG8UDMYR AD D7 94 252CE 12b/512B 41nm N N Y Y Hynix 64Gbit MLC-4K 925A H27UCG8V5ATR AD D7 94 252CE 12b/512B 41nm N N Y Y Hynix 128Gbit MLC-4K 914A H27UDG8VEMYR AD D7 94 254CE 12b/512B 41nm N N Y Y Hynix 64Gbit TLC-4K 928A H2EUCG8N1MYR AD D7 18 352CE Error Free 48nm N N N N Hynix 128Gbit TLC-4K 922A H2EUDG8P1MXR AD D7 18 354CE Error Free 48nm N N N N Hynix 2Gbit MLC-2K 818A later H27U2G8T2MTR AD DA 14 A51CE 4b/512B 48nm Y Y Y Y Hynix 16Gbit MLC-4K 830AA laterH27UAG8T2MTR AD D5 14 B61CE 4b/512B 48nm Y Y Y Y Hynix 32Gbit MLC-4K 830A later H27UBG8U5MTR AD D5 14 B64CE 4b/512B 48nm Y Y Y Y Hynix 64Gbit MLC-4K 821A later H27UCG8VFMTR AD D5 14 B64CE 4b/512B 48nm Y Y Y Y Hynix 64Gbit MLC-4K 831A later H27UCG8V5MTR AD D7 55 B62CE 4b/512B 48nm Y Y Y Y Hynix 128Gbit MLC-4K 837AA laterH27UDG8YFMXR AD D7 55 B64CE 4b/512B 48nm Y Y Y Y Hynix 128MB SLC-2K H27U1G8F2BTR AD F1 00 1D 1CE 1b/512B 48nm N N Y Y Hynix 8Gbit SLC-2K H27U8G8F2MTR AD D3 10 A61CE 1b/512B 48nm Y Y Y Y Hynix 4Gbit MLC-2K HY27UT084G2A AD DC 14 A51CE 4b/512B 57nm Y Y Y Y Hynix 8Gbit MLC-2K HY27UT088G2A AD D5 14 B61CE 4b/512B 57nm Y Y Y Y Hynix 16Gbit MLC-2K HY27UU08AG5A AD D3 14 A52CE 4b/512B 57nm Y Y Y Y Hynix 32Gbit MLC-2K HY27UV08BGFA AD D3 14 A54CE 4b/512B 57nm Will Test Will TestWill TestWill TestHynix 32Gbit MLC-2K HY27UV08BG5A AD D3 14 A52CE 4b/512B 57nm Y Y Y Y Hynix 64Gbit MLC-2K HY27UW08CGFA AD D5 55 A54CE 4b/512B 57nm Will Test Will TestWill TestWill TestHynix 2Gbit SLC-2K HY27UF082G2B AD DA 10 951CE 1b/512B 57nm Y Y Y Y Hynix 4Gbit SLC-2K HY27UF084G2B AD DC 10 951CE 1b/512B 57nm Y Y Y Y Hynix 8Gbit SLC-2K HY27UG088G5B AD DC 10 952CE 1b/512B 57nm Y Y Y Y Hynix 16Gbit SLC-2K HY27UH08AG5B AD D3 51 952CE 1b/512B 57nm Y Y Y Y Hynix 32Gbit SLC-2K HY27UK08BGFB AD D3 51 954CE 1b/512B 57nm Will Test Will TestWill TestWill TestHynix 8Gbit MLC-2K HY27UT088G2M AD D3 14 A51CE 4b/512B 60nm Y Y Y Y Hynix 16Gbit MLC-2K HY27UU08AG5M AD D3 14 A52CE 4b/512B 60nm Y Y Y Y Hynix 32Gbit MLC-2K HY27UV08BG5M AD D5 55 A52CE 4b/512B 60nm Y Y Y Y Hynix 32Gbit MLC-2K HY27UV08BGFM AD D3 14 A54CE 4b/512B 60nm Y Y Y Y Hynix 64GbitMLC-2K HY27UW08CGFM AD D5 55 A54CE 4b/512B 60nm Y Y Y YFlash Flash Flash Flash Flash Flash Flash Flash Part Number SM321U SM325SM3251SM3252SM3253SM3254SM3255SM3257SM3255EN SM3257EN SM3260VendorCapacityTypeDateCodePart#ID#CE#ECC IC revision CC AC BB BB AE AE ABAA AA AA AD MP Tool version V2.03.20V2.03.20V2.03.20 v4V2.03.20 v4V2.03.36 v16V2.03.36 v16V2.03.46 v4 V2.03.68 v9V2.03.54 v8V 2.3.72 V1 V 2.3.70 v8F/W version J1015J1015J1015J1015K0222K0222K0823L0403K1216L0425 v2L0504Dyna Flash Support List Updated on 05/04/2012Hynix1Gbit SLC-2K HY27UF081G2B AD F1 80 1D 1CE 1b/512B 60nm Y Y Y Y Hynix 8Gbit SLC-2K HY27UG088G2M AD D3 C1 951CE 1b/512B 60nm Y Y Y Y Hynix 16Gbit SLC-2K HY27UH08AG5M AD D3 C1 952CE 1b/512B 60nm Y Y Y Y Hynix 512Mbit SLC-512HY27US08121B AD 76 AD 761CE 1b/512B 70nm N N N N Hynix 1Gbit SLC-2K HY27UF081G2A AD F1 80 1D 1CE 1b/512B 70nm Y Y Y Y Hynix 1Gbit SLC-2K HY27UA081G1M AD 79 A5 001CE 1b/512B 70nm N N N N Hynix 2Gbit SLC-2K HY27UF082G2A AD DA 80 1D 1CE 1b/512B 70nm Y Y Y Y Hynix 2Gbit SLC-2K HY27UB082G4M AD 79 A5 002CE 1b/512B 70nm N N N N Hynix 4Gbit SLC-2K HY27UF084G2M AD DC 80 951CE 1b/512B 70nm Y Y Y Y Hynix 8Gbit SLC-2K HY27UH088G2M AD D3 80 151CE 1b/512B 70nm Y Y Y Y Hynix 8Gbit SLC-2K HY27UG088G5M AD DC 80 952CE 1b/512B 70nm Y Y Y Y Hynix 128Mbit SLC-512HY27US08281A AD 73 A5 C0 1CE 1b/512B 90nm N N N N Hynix 256Mbit SLC-512HY27US08561A AD 75 A5 001CE 1b/512B 90nm N N N N Hynix 256Mbit SLC-512HY27US08561M AD 75 A5 001CE 1b/512B 90nm N N N N Hynix 512Mbit SLC-512HY27US08121M AD 76 A5 001CE 1b/512B 90nm N N N N Hynix 1Gbit SLC-2K HY27UF081G2M AD F1 80 151CE 1b/512B 90nm Y Y Y Y Hynix 2Gbit SLC-2K HY27UF082G2M AD DA 80 151CE 1b/512B 90nm Y Y Y Y Hynix 2Gbit SLC-2K HY27UG082G2M AD DA 80 151CE 1b/512B 90nm Y Y Y Y Hynix 4Gbit MLC-2K HY27UT084G2M AD DC 84 251CE 4b/512B 90nm Y Y Y Y Hynix 4Gbit SLC-2K HY27UH084G2M AD DA 80 15 1CE 1b/512B 90nm Y Y Y Y Hynix 4Gbit SLC-2K HY27UG084G2M AD DC 80 151CE 1b/512B 90nm Y Y Y Y Hynix 8Gbit MLC-2K HY27UU088G5M AD DC 84 252CE 4b/512B 90nm Y Y Y Y Hynix 16Gbit MLC-2K HY27UV08AG5M AD D3 85 252CE 4b/512B 90nm Y Y Y Y Hynix 32Gbit MLC-2K HY27UW08BGFM AD D3 85 254CE 4b/512B 90nm Y Y Y Y Hynix 64MB SLC-512H27U518S2CTP AD 76 AD 761CE 1b/512B N N N N Hynix 128Mbit SLC-512HY27US08281B AD 73 A5 C0 1CE 1b/512B N N N N STM 32Gbit MLC-4K NAND32GW3D4AN620 D5 14 B62CE 4b/512B 48nm Y Y Y Y STM 16Gbit MLC-4K NAND16GW3D2AN620 D5 14 B61CE 4b/512B 48nm Y Y Y Y STM 8Gbit SLC-4K NAND08GW3F2AN620 D3 10 A61CE 1b/512B 48nm Y Y Y Y STM 16Gbit MLC-2K NAND16GW3C4BN620 D3 14 A52CE 4b/512B 57nm Y Y Y Y STM 8Gbit MLC-2K NAND08GW3C2BN120 D3 14 A51CE 4b/512B 57nm Y Y Y Y STM 4Gbit MLC-2K NAND04GW3C2BN620 DC 14 A51CE 4b/512B 60nm Y Y Will Test Will Test STM 8Gbit MLC-2K NAND08GW3C2A 20 D3 14 A51CE 4b/512B 60nm Y Y Y Y STM 2Gbit SLC-2K NAND02GW3B2DN620 DA 10 951CE 1b/512B 60nm Y Y Y Y STM 4Gbit SLC-2K NAND04GW3B2DN6 20 DC 10 95 1CE 1b/512B 60nm Y Y Y Y STM 2Gbit SLC-2K NAND02GW3B2C 20 DA 80 1D 1CE 1b/512B 70nm Y Y Y Y STM 4Gbit SLC-2K NAND04GW3B2B 20 DC 80 951CE 1b/512B 70nm Y Y Y Y STM 8Gbit SLC-2K NAND08GW3B2A 20 D3 C1 951CE 1b/512B 70nm Y Y Y Y STM 4Gbit SLC-2K NAND04GW3B2A 20 DC 80 951CE 1b/512B 90nm Y Y Y Y STM 2Gbit SLC-2K NAND02GW3B2B 20 DA 80 15 1CE 1b/512B 90nm Y Y Y Y STM 2Gbit SLC-2K NAND02GW3B2A 20 DA 80 15 1CE 1b/512B 90nm Y Y Y Y STM 1Gbit SLC-2K NAND01GW3B2B 20 F1 80 1D 1CE 1b/512B 90nm Y Y Y Y STM 1Gbit SLC-2K NAND01GW3B2A 20 F1 80 151CE 1b/512B 90nm Y Y Y Y STM 1Gbit SLC-2K NAND01GW3A0A 20 79 A5 001CE 1b/512B 90nm Y Y Y Y STM 512Mbit SLC-512NAND512W3A2BN6 20 76 20 76 1CE 1b/512B 90nm N N N N STM 512Mbit SLC-512NAND512W3A2C 20 76 A5 001CE 1b/512B 90nm N N N N STM 512Mbit SLC-512NAND512W3A2B 20 76 A5 001CE 1b/512B 90nm N N N N STM 256Mbit SLC-512NAND256W3A0AN620 75 20 751CE 1b/512B 90nm N N N N STM 128Mbit SLC-512NAND128W3B2BN620 73 20 73 1CE 1b/512B 90nm N N N N STM 256Mbit SLC-512NAND256W3A2A 20 75 A5 00 1CE 1b/512B N N N NFlash Flash Flash Flash Flash Flash Flash Flash Part Number SM321U SM325SM3251SM3252SM3253SM3254SM3255SM3257SM3255EN SM3257EN SM3260VendorCapacityTypeDateCodePart#ID#CE#ECC IC revision CC AC BB BB AE AE ABAA AA AA AD MP Tool version V2.03.20V2.03.20V2.03.20 v4V2.03.20 v4V2.03.36 v16V2.03.36 v16V2.03.46 v4 V2.03.68 v9V2.03.54 v8V 2.3.72 V1 V 2.3.70 v8F/W version J1015J1015J1015J1015K0222K0222K0823L0403K1216L0425 v2L0504Dyna Flash Support List Updated on 05/04/2012STM128Mbit SLC-512NAND128W3A2A 20 73 A5 00 1CE 1b/512B N N N N Renesas 4Gbit MLC-2K R1FV04G13RSA 07 29 07 291CE 4b/512B 90nm Y Y Y Y Renesas 1Gbit MLC-2K HN29V1G91T-30V 07 01 07 01 1CE 4b/512B 90nm N N N N Renesas 1Gbit MLC-2K HN29V1G91T-3007 01 07 01 1CE 4b/512B 90nm N N N N Powerchip 4Gbit SLC-2K P1U4GA31DT-G30CA92 DC 00151CE 4b/512B 90nm Y Y Y Y Powerchip 4Gbit MLC-2K P1U4GR30CT-G45CA07 29 07 291CE 4b/512B 90nm Y Y Y Y Powerchip 4Gbit MLC-2K P1U4GR30CT-G45CB07 29 07 291CE 4b/512B 90nm Note 1Note 1Note 1Note 1Powerchip 4Gbit MLC-2K P1U4GR30CT-G45CD07 29 07 291CE 4b/512B 90nm Note 1Note 1Note 1Note 1Infenion 512Mbit MLC-512HYF31DS512805BTC C1 66 29 411CE 4b/512B N N N N Infenion 512Mbit MLC-512HYF33DS512800ATC C1 76 C1 76 1CE 4b/512B N N N NMicron 64Gbit MLC-8K MT29F64G08CBABA 2C 84 C5 4B A9 001CE 40b/1KB20nm (L84)N N N N N N N Y Y Y Testing Micron 64Gbit MLC-8K MT29F64G08CBABB 2C 64 44 4B A9 001CE 40b/1KB20nm (L84)N N N N N N N NY TestingMicron 128Gbit TLC-8K MT29F128G08EFAA 2C 88 08 5F A9 002CE 66b/1KB 25nm (B74A)N N N N N N N Y Y Micron 256Gbit TLC-8K MT29F256G08EJAA 2C 88 08 5F 89 002CE 66b/1KB 25nm (B74A)N N N N N N N Y Y Micron 64Gbit TLC-8K MT29F64G08EBAAA 2C 88 28 5F1CE 66b/1KB 25nm (B74A)N N N N N N N N YY Micron 16Gbit MLC-4K MT29F16G08CBACA 2C 48 04 4A1CE 24b/1KB 25nm (L72A)N N N N Y Y Y Y Y Micron 32Gbit MLC-4K MT29F32G08CBACA 2C 68 04 4A1CE 24b/1KB 25nm (L73A)N N N N Y Y Y Y Y Micron 32Gbit MLC-4K MT29F32G08CFACA 2C 48 04 4A2CE 24b/1KB 25nm (L72A)N N N N Y Y Y Y Y Micron 64Gbit MLC-8K MT29F64G08CBAAB 2C 88 04 4B A91CE 24b/1KB 25nm (L74A)Y Y Micron 64Gbit MLC-8K MT29F64G08CBAAA 2C 88 04 4B 1CE 24b/1KB 25nm (L74A)N N N N Y Y YY YY Y Micron 64Gbit MLC-4K MT29F64G08CFACA 2C 68 04 4A2CE 24b/1KB 25nm (L73A)N N N N Y Y Y Y Y Micron 128Gbit MLC-8K MT29F128G08CFAA 2C 88 04 4B A9 002CE 24b/1KB 25nm (L74A)Y Y Micron 128Gbit MLC-8K MT29F128G08CFAA 2C 88 04 4B2CE 24b/1KB 25nm (L74A)N N N N Y Y Y Y Y Y YMicron 256Gbit MLC-8K MT29F256G08CJAA 2C A8 25 CB2CE 24b/1KB 25nm (L74A)N N N N Y Y Y Y YYMicron 32Gbit SLC-8K MT29F32G08ABAAA 2C 68 00 2B1CE 8b/540B 25nm N N N N Y Y Micron 32Gbit TLC-4K MT28F32G08EBAAA 2C 68 08 561CE 24b/1KB 34nm (B63)N N N N N N N N Micron 16Gbit MLC-4K MT29F16G08CBABA 2C 48 04 461CE 12b/540B 34nm (L62A)N N Y Y Y Y Y Y Micron 32Gbit MLC-4K MT29F32G08MAA 2C D7 94 3E 1CE 12b/539B 34nm (L63A)N N Y Y Y Y Y Y Micron 32Gbit MLC-4K MT29F32G08CBAAA 2C D7 94 3E 1CE 12b/539B 34nm (L63A)N N Y Y Y Y Y Y Micron 32Gbit MLC-4K MT29F32G08CBABA 2C 68 04 461CE 12b/540B 34nm (L63B)N N Y Y Y Y Y Y Micron 64Gbit MLC-4K MT29F64G08QAA 2C D7 94 3E 2CE 12b/539B 34nm (L63A)N N Y Y Y Y Y Y Micron 64Gbit MLC-4K MT29F64G08CFAAA 2C D7 94 3E 2CE 12b/539B 34nm (L63A)N N Y Y Y Y Y Y Micron 64Gbit MLC-4K MT29F64G08CFABA 2C 68 04 462CE 12b/540B 34nm (L63B)N N Y Y Y Y Y Y Micron 128Gbit MLC-4K MT29F128G08CJABA 2C 88 05 C62CE 12b/540B 34nm (L63B)N N Y Y Y Y Y Y Micron 128Gbit MLC-4K MT29F128G08TAA 2C D9 D5 3E 2CE 12b/539B 34nm (L63A)N N Y Y Y Y Y Y Micron 128Gbit MLC-4K MT29F128G08CJAAA 2C D9 D5 3E 2CE 12b/539B 34nm (L63A)N N Y Y Y Y Y YMicron 8Gbit SLC-4K MT29F8G08ABABA 2C 38 00 261CE 4b/540B 34nm N N Y Y Micron 16Gbit SLC-4K MT29F16G08ABABA 2C 48 00 261CE 4b/540B 34nm N N Y Y Micron 32Gbit SLC-4K MT29F32G08AFABA 2C 48 00 262CE 4b/540B 34nm N N Y Y Micron 64Gbit SLC-4K MT29F64G08AJABA 2C 68 01 A62CE 4b/540B 34nm N N Y Y Micron 8Gbit MLC-2K MT29F8G08MAD 2C D3 94 2D 1CE 4b/512B 50nm Y Y Y Y Micron 16Gbit MLC-4K MT29F16G08MAA 2C D5 94 3E 1CE 8b/512B 50nm Y Y Y Y Micron 32Gbit MLC-4K MT29F32G08QAA 2C D5 94 3E 2CE 8b/512B 50nm Y Y Y Y Micron 64Gbit MLC-4K MT29F64G08TAA 2C D7 D5 3E 2CE 8b/512B 50nm Y Y Y Y Micron 2Gbit SLC-2K MT29F2G08AAD 2C DA 80 951CE 1b/512B 50nm Y Y Y Y Micron 8Gbit SLC-4K MT29F8G08AAA 2C D3 90 2E 1CE 1b/512B 50nm Y Y Y Y Micron 16Gbit SLC-4K MT29F16G08DAA 2C D3 90 2E 2CE 1b/512B 50nm Y Y Y Y Micron 32Gbit SLC-4K MT29F32G08FAA 2C D5 D1 2E 2CE 1b/512B 50nm Y Y Y Y Micron 4Gbit MLC-2K MT29F4G08MAA 2C DC 84 25 1CE 4b/512B 72nm Y Y Y Y Micron 8Gbit MLC-2KMT29F8G08MAA 2C D3 94 A51CE 4b/512B 72nm Y Y Y Y。

UFD Controller Support Flash ListAU6985AU6987AU6987ANA U6987TAU6989L AU6989NL AU6989AU6989NA U6989AN(SZ 2012-09-10)FLASHB rand T ypeC AP Flash NameCE A U6981Controller备注单通道单通道单通道单通道单通道单通道单通道Samsung SLC 16M K9F2808U0M/A/B/C 1YYSamsung SLC 16M K9F2816Q0C(x16)1Y 1.8vSamsung SLC 32M K9F5608U0M/A/B/C 1Y YSamsung SLC 32M K9F5616U0C(x16)1Y yp 制程PIN Samsung SLC 32M K9F5616U0B(x16)1Y Samsung SLC 64M K9F1208U0M/A/B/C 1Y YSamsung SLC 64M K9F1208Q0C1Y Y1.8v Samsung SLC 64M K9K1216U0C(x16)1Y Samsung SLC 64M K9k1216Q0C(x16)1Y 1.8v Samsung SLC 128M K9K1G08Q0A1Y Y 1.8vSamsung SLC 128M K9K1G08U0M/A/B 1Y Y Samsung SLC 128M K9K1G16U0A(x16)1Y Samsung SLC 256M K9E2G08U0M 1Y Y Samsung SLC 256M K9E2G08U1M 2Y Y Samsung SLC 128M K9F1G08U0M/A 1Y Y Y Y Y Y Y Samsung SLC 128M K9F1G08R0M/A 1Y Y Y Y Y Y 1.8v Samsung SLC 256M K9K2G08U1A2Y Y Y Y Y Y Y 18vSamsung SLC 128M K9F1G16Q0M(x16)1Y Y Y Y Y Y 1.8v Samsung SLC 128M K9F1G16U0M(x16)1Y Y Y Y Y Y Y Samsung SLC 128M K9F1G08U0A 1YY Y Y Y Y Y Samsung SLC 128M K9F1G08R0A 1Y Y Y Y Y Y 1.8v Samsung SLC 256M K9K2G08Q0M/A 1Y Y Y Y Y Y 1.8vSamsungSLC 256M K9K2G08U0M/A 1Y Y Y Y Y Y Y SamsungSLC 512M K9W4G08U1M2Y Y Y Y Y Y Y g Samsung SLC 256M K9K2G16Q0M/A(x16)1Y Y Y Y Y Y 1.8vSamsung SLC 256M K9K2G16U0M/A(x16)1Y Y Y Y Y Y Y Samsung SLC 512M K9W4G16U1M(x16)2Y Y Y Y Y Y Y Samsung SLC 256M K9F2G08U0M1Y Y Y Y Y Y Y Samsung SLC 256M K9F2G16U0M(x16)1Y Y Y Y Y Y Y Samsung SLC 512M K9K4G08U0M 1Y Y Y Y Y Y Y S Samsung SLC 1G K9W8G08U1M 2Y Y Y Y Y Y Y Samsung SLC 128M K9F1G08U0B1Y Y Y Y Y Y Y Samsung SLC 128M K9F1G16Q0B(x16)1Y Y Y Y Y Y 1.8v Samsung SLC 256M K9F2G08U0A 1Y Y Y Y Y Y Y Samsung SLC 256M K9F2G08R0A 1Y Y Y Y Y Y 1.8vSamsung SLC 512M K9F4G08U0M 1Y Y Y Y Y Y Y Samsung SLC 1G K9K8G08U1M 2Y Y Y Y Y Y Y Samsung SLC 1G K9K8G08U0M/A 1Y Y Y Y Y Y Y Samsung SLC 2G K9WAG08U1M/A 2Y Y Y Y Y Y Y SamsungSLC4G K9NBG08U5M/A4YYY Y Y Y YPIN单通道单通道单通道单通道单通道单通道单通道Samsung SLC1G K9K8G08U0D1Y Y Y Y Y Y Samsung SLC2G K9WAG08U1D2Y Y Y Y Y Y Samsung SLC1G K9F8G08U0M50nm1Y Y Y Y Y Y Samsung SLC2G K9KAG08U0M50nm1Y Y Y Y Y Y Samsung SLC4G K9WBG08U1M50nm2Y Y Y Y Y Y Samsung SLC8G K9NCG08U5M50nm4Y YSamsung MLC256M K9G2G08U0M1Y Y Y Y Y Y Y Samsung MLC512M K9G4G08U0B1Y Y Y Y Y Y Y Samsung MLC512M K9G4G08U0M/A1Y Y Y Y Y Y Y Samsung MLC1G K9L8G08U1M2Y Y Y Y Y Y Y Samsung MLC1G K9G8G08U0M1Y Y Y Y Y Y Y gSamsung MLC2G K9LAG08U1M2Y Y Y Y Y Y Y Samsung MLC1G K9G8G08U0A/B1Y Y Y Y Y Y Y Samsung MLC1G K9L8G08U0M/A1Y Y Y Y Y Y Y Samsung MLC2G K9HAG08U1M2Y Y Y Y Y Y Y Samsung MLC4G K9MBG08U5M4Y Y Y Y Y Y Y Samsung MLC2G K9LAG08U0M1Y Y Y Y Y Y Y Samsung MLC4G K9HBG08U1M2Y Y Y Y Y Y YS Samsung MLC8G K9MCG08U5M4Y Y YSamsung MLC2G K9LAG08U0A/B1Y Y Y Y Y Y Y Samsung MLC4G K9HBG08U1A/B2Y Y Y Y Y Y Y Samsung MLC2G K9GAG08U0M50nm1Y Y Y Y Y Y Samsung MLC4G K9LBG08U1M50nm2Y Y Y Y Y Y Samsung MLC8G K9HCG08U5M50nm4Y Y Y Y Y Y Samsung MLC4G K9LBG08U0M50nm1Y Y Y Y Y Y Samsung MLC8G K9HCG08U1M50nm2Y Y Y Y Y Y Samsung MLC16G K9MDG08U5M50nm4Y YSamsung MLC2G K9GAG08U0A50nm1Y Y Y Y Y Y Samsung MLC2G K9GAG08U0D42nm1Y Y Y Y Y Y Samsung MLC4G K9LBG08U1D42nm2Y Y Y Y Y Y Samsung MLC8G K9HCG08U5D42nm4Y Y Y Y Y Y Samsung MLC4G K9LBG08U0D42nm1Y Y Y Y Y Y Samsung MLC8G K9HCG08U1D42nm2Y Y Y Y Y Y Samsung MLC16G K9MDG08U5D42nm4Y YSamsung MLC4G K9GBG08U0M35nm1Y Y Y Y Y Samsung MLC8G K9LCG08U1M35nm2Y Y Y Y Y Samsung MLC16G K9HDG08U5M35nm4Y Y Y Y Y Samsung MLC32G K9PFG08U5M35nm4YSamsung MLC1G K9G8G08U0C35nm1Y Y Y Y Y Samsung MLC2G K9GAG08U0E35nm1Y Y Y Y Y Samsung MLC4G K9LBG08U0E35nm1Y Y Y Y Y Samsung MLC8G K9HCG08U1E35nm2Y Y Y Y Y Samsung MLC16G K9MDG08U5E35nm4YSamsung MLC4G K9GBG08U0A27nm1Y Y Y Y Y gSamsung MLC8G K9LCG08U1A27nm2Y Y Y Y Y Samsung MLC16G K9HDG08U5A27nm4Y Y Y Y Y Samsung MLC8G K9LCG08U0A27nm1Y Y Y Y Y单通道单通道单通道单通道单通道单通道单通道PINSamsung MLC16G K9HDG08U1A27nm2YSamsung MLC2G K9GAG08U0F27nm1Y Y Y Y Y Samsung TLC4G K9ABG08U0M42nm1Y Y Y Y Samsung TLC8G K9BCG08U1M42nm2Y Y Y Y Samsung TLC16G K9CDG08U5M42nm4Y Y Y Y Samsung TLC4G K9ABG08U0A32nm1Y Y Y Y Samsung TLC8G K9BCG08U1A32nm2Y Y Y Y Samsung TLC16G K9CDG08U5A32nm4Y Y Y YSamsung TLC4G K9ABGD8U0B27nm1Y Y flash pin21,28,34,38,39,45 接vcc3.3v flash pin20,27,33,40,46 接GND需贴R12,R15Samsung TLC8G K9ACGD8U0M27nm1Y Y flash pin21,28,34,38,39,45 接vcc3.3v flash pin20,27,33,40,46 接GND需贴R12,R15Samsung TLC16G K9BDGD8U0M27nm1Y Y flash pin21,28,34,38,39,45 接vcc3.3v flash pin20,27,33,40,46 接GND需贴R12,R15flash pin21,28,34,38,39,45 接vcc3.3vSamsung TLC32G K9CFGD8U1M27nm2Y Y flash pin20,27,33,40,46 接GND需贴R12,R15Samsung MLC2G K9GAGD8U0F27nm1Y Y flash pin21,28,34,38,39,45 接vcc3.3v flash pin20,27,33,40,46 接GND需贴R12,R15S27flash pin21,28,34,38,39,45 接vcc3.3v fl h i2027334046Samsung MLC4G K9GBGD8U0A27nm1Y Y flash pin20,27,33,40,46 接GND需贴R12,R15Samsung MLC4G K9GBGD8U0B21nm1Y Y flash pin21,28,34,38,39,45 接vcc3.3v flash pin20,27,33,40,46 接GND需贴R12,R15flash pin21,28,34,38,39,45 接vcc3.3v flash pin2027334046Samsung MLC8G K9GCGD8U0M21nm1Y Y flash pin20,27,33,40,46 接GND需贴R12,R15Samsung TLC2G K9AAGD8U0A21nm1Y flash pin21,28,34,38,39,45 接vcc3.3v flash pin20,27,33,40,46 接GND需贴R12,R15Samsung TLC4G K9ABGD8U0C21nm1Y flash pin21,28,34,38,39,45 接vcc3.3v flash pin20,27,33,40,46 GNDSa su g C G9G8U0C as p0,,33,0,6接G需贴R12,R15Samsung TLC8G K9ACGD8U0A21nm1Y flash pin21,28,34,38,39,45 接vcc3.3v flash pin20,27,33,40,46 接GND需贴R12,R15Micron SLC128M MT29F1G08ABB1Y Y Y Y Y Y 1.8V Micron SLC128M MT29F1G16ABB(x16)1Y Y Y Y Y Y 1.8V Micron SLC128M MT29F1G08ABC1Y Y Y Y Y Y 1.8V Micron SLC128M MT29F1G16ABC(x16)1Y Y Y Y Y Y 1.8V Micron SLC128M MT29F1G08AAC1Y Y Y Y Y Y Y单通道单通道单通道单通道单通道单通道单通道PINMicron SLC128M MT29F1G16AAC(x16)1Y Y Y Y Y Y YMicron SLC128M MT29F1G08AAC1Y Y Y Y Y Y YMicron SLC256M MT29F2G08AAA1Y Y Y Y Y Y YMicron SLC256M MT29F2G16AAA(x16)1Y Y Y Y Y Y YMicron SLC512M MT29F4G08BBC1Y Y Y Y Y Y 1.8V18V Micron SLC512M MT29F4G16BBC(x16)1Y Y Y Y Y Y 1.8VMicron SLC256M MT29F2G08AAB1Y Y Y Y Y Y YMicron SLC256M MT29F2G16AAB(x16)1Y Y Y Y Y Y YMicron SLC512M MT29F4G08BAB1Y Y Y Y Y Y YMicron SLC512M MT29F4G16BAB(x16)1Y Y Y Y Y Y YMicron SLC1G MT29F8G08FAB2Y Y Y Y Y Y YMicron SLC256M MT29F2G08ABD1Y Y Y Y Y Y 1.8vMicron SLC256M MT29F2G16ABD(x16)1Y Y Y Y Y Y 1.8vMicron SLC256M MT29F2G08AAD1Y Y Y Y Y Y YMicron SLC256M MT29F2G16AAD(x16)1Y Y Y Y Y Y YMicron SLC512M MT29F4G08ABA/C1Y Y Y Y Y Y 1.8vMicron SLC512M MT29F4G16ABA/C(x16)1Y Y Y Y Y Y 1.8vMicron SLC512M MT29F4G08AAA/C1Y Y Y Y Y Y YMi MT29F4G16AAA/C(16)Micron SLC512M MT29F4G16AAA/C(x16)1Y Y Y Y Y Y YMicron SLC1G MT29F8G08DAA2Y Y Y Y Y Y YMicron SLC1G MT29F8G08BAA1Y Y Y Y Y Y YMicron SLC1G MT29F8G16BAA(x16)1Y Y Y Y Y Y YMicron SLC2G MT29F16G08FAA2Y Y Y Y Y Y YMicron SLC2G MT29F16G16FAA(x16)2Y Y Y Y Y Y Y18v Micron SLC512M MT29F4G08ABBDA M60A1Y Y Y Y Y Y 1.8vMicron SLC512M MT29F4G16ABBDA(x16)M60A1Y Y Y Y Y Y 1.8vMicron SLC512M MT29F4G08ABADA M60A1Y Y Y Y Y YMicron SLC512M MT29F4G16ABADA(x16)M60A1Y Y Y Y Y YMicron SLC1G MT29F8G08ADBDAH4M60A1Y Y Y Y Y Y 1.8vMicron SLC1G MT29F8G16ADBDAH4(x16M60A1Y Y Y Y Y Y 1.8vMicron SLC1G MT29F8G08ADADAH4M60A1Y Y Y Y Y YMicron SLC1G MT29F8G16ADADAH4(x16M60A1Y Y Y Y Y YMicron SLC256M MT29F2G08ABBEA M69A1Y Y Y Y Y Y 1.8vMicron SLC256M MT29F2G16ABBEA(x16)M69A1Y Y Y Y Y Y 1.8vMicron SLC256M MT29F2G08ABAEA M69A1Y Y Y Y Y YMicron SLC256M MT29F2G16ABAEA(x16)M69A1Y Y Y Y Y YMicron SLC1G MT29F8G08AAA50nm1Y Y Y Y Y YMicron SLC2G MT29F16G08DAA50nm2Y Y Y Y Y YMicron SLC4G MT29F32G08FAA50nm2Y Y Y Y Y YMicron SLC1G MT29H8G08ACAH150nm1Y Y Y Y Y YMicron SLC2G MT29H16G08ECAH150nm2Y Y Y Y Y YMicron SLC4G MT29H32G08GCAH250nm2Y Y Y Y Y YMicron SLC1G MT29F8G08ABABA34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron SLC2G MT29F16G08ABABA34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND单通道单通道单通道单通道单通道单通道单通道PINMicron SLC4G MT29F32G08AFABA34nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron SLC8G MT29F64G08AJABA34nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDS C G298G08C flash pin34,39Micron SLC1G MT29F8G08ABBCA M71M1Y Y Y Y Y Y接vcc3.3v flash pin25,48接GNDMicron SLC1G MT29F8G16ABBCA(x16)M71M1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron SLC1G MT29F8G08ABACA M71M1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDfl h i343933Micron SLC1G MT29F8G16ABACA(x16)M71M1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron SLC2G MT29F16G08ADBCA M71M1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron SLC2G MT29F16G16ADBCA(x16)M71M1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron SLC2G MT29F16G08ADACA M71M1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron SLC2G MT29F16G16ADACA(x16)M71M1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND flash pin34,39接vcc3.3vMicron SLC4G MT29F32G08ABAAA M73A1Y Y Y Y Y Yflash pin25,48接GNDMicron SLC8G MT29F64G08AFAAA M73A2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron SLC16G MT29F128G08AJAAA M73A2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC512M MT29F4G08MAA1Y Y Y Y Y Y Y Micron MLC1G MT29F8G08QAA2Y Y Y Y Y Y Y Micron MLC2G MT29F16G08TAA2Y Y Y Y Y Y Y Micron MLC1G MT29F8G08MAA72nm1Y Y Y Y Y Y Y Micron MLC1G MT29F8G16MAA(x16)72nm1Y Y Y Y Y Y Y Micron MLC2G MT29F16G08QAA72nm2Y Y Y Y Y Y Y Micron MLC4G MT29F32G08TAA72nm2Y Y Y Y Y Y Y Micron MLC1G MT29F8G08MAD50nm1Y Y Y Y Y Y Y Micron MLC1G MT29F8G08MBD50nm1Y Y Y Y Y Y Y Micron MLC2G MT29F16G08MAA50nm1Y Y Y Y Y Y Micron MLC4G MT29F32G08QAA50nm2Y Y Y Y Y Y Micron MLC8G MT29F64G08TAA50nm2Y Y Y Y Y Y Micron MLC4G MT29F32G08NAA50nm1Y Y Y Y Y YMi MLC34Micron4G MT29F32G08MAA34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC8G MT29F64G08CFAAA34nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND单通道单通道单通道单通道单通道单通道单通道PINMicron MLC16G MT29F128G08CJAAA34nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC2G MT29F16G08CBABA34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND flash pin34,39接vcc3.3vMicron MLC4G MT29F32G08CBABA34nm1Y Y Y Y Y Yp,flash pin25,48接GNDMicron MLC8G MT29F64G08CFABA34nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC16G MT29F128G08CJABA34nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC2G MT29F16G08CBACA25nm1Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC4G MT29F32G08CFACA25nm2Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC4G MT29F32G08CBACA25nm1Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND flash pin3439vcc33vMicron MLC8G MT29F64G08CFACA25nm2Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron TLC4G MT29F32G08EBAAA34nm1Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron TLC8G MT29F64G08EFAAA34nm2Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDfl hMicron TLC16G MT29F128G08EJAAA34nm2Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC8G MT29F64G08CBAAA25nm1Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC16G MT29F128G08CFAAA25nm2Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC32G MT29F256G08CJAAA25nm2Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC64G MT29F512G08CUAAA25nm2Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC8G MT29F64G08CBABA20nm 1Y Y Y Y flash pin34,39接vcc3.3v flash pin2548flash pin25,48接GNDMicron MLC16G MT29F128G08CFABA20nm 2Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDMicron MLC32G MT29F256G08CJABA20nm 2Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND flash pin34,39接vcc3.3vMicron TLC8G MT29F64G08EBAAA25nm 1Y Yflash pin25,48接GNDMicron TLC16G MT29F128G08EFAAA25nm 2Y Y flash pin34,39接vcc3.3v flash pin25,48接GND单通道单通道单通道单通道单通道单通道单通道PINIntel SLC512M JS29F04G08AANB11Y Y Y Y Y Y Y Intel SLC1G JS29F08G08CANB11Y Y Y Y Y Y Y Intel SLC1G JS29F08G08BANB12Y Y Y Y Y Y Y Intel SLC2G JS29F16G08FANB12Y Y Y Y Y Y Y50nmIntel SLC1G JS29F08G08AANC11Y Y Y Y Y Y Intel SLC2G JS29F16G08CANC150nm2Y Y Y Y Y Y Intel SLC4G JS29F32G08FANC150nm2Y Y Y Y Y YIntel SLC1G JS29F08G08AAND1/234nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel SLC2G JS29F16G08AAND1/234nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin2548flash pin25,48接GNDIntel SLC4G JS29F32G08CAND1/234nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel SLC8G JS29F64G08JAND1/234nm4Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel SLC16G JS29F16B08JAND134nm4Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin2548flash pin25,48接GNDIntel MLC1G JS29F08G08AAMB11Y Y Y Y Y Y Y Intel MLC1G JS29F08G08AAMC11Y Y Y Y Y Y Y Intel MLC2G JS29F16G08CAMB12Y Y Y Y Y Y Y Intel MLC4G JS29F32G08FAMB12Y Y Y Y Y Y Y Intel MLC2G JS29F16G08AAMC150nm1Y Y Y Y Y Y Intel MLC4G JS29F32G08CAMC150nm2Y Y Y Y Y Y Intel MLC8G JS29F64G08FAMC150nm2Y Y Y Y Y YIntel MLC4G JS29F32G08AAMD1/234nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC8G JS29F64G08CAMD1/234nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC16G JS29F16B08JAMD1/234nm4Y Y flash pin34,39接vcc3.3v fl h i2548/flash pin25,48接GNDIntel MLC2G JS29F16G08AAMDB34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC4G JS29F32G08AAMDA/B34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC8G JS29F64G08CAMDA/B34nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC16G JS29F16B08JAMDA/B34nm4Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC2G JS29F16G08AAME125nm1Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC4G JS29F32G08AAME125nm1Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC8G JS29F64G08CAME125nm2Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC16G JS29F16B08AAME125nm4Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND单通道单通道单通道单通道单通道单通道单通道PINIntel MLC8G JS29F64G08AAME125nm1Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC16G JS29F16B08CAME125nm2Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC32G JS29F32B08JAME125nm4Y Y Y Y Y flash pin34,39接vcc3.3v flash pin2548flash pin25,48接GNDIntel MLC8G JS29F64G08AAMF120nm 1Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC16G JS29F16B08CAMF120nm 2Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel MLC32G JS29F32B08JAMF120nm 4Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48GNDp,接Intel TLC8G JS29F64G08AATE125nm 1Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel TLC16G JS29F16B08CATE125nm 2Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDIntel TLC32G JS29F32B08JATE125nm 4Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDSpectek SLC128M FxxM58Axxxxxxx1Y Y Y Y Y Y Spectek SLC128M FxxMx9xxxK3WG1Y Y Y Y Y Y Spectek SLC512M FxxM40AxxK3xG1Y Y Y Y Y Y Spectek SLC512M FxxMx9xxxK3W21Y Y Y Y Y Y Spectek SLC1G FxxM40AxxK3x22Y Y Y Y Y Y Spectek SLC1G FxxMx9xxxK3W42Y Y Y Y Y Y Spectek SLC2G FxxM40AxxK3x42Y Y Y Y Y Y Spectek SLC1G FxxM51AxxK3xG50nm1Y Y Y Y Y Y Spectek SLC2G FxxM51AxxK3x250nm2Y Y Y Y Y Y Spectek SLC4G FxxM51AxxK3x450nm2Y Y Y Y Y YSpectek SLC1G FxxM61AxxK3xG34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDSpectek SLC2G FxxM62BxxK3xG34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDSpectek SLC4G FxxM62BxxK3x234nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDSpectek SLC8G FxxM62BxxK3x434nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDSpectek MLC1G FxxL41BxxK3xG1Y Y Y Y Y Y Spectek MLC1G FxxL51AxxK3xG1Y Y Y Y Y Y Spectek MLC2G FxxL41BxxK3x22Y Y Y Y Y Y Spectek MLC4G FxxL41BxxK3x42Y Y Y Y Y Y Spectek MLC2G FxxL52AxxK3xG50nm1Y Y Y Y Y Y Spectek MLC4G FxxL52AxxK3x250nm2Y Y Y Y Y Y Spectek MLC8G FxxL52AxxK3x450nm2Y Y Y Y Y YSpectek MLC4G FxxL63AxxK3xG34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND单通道单通道单通道单通道单通道单通道单通道PINSpectek MLC8G FxxL63AxxK3x234nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDSpectek MLC16G FxxL63AxxK3x434nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND flash pin34,39接vcc3.3vSpectek MLC2G FxxL62AxxK3xG34nm1Y Y Y Y Y Yflash pin25,48接GNDSpectek MLC4G FxxL63BxxK3xG34nm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDSpectek MLC8G FxxL63BxxK3x234nm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GND flash pin34,39接vcc3.3vSpectek MLC16G FxxL63BxxK3x434nm2Y Y Y Y Y Yflash pin25,48接GNDSpectek MLC4G FxxL73AxxK3xx2xnm1Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDSpectek MLC8G FxxL73AxxK3xx2xnm2Y Y Y Y Y Y flash pin34,39接vcc3.3v flash pin25,48接GNDSpectek MLC8G FxxL74A61K3Bxx25nm1Y Y Y Y YSpectek MLC16G FxxL74A71K3Fxx25nm2Y Y Y Y YSpectek MLC32G FxxL74A81K3Jxx25nm2Y Y Y Y Y Renesas AG-N32M HN29V25611T-501YRenesas AG-N64M HN29V51211T-501YRenesas AG-N64M DFT512W08B-P11YAG N HN29V1G91T30Renesas AG-N128M HN29V1G91T-301Y YRenesas AG-N512M R1FV04G13RSA-31Y YPowerFlash SLC64M PF79AL12081Y YPowerFlash SLC64M PF79BL12081Y YPowerFlash SLC256M ASU2GA30GT1Y Y YPowerFlash SLC512M ASU4GA30GT1Y Y YPowerFlash SLC128M ASU1GA30HT1Y Y YPowerFlash SLC128M ASU1GA40HT(x16)1Y Y YPowerFlash MLC512M A1U4GA30GT1Y Y YPowerFlash MLC1G A1U8GA30GT1Y Y YPowerFlash MLC2G P1UAGA30AT1YH i SLC16M HY27US08281A1YHynix YHynix SLC16M HY27US16281A(x16)1YHynix SLC32M HY27US08561M/A1Y YHynix SLC32M HY27US16562M/A(x16)1YHynix SLC32M HY27SS08561M/A1Y 1.8v Hynix SLC32M HY27SS16561M/A(x16)1 1.8v Hynix SLC64M HY27US08121M/A1Y YHynix SLC64M HY27US16121M/A(x16)1YHynix SLC64M HY27SS08121M/A1Y 1.8v Hynix SLC64M HY27SS16121M/A(x16)1 1.8vPIN单通道单通道单通道单通道单通道单通道单通道Hynix SLC128M HY27UA081G4M2Y YHynix SLC128M HY27(U/S)A081G1M1Y 3.3v/1.8v Hynix SLC128M HY27(U/S)A161G1M(x16)1 3.3v/1.8v Hynix SLC256M HY27(U/S)B082G4M2Y 3.3v/1.8v Hynix SLC256M HY27(U/S)B162G4M(x16)2 3.3v/1.8v Hynix SLC128M HY27SS081G1X1 1.8vY18v Hynix SLC128M HY27UF081G2M1Y Y Y Y Y Y YHynix SLC128M HY27SF081G2M(x16)1Y Y Y Y Y Y 1.8v Hynix SLC256M HY27UF082G2M1Y Y Y Y Y Y YHynix SLC256M HY27SF082G2M1Y Y Y Y Y Y 1.8v Hynix SLC256M HY27UF162G2M(x16)1Y Y Y Y Y Y Yy()Hynix SLC256M HY27SF162G2M(x16)1Y Y Y Y Y Y 1.8v Hynix SLC512M HY27UG084G2M1Y Y Y Y Y Y YHynix SLC512M HY27SG084G2M1Y Y Y Y Y Y 1.8v Hynix SLC512M HY27UG164G2M(x16)1Y Y Y Y Y Y YHynix SLC512M HY27SG164G2M(x16)1Y Y Y Y Y Y 1.8v Hynix SLC1G HY27UH088G2M1Y Y Y Y Y Y YHynix SLC128M HY27UF081G2A1Y Y Y Y Y Y YH iHynix SLC256M HY27UF082G2A1Y Y Y Y Y Y YHynix SLC256M HY27UF162G2A(x16)1Y Y Y Y Y Y YHynix SLC256M HY27SF162G2A(x16)1Y Y Y Y Y Y 1.8v Hynix SLC512M HY27UF084G2M1Y Y Y Y Y Y YHynix SLC1G HY27UF084G2M2Y Y Y Y Y Y YHynix SLC1G HY27UG088G2M1Y Y Y Y Y Y YHynix SLC2G HY27UH08AG5M2Y Y Y Y Y Y YHynix SLC4G HY27UK08BGFM4Y Y YHynix SLC256M HY27UF082G2B1Y Y Y Y Y Y YHynix SLC256M HY27SF082G2B(x16)1Y Y Y Y Y Y 1.8v Hynix SLC512M HY27UF084G2B1Y Y Y Y Y Y YHynix SLC512M HY27UF164G2B(x16)1Y Y Y Y Y Y YHynix SLC512M HY27SF084G2B1Y Y Y Y Y Y 1.8v Hynix SLC512M HY27SF164G2B(x16)1Y Y Y Y Y Y 1.8v Hynix SLC1G HY27UG088G5B2Y Y Y Y Y Y YHynix SLC2G HY27UH08AG5B2Y Y Y Y Y Y YHynix SLC4G HY27UK08BGFB4Y Y YHynix SLC128M H27U1G8F2B41nm1Y Y Y Y Y Y YHynix SLC1GB H27U8G8F2M48nm1Y Y Y Y Y YHynix SLC2GB H27UAG8G5M48nm2Y Y Y Y Y YHynix SLC4GB H27UBG8H5M48nm2Y Y Y Y Y YHynix SLC8GB H27UCG8KFM48nm4Y YHynix MLC512M HY27UT084G2M90nm1Y Y Y Y Y Y YHynix MLC1G HY27UU088G5M90nm2Y Y Y Y Y Y YHynix MLC2G HY27UV08AG5M90nm2Y Y Y Y Y Y YHynix MLC4G HY27UW08BGFM90nm4Y Y Y Y Y Y YyHynix MLC1G HY27UT088G2M60nm1Y Y Y Y Y Y YHynix MLC2G HY27UU08AG5M60nm2Y Y Y Y Y Y YHynix MLC4G HY27UV08BGFM60nm4Y Y Y Y Y Y YPIN单通道单通道单通道单通道单通道单通道单通道Hynix MLC1G Hynix InkDie60nm1Y Y Y Y Y Y YHynix MLC4G HY27UV08BG5M60nm2Y Y Y Y Y Y YHynix MLC8G HY27UW08CGFM60nm4Y Y YHynix MLC512M HY27UT084G2A57nm1Y Y Y Y Y Y YHynix MLC1G HY27UT088G2A57nm1Y Y Y Y Y Y YHynix MLC2G HY27UU08AG5A57nm2Y Y Y Y Y Y YHynix MLC4G HY27UV08BGFA57nm4Y Y Y Y Y Y YHynix MLC4G HY27UV08BG5A57nm2Y Y Y Y Y Y YHynix MLC256M H27U2G8T2M48nm1Y Y Y Y Y Y YHynix MLC512M H27U4G8T2B48nm1Y Y Y Y Y Y YHynix MLC1G H27U8G8T2B48nm1Y Y Y Y Y YyHynix MLC2G H27UAG8T2M48nm1Y Y Y Y Y YHynix MLC4G H27UBG8U5M48nm2Y Y Y Y Y YHynix MLC8G H27UCG8VFM48nm4Y Y Y Y Y YHynix MLC8G H27UCG8V5M48nm2Y Y Y Y Y YHynix MLC16G H27UDG8WFM48nm4Y YHynix MLC2G H27UAG8T2A41nm1Y Y Y Y Y YHynix MLC4G H27UBG8U5A41nm2Y Y Y Y Y YH i41Hynix MLC8G H27UCG8V5A41nm2Y Y Y Y Y YHynix MLC4G H27UBG8T2M41nm1Y Y Y Y YHynix MLC8G H27UCG8UDM41nm2Y Y Y Y YHynix MLC16G H27UDG8VEM41nm4Y Y Y Y YHynix TLC2G H27UAG8M2MYR41nm1Y Y Y Y YHynix TLC8G H2EUCG8N1MYR48nm2YHynix TLC16G H2EUDG8M1MYR48nm4YHynix TLC4G H27UBG8M2A32nm1Y Y Y Y YHynix MLC2G H27UAG8T2B1Y Y Y Y YHynix MLC4G H27UBG8T2A32nm1Y Y Y Y YHynix MLC8G H27UCG8U5A32nm2Y Y Y Y YHynix MLC16G H27UDG8VFA32nm4Y Y Y Y YHynix MLC16G H27UDG8V5A32nm2Y Y Y Y YHynix MLC32G H27UEG8YEA32nm4Y Y Y Y YHynix MLC8G H27UCG8T2MYR26nm1YHynix MLC4G H27UBG8T2BTR26nm1YHynix MLC8G H27UCG8T2ATR20nm1Y Y Y YHynix MLC4G H27UBG8T2CTR20nm1Y Y Y YHynix MLC16G H2DTDG8UD1MYR32nm2Y E2NAND Hynix MLC32G H2DTEG8VD1MYR32nm2Y E2NAND Hynix MLC64G H2DTFG8YD1MYR32nm2Y E2NAND ST SLC16M NAND128R3A1Y 1.8VST SLC16M NAND128W3A1Y YST SLC16M NAND128R4A(x16)1 1.8VST SLC16M NAND128W4A(x16)1Y()ST SLC32M NAND256R3A1Y 1.8VST SLC32M NAND256W3A1Y YST SLC32M NAND256R4A(x16)1 1.8VPIN单通道单通道单通道单通道单通道单通道单通道ST SLC32M NAND256W4A(x16)1YST SLC64M NAND512R3A1Y 1.8V ST SLC64M NAND512W3A1Y YST SLC64M NAND512R4A(x16)1 1.8V ST SLC64M NAND512W4A(x16)1YST SLC128M NAND01GR3A1 1.8VY18V ST SLC128M NAND01GW3A1Y YST SLC128M NAND01GR4A(x16)1 1.8V ST SLC128M NAND01GW4A(x16)1YST SLC64M NAND512W3B1Y Y Y Y Y Y YST SLC128M NAND01GW3B2A1Y Y Y Y Y Y YST SLC256M NAND02GW3B2A1Y Y Y Y Y Y YST SLC128M NAND01GR3B2B1Y Y Y Y Y Y 1.8v ST SLC128M NAND01GW3B2B1Y Y Y Y Y Y YST SLC128M NAND01GR4B2B(x16)1Y Y Y Y Y Y 1.8v ST SLC128M NAND01GW4B2B(x16)1Y Y Y Y Y Y YST SLC128M NAND01GR3B2C1Y Y Y Y Y Y 1.8v ST SLC128M NAND01GW3B2C1Y Y Y Y Y Y Y NAND01GR4B2C(16)18 ST SLC128M NAND01GR4B2C(x16)1Y Y Y Y Y Y 1.8v ST SLC128M NAND01GW4B2C(x16)1Y Y Y Y Y Y YST SLC256M NAND02GR3B2C1Y Y Y Y Y Y 1.8v ST SLC256M NAND02GW3B2C1Y Y Y Y Y Y YST SLC256M NAND02GR4B2C(x16)1Y Y Y Y Y Y 1.8v ST SLC256M NAND02GW4B2C(x16)1Y Y Y Y Y Y YST SLC256M NAND02GR3B2D1Y Y Y Y Y Y 1.8v18v ST SLC256M NAND02GW3B2D1Y Y Y Y Y Y YST SLC256M NAND02GR4B2D(x16)1Y Y Y Y Y Y 1.8v ST SLC256M NAND02GW4B2D(x16)1Y Y Y Y Y Y YST SLC512M NAND04GW3B2B1Y Y Y Y Y Y YST SLC1G NAND08GW3B2A1Y Y Y Y Y Y YST SLC512M NAND04GR3B2D1Y Y Y Y Y Y 1.8v ST SLC1G NAND08GR3B4C2Y Y Y Y Y Y 1.8v ST SLC512M NAND04GW3B2D1Y Y Y Y Y Y YST SLC1G NAND08GW3B4C2Y Y Y Y Y Y YST SLC2G NAND16GW3B6D4Y Y Y Y Y Y YST SLC512M NAND04GR4B2D(x16)1Y Y Y Y Y Y 1.8v ST SLC512M NAND04GW4B2D(x16)1Y Y Y Y Y Y YST SLC1G NAND08GR3B2C1Y Y Y Y Y Y 1.8v18v ST SLC1G NAND08GW3B2C1Y Y Y Y Y Y YST SLC2G NAND16GW3B4D2Y Y Y Y Y Y YST SLC1G NAND08GR4B2C(x16)1Y Y Y Y Y Y 1.8v ST SLC1G NAND08GW4B2C(x16)1Y Y Y Y Y Y YST SLC1G NAND08GW3F2A1Y Y Y Y Y YST SLC2G NAND16GW3F4A2Y Y Y Y Y YST SLC2G NAND16GW3F2A1Y Y Y Y Y YST SLC4G NAND32GW3F4A2Y Y Y Y Y YST MLC512M NAND04GW3C2A1Y Y Y Y Y Y Y单通道单通道单通道单通道单通道单通道单通道PINST MLC1G NAND08GW3C2A1Y Y Y Y Y Y Y ST MLC2G NAND16GW3C2A1Y Y Y Y Y Y Y ST MLC512M NAND04GW3C2B1Y Y Y Y Y Y Y ST MLC1G NAND08GW3C2B1Y Y Y Y Y Y Y ST MLC2G NAND16GW3C4B2Y Y Y Y Y Y Y ST MLC2G NAND16GW3C2B1Y Y Y Y Y Y Y ST MLC1G NAND08GW3D2A1Y Y Y Y Y Y ST MLC2G NAND16GW3D2A1Y Y Y Y Y Y ST MLC4G NAND32GW3D4A2Y Y Y Y Y Y ST MLC8G NAND64GW3D4A2Y Y Y Y Y Y Toshiba SLC16M TC58DVM72A1FT001Y YToshiba SLC32M TC58DVM82A1FT001Y YToshiba SLC64M TC58DVM92A1FT001Y YToshiba SLC128M TC58DVG02A1FT001Y YToshiba SLC256M TC58DVG12A1FT001Y YToshiba SLC128M TC58NVG0S3AFT051Y Y Y Y Y Y Y Toshiba SLC128M TC58NVG0S3BTG001Y Y Y Y Y Y YT hibToshiba SLC256M TH58NVG1S3AFT051Y Y Y Y Y Y Y Toshiba SLC64MB TC58NVM9S3BTG001Y Y Y Y Y Y Y Toshiba SLC64MB TC58NVM9S8CTA00(x16)1Y Y Y Y Y Y Y Toshiba SLC128M TC58NVG0S3BTGI01Y Y Y Y Y Y Y Toshiba SLC256M TC58NVG1S3BFT001Y Y Y Y Y Y Y Toshiba SLC256M TC58NVG1S3BFT001Y Y Y Y Y Y Y Toshiba SLC256M TC58NVG1S8BFT00(x16)1Y Y Y Y Y Y Y Toshiba SLC256M TC58NVG1S8BFT00(x16)1Y Y Y Y Y Y Y Toshiba SLC512M TH58NVG2S3BFT001Y Y Y Y Y Y YToshiba SLC128M TC58NVG0S3ETA0043nm1Y Y Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba SLC256M TC58NVG1S3ETA0043nm1Y Y Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2232548flash pin2,23,25,48 接GNDToshiba SLC1G TC58NVG3S0DTG0056nm1Y Y Y Y Y Y Toshiba SLC2G TH58NVG4S0DTG2056nm2Y Y Y Y Y Y Toshiba SLC4G TC58NVG5S0DTG2056nm2Y Y Y Y Y Y Toshiba MLC64M TC58DVM94B1FT001YToshiba MLC128M TC58DVG04B1TG001YToshiba MLC256M TC58DVG14B1TG001YToshiba MLC512M TH58DVG24B1TG001YToshiba MLC256M TC58NVG1D4BTG001Y Y Y Y Y Y Y Toshiba MLC512M TC58NVG2D4BTG001Y Y Y Y Y Y Y Toshiba MLC512M TC58NVG2D9BTG00(x16)1Y Y Y Y Y Y Y Toshiba MLC1G TH58NVG3D4BTG001Y Y Y Y Y Y Y Toshiba MLC1G TC58NVG3D4CTG001Y Y Y Y Y Y Y T hib TC58NVG3D9CTG00(16)Toshiba MLC1G TC58NVG3D9CTG00(x16)1Y Y Y Y Y Y Y Toshiba MLC2G TH58NVG4D4CTG001Y Y Y Y Y Y Y Toshiba MLC2G TH58NVG4D9CTG00(x16)1Y Y Y Y Y Y Y Toshiba MLC4G TH58NVG5D4CTG202Y Y Y Y Y Y Y单通道单通道单通道单通道单通道单通道单通道PINToshiba MLC8G TH58NVG6D4CTG202Y Y YToshiba MLC512M TC58NVG2D1DTG0056nm1Y Y Y Y Y Y Toshiba MLC1G TC58NVG3D1DTG0056nm1Y Y Y Y Y Y Toshiba MLC2G TH58NVG4D1DTG0056nm1Y Y Y Y Y Y Toshiba MLC2G TC58NVG4D1DTG00(x16)56nm1Y Y Y Y Y Y Toshiba MLC4G TH58NVG5D1DTG2056nm2Y Y Y Y Y Y Toshiba MLC8G TH58NVG6D1DTG8056nm4Y Y Y Y Y Y Toshiba MLC4G TH58NVG5D1DTG0056nm1Y Y Y Y Y Y Toshiba MLC8G TH58NVG6D1DTG2056nm2Y Y Y Y Y Y Toshiba MLC16G TH58NVG7D1DTG8056nm4Y YToshiba MLC8G TH58NVG6D1DTG0056nm1Y Y Y Y Y Y Toshiba MLC16G TH58NVG7D1DTG2056nm2Y YToshiba MLC1G TC58NVG3D2ETA0043nm1Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC2G TC58NVG4D2ETA0043nm1Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC4G TH58NVG5D2ETA2043nm2Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2232548flash pin2,23,25,48 接GNDToshiba MLC4G TC58NVG5D2ETA0043nm1Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC4G TH58NVG5D2ETA0043nm1Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GND flash pin１,24,34,38 接vcc3.3vToshiba MLC8G TH58NVG6D2ETA2043nm2Y Y Y Y Yflash pin2,23,25,48 接GNDToshiba MLC8G TH58NVG6D2ETA0043nm1Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC16G TH58NVG7D2ELA8943nm4Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GND flash pin243438 vcc33vToshiba MLC16G TH58NVG7D2ELA4943nm2Y１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC32G TH58NVG8D2ELA8943nm4Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC2G TC58NVG4D2FTA0032nm1Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC4G TC58NVG5D2FTA0032nm1Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC8G TH58NVG6D2FTA2032nm2Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC16G TH58NVG7D2FTA8032nm4Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GNDToshiba MLC16G TH58NVG7D7FTA80(x16)32nm4Y Y Y Y Y flash pin１,24,34,38 接vcc3.3v flash pin2,23,25,48 接GND。