MPC860_SIUIntControl
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11 - 1SIU Interrupt ControllerSIU Interrupt Controller11 - 2SIU Interrupt ControllerSIU Interrupts•CPIC Generates an interrupt to the SIU Interrupt Controller at a User Programmable Level
To SIU Interrupt Controller
•SIU Receives an interrupt from 1 of 8 external sources or 1 of 8 internal sources
–Assuming no masking•SIU asserts the IREQ input to the EPPC CoreLevel 2
Level 7Level 6Level5Level 4Level 3
Level 1Level 0
IREQEPPCCORE
DEC
DEBUGCommunication Processor Module (CPM)
PORT C[4:15]TIMER1TIMER2TIMER3TIMER4SCC1
SCC2SMC1
SPII2C
PIP
SMC2
IDMA1IDMA2SDMARISC TIMERS
IREQ[0:7]0IRQ
NMIGEN
System Interface Unit (SIU)TBPITRTCPCMCIA
SWTDEC
DEBUGEdge/LevelNMI
SIU
INT
CNTRLR
CPM
INT
CNTRLR11 - 3SIU Interrupt Controller
StartSIU Interrupt occursSet bit in SIPEND
YBit set in SIMASK ?ENDN
To IREQ of EPPC
Flow Diagram: How SIU Processes an Interrupts 11 - 4SIU Interrupt Controller
Vector TableHARD & SRESETSIRQ[1 :7], PIT, TB, RTC, PCMCIA, CPMALIGNMENT ERRORINSTR. TRAPS,ERRORS, ILLEGAL, PRIVILEGEDMSR[FP]=0 & F.P. INSTRUCTION ENCOUNTEREDDECREMENTER REGISTER 'SC' INSTRUCTIONTEA (BUS ERROR)SINGLE-STEP OR BRANCH TRACINGSOFTWARE ASSIST FOR INFREQUENT &COMPLEX FP OPERATIONSVECTOROFFSET(HEX)EXCEPTION TYPERESERVEDSYSTEM RESETMACHINE CHECKDATA STORAGEINSTRUCTION STORAGEEXTERNAL INTERRUPTALIGNMENTPROGRAMFLOATING-POINT UNAVAILABLEDECREMENTERRESERVEDRESERVEDSYSTEM CALLTRACE*FLOATING-POINT ASSIST*IMPLEMENTATION DEPENDENT SOFTWARE EMULATIONIMPLEMENTATION DEPENDENT INSTRUCTION TLB MISSIMPLEMENTATION DEPENDENT DATA TLB MISSIMPLEMENTATION DEPENDENT INSTRUCTION TLB ERRORIMPLEMENTATION DEPENDENT DATA TLB ERRORRESERVEDIMPLEMENTATION DEPENDENT DATA BREAKPOINTIMPLEMENTATION DEPENDENT INSTRUCTION BREAKPOINTIMPLEMENTATION DEPENDENT PERIPHERAL BREAKPOINTIMPLEMENTATION DEPENDENT NON MASKABLE DEVELOPMENT PORT0 1500 - 01BFF0 00000 01000 02000 03000 04000 05000 06000 07000 08000 09000 0A000 0B00
0 0D000 0C00
0 0E000 10000 11000 12000 13000 1400
0 1C000 1D000 1E000 1F0011 - 5SIU Interrupt Controller
SIU Interrupt SourcesModuleConfiguration
BusMonitor
Periodic IntTimer
SoftwareWatchdog
PPCDecrementer
PPCTime Base
Real TimeClock
Clock
TEA signalinterruptinterrupt osystem rese
interrupt
interruptinterrupt
System Configuration and Protection LogicLevel 2Level 7Level 6Level5Level 4Level 3
Level 1Level 0
NMIIRQ[0:7]IREQNMIGEN
EPPCCORE
SIUTBPITRTCPCMCIACPM
SWTIRQ0
DECDEC
DEBUGDEBUG11 - 6SIU Interrupt ControllerPriority of SIU Interrupt Sources
•IRQx Pins have a fixed priority level Example: IRQ0 Highest Priority Level (Code = 00000000) IRQ7 Lowest Priority Level (Code = 00111000)•Interrupt Code(SIVEC reg) defines interrupt priority level•IRQx Interrupt Codes are only associated with IRQx pins•IRQx interrupt source has highest priority than LEVELx Example: If both IRQ3 and LEVEL3 interrupt simultaneously IRQ3 will be acknowledged first
NumberPriorityLevelInterrupt SourceDescriptionInterruptCode
0HighestIRQ0000000001LEVEL 0000001002IRQ1000010003LEVEL 1000011004IRQ2000100005LEVEL 2000101006IRQ3000110007LEVEL 3000111008IRQ4001000009LEVEL 40010010010IRQ50010100011LEVEL 50010110012IRQ60011000013LEVEl 60011010014IRQ70011100015LowestLEVEL 70011110016 -31Reserved11 - 7SIU Interrupt Controller
Interrupt Sources vs. LevelsSourceLevelNMI:SWTIRQ0_L
External Pins: IRQ1_LLevel 1 IRQ2_LLevel 2 IRQ3_LLevel 3 IRQ4_LLevel 4 IRQ5_LLevel 5 IRQ6_LLevel 6IRQ7_LLevel 7
Internal: PITAssignable between 0:7 RTCAssignable between 0:7TBAssignable between 0:7CPMAssignable between 0:7
•Each interrupt source is identified by a level•PIT,RTC, TB, CPM levels are assigned using register PISCR, RTCSC, TBSCR, CICR respectively(disscussed later)
