EDA多路选择器设计实验报告

EDA多路选择器设计实验报告

多路选择器设计实验

一、实验目的:

进一步熟悉Quartus II的Verilog文本设计流程，组合电路的设计仿真和硬件测

试。

二、实验内容:

1、根据4.1节流程，利用Quartus II完成4选1多路选择器的文本代码编辑输

入和仿真测试等步骤，给出仿真波形。

2、在实验系统上硬件测试，验证此设计的功能。

三、实验程序:

Quartus II程序:

module mux41a(a,b,c,d,s0,s1,y);

input a,b,c,d;

input s0,s1;

output y;

reg y;

always@(a,b,c,d,s0,s1)

begin :mux41

case({s0,s1})

2'b00:y<=a;

2'b01:y<=b;

2'b10:y<=c;

2'b11:y<=d;

default :y<=a;

endcase

end

endmodule

modelsim程序:

// Copyright (C) 1991-2012 Altera Corporation

// Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details.

//

******************************************************************** *********

// This file contains a Verilog test bench template that is freely editable to

// suit user's needs .Comments are provided in each section to help the user

// fill out necessary details.

//

******************************************************************** *********

// Generated on "10/11/2015 21:31:33"

// Verilog Test Bench template for design : mux41a

//

// Simulation tool : ModelSim-Altera (Verilog)

//

`timescale 1 us/ 1 ps

module mux41a_vlg_tst();

// constants // general purpose registers

//reg eachvec;

// test vector input registers

reg a;

reg b;

reg c;

reg d;

reg s0;

reg s1;

// wires wire y;

// assign statements (if any) mux41a i1 (

// port map - connection between master ports and signals/registers .a(a),

.b(b),

.c(c),

.d(d),

.s0(s0),

.s1(s1),

.y(y)

);

initial

begin

a=0;b=0;

c=0;d=0;

s0=0;s1=0;

#20 s0=0;s1=1;

#20 s0=1;s1=0;

#20 s0=1;s1=1;

#20 $stop;

end

always #2 a=~a;

always #4 b=~b;

always #6 c=~c;

always #8 d=~d;

endmodule