LM29153RS-3.0中文资料

ABSOLUTE MAXIMUM RATINGS
SYMBOL VS VIN Supply voltage, V+ Differential input voltage Input voltage Maximum power dissipation TA=25°C (Still air)1 FE package N package D package Output short-circuit to GND5 V+<15 VDC and TA=25°C Operating ambient temperature range NE532/LM358/LM358A TA LM258 LM2904 SA532 SE532/LM158 TSTG TSOLD Storage temperature range Lead soldering temperature (10sec max) 0 to +70 -25 to +85 -40 to +125 -40 to +85 -55 to +125 -65 to +150 300 °C °C °C °C °C °C °C Continuous PARAMETER RATING 32 or ±16 32 -0.3 to +32 UNIT VDC VDC VDC
Philips Semiconductors
Product specification
Low power dual operational amplifiers
NE/SA/SE532/ LM158/258/358/A/2904
DESCRIPTION
The 532/358/LM2904 consists of two independent, high gain, internally frequency-compensated operational amplifiers internally frequency-compensated operational amplifiers designed specifically to operate from a single power supply over a wide range of voltages. Operation from dual power supplies is also possible, and the low power supply current drain is independent of the magnitude of the power supply voltage.

L295DUAL SWITCH-MODE SOLENOID DRIVERPRELIMINARY DATAHIGH CURRENT CAPABILITY (up to 2.5A per channel)HIGH VOLTAGE OPERATION (up to 46V for power stage)HIGH EFFICIENCY SWITCHMODE OPERATION REGULATED OUTPUT CURRENT (adjustable)FEW EXTERNAL COMPONENTS SEPARATE LOGIC SUPPLY THERMAL PROTECTIONDESCRIPTIONThe L295 is a monolithic integrated circuit in a 15 -lead Multiwatt ® package; it incorporates all the functions for direct interfacing between digital cir-cuitry and inductive loads. The L295 is designed to accept standard microprocessor logic levels at the inputs and can drive 2 solenoids. The output current is completely controlled by means of a switch-March 1993ABSOLUTE MAXIMUM RATINGSing technique allowing very efficient operation.Furthermore, it includes an enable input and dual supplies (for interfacing with peripherals running at a higher voltage than the logic).The L295 is particularly suitable for applications such as hammer driving in matrix printers, stepmotor driving and electromagnet controllers.APPLICATION CIRCUIT1/8CONNECTION DIAGRAM(top view)BLOCK DIAGRAMSymbol ParameterValue Unit R th-j-case Thermal resistance junction-case max 3°C/W R th-j-ambThermal resistance junction-ambientmax35°C/WTHERMAL DATA(*) V drop = V CEsat Q1 + V CEsat Q2.ELECTRICAL CHARACTERISTICS (Refer to the application circuit, V ss = 5V, V s = 36V; T j = 25°C; L =Low; H = High; unless otherwise specified)APPLICATION CIRCUITD2, D4 = 2A High speed diodesD1, D3 = 1A High speed diodesR1 = R2 = 2ΩL1 = L2 = 5 mH)trr ≤ 200 ns FUNCTIONAL DESCRIPTIONThe L295 incorporates two indipendent driver channals with separate inputs and outputs, each capable of driving an inductive load (see block diagram).The device is controlled by three micriprocessor compatible digital inputs and two analog inputs. These inputs are:EN chip enable (digital input, active low), enables both channels when in the lowstate.V in1, V in2channel inputs (digital inputs, active high), enable each channel inde-pendently. A channel is actived whenboth EN and the appropriate channelinput are active.V ref1, V ref2 referce voltages (analog inputs), used to program the peak load currents.Peak load current is proportional to V ref.Since the two channels are identical, only channel one will be described.The following description applies also the channel two, replacing FF2 for FF1, V ref for V ref1 etc. When the channel is avtivated by low level on the EN input and a high level on the channel input, V in2, the output transistors Q1 and Q2 switch on and current flows in the load according to the exponen-tial law:I =VR1( 1 − e− R1 tL1)where:R1 and R2 are the resistance and in-ductance of the load and V is the volt-age available on the load (V s - V drop -V sense).The current increases until the voltage on the ex-ternal sensing resistor, R S1, reaches the reference voltage, V ref1. This peak current, I p1, is given by:I p1=V ref1R S1At this point the comparator output, Vomp1, sete the RS flip-flop, FF1, that turns off the output tran-sistor, Q1. The load current flowing through D2, Q2, R S1, decreases according to the law:I =(V AR1+ I p1) e− R1 tL1−V AR1 where V A = V CEsat Q2 + V sense + V D2If the oscillator pin (9) is connected to ground the load current falls to zero as shown in fig. 1.At this time t2 the channel 1 is disabled, by taking the inputs V in1 low and/or EN high, and the output transistor Q2 is turned off. The load current flows through D2 and D1 according to the law:I =(V BR1+ I T2) e− R1 tL1−V BR1where V B = V S + V D1 + V D2I T2 = current value at the time t2.Fig. 2 in shows the current waveform obtained with an RC network connected between pin 9 and ground. From to t1 the current increases as in fig.1. A difference exists at the time t2 because the current starts to increase again. At this time a pulse is produced by the oscillator circuit that resets the flip.flop, FF1, and switches on the outout transistor, Q1. The current increases until the drop on the sensing resistor R S1 is equal to V ref1 (t3) and the cycle repeats.SIGNAL WAVEFORMS The switching frequency depends on the value R and C, as shown in fig. 4 and must be chosen in the range 10 to 30 KHz.It is possible with external hardware to change the reference voltage V ref in order to obtain a high peak current I p and a lower holding current I h (see fig. 3). The L295 is provided with a thermal protection that switches off all the output transistors when the junction temperature exceeds 150°C. The pres-ence of a hysteresis circuit makes the IC work again aftera fall of the junction temperature of about 20°C.The analog input pins (V ref1 , V ref2) can be left open or connected to V ss; in this case the circuit works with an internal reference voltage of about 2.5V and the peak current in the load is fixed only by the value of R s:I p=2.5RSFigure 1. Load current waveform with pin 9connected to GND.Figure 2. Load current waveform with externalR-C network connected between pin 9 and5/8SIGNAL WAVEFORMS (continued)Figure 3. With V ref changed by hardware.Figure 4. Switching frequency vs. values of Rand C.MULTIWATT15 PACKAGE MECHANICAL DATAInformation furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.© 1994 SGS-THOMSON Microelectronics - All Rights ReservedSGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore -Spain - Sweden - Switzerland - T aiwan - Thaliand - United Kingdom - U.S.A.。

LM5030100V Push-Pull Current Mode PWM ControllerGeneral DescriptionThe LM5030High Voltage PWM controller contains all of the features needed to implement Push-Pull and Bridge topolo-gies,using current-mode control in a small 10pin package.This device provides two alternating gate driver outputs.The LM5030includes a high-voltage start-up regulator that oper-ates over a wide input range of 14V to 100V.Additional features include:error amplifier,precision reference,dual mode current limit,slope compensation,softstart,sync ca-pability and thermal shutdown.This high speed IC has total propagation delays less than 100ns and a 1MHz capable single resistor adjustable oscillator.Package:MSOP-10(Contact factory for thermally enhanced LLP availability).Featuresn Internal High Voltage Start-up Regulator n Single Resistor Oscillator Setting n Synchronizable n Error Amplifiern Precision Reference n Adjustable Softstartn Dual Mode Over-Current Protection n Slope Compensationn Direct Optocoupler Interface n 1.5A Peak Gate Drivers nThermal ShutdownApplicationsn Telecommunication Power Converters n Industrial Power Converters n +42V Automotive SystemsConnection DiagramTop View2005811210-Lead MSOPOrdering InformationOrder Number Package MarkingNSC Package DrawingSupplies AsLM5030MM S73B MUB10A 1000Units on Tape and Reel LM5030MMXS73BMUB10A3500Units on Tape and ReelAugust 2003LM5030100V Push-Pull Current Mode PWM Controller©2003National Semiconductor Corporation Block Diagram20058101FIGURE 1.L M 5030 2Pin DescriptionPin Name PinNumberDescription Application Information V IN1Source Input Voltage Input to start-up regulator.Input range14to100Volts.V FB2Inverting input to the error amplifier The non-inverting input is internally connected to a1.25Voltreference.COMP3Output to the error amplifier There is an internal5K resistor pull-up on this pin.The erroramplifier provides an active sink.Vcc4Output from the internal highvoltage series pass regulator.Theregulation setpoint is7.7Volts.If an auxiliary winding raises the voltage on this pin above the regulation setpoint the internal series pass regulator will shutdown,reducing the IC power dissipation.OUT15Output of the PWM controller Alternating PWM output gate driver.OUT26Output of the PWM controller Alternating PWM output gate driver.GND7Return GroundCS8Current sense input Current sense input for current mode control and current limiting separate dedicated comparators,if CS exceeds0.5Volt the outputs will go into Cycle by Cycle current limit.If CSexceeds0.625V the outputs will be disabled and a softstartcommenced.RT9Oscillator timing resistor pin andsynchronization input.An external resistor sets the oscillator frequency.This pin will also accept synchronization pulses from an external oscillator.SS10Dual purpose Softstart andShutdown pin A10µA current source and an external capacitor set the softstart timing length.The controller will enter a low power state if the SSpin is pulled below the typical shutdown threshold of0.45V.LM50303Absolute Maximum Ratings(Note 1)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.V IN to GND (Survival)-0.3V to 100V V CC to GND (Survival)-0.3V to 16V RT to GND (Survival)-0.3V to 5.5V All other pins to GND (Survival)-0.3V to 7V Power Dissipation (Note 2)Internally LimitedESD Rating (Note 3)Human Body Model Machine Model2kV 200VLead Temperature(Soldering 4seconds)260˚CStorage Temperature Range -55˚C to +150˚CJunction Temperature150˚COperating RatingsJunction Temperature -40˚C to +105˚CV IN14V to 90VElectrical CharacteristicsSpecifications in standard type face are for T J =+25˚C and those in boldface type apply over the full operating junction tem-perature range.Unless otherwise specified:V IN =48V,V CC =10V,and RT =26.7K ΩSymbol ParameterConditionsMin (Note 4)Typ (Note 5)Max (Note 4)UnitsStartup Regulator V CC Reg V CC Regulation open ckt 7.47.78.0V V CC Current Limit(Note 2)1017mA I-V IN Startup Regulator Leakage (external Vcc Supply)V IN =90V150500µA I INShutdown CurrentSS =0V,V CC =open250350µAV CC SupplyV CC undervoltage Lockout VoltageVccReg -300mV VccReg -100mV V Undervoltage Hysteresis1.21.62.1V I CC Supply Current Cload =023mAError AmplifierGBWGain Bandwidth 4MHz DC Gain 75dB Input VoltageV FB =COMP1.220 1.245 1.270V COMP Sink CapabilityV FB =1.5V COMP=1V513mACurrent Limit CS1Cycle by Cycle CS Threshold Voltage0.450.50.55V CS2Restart CS Threshold Voltage Resets SS capacitor;auto restart0.5750.6250.675V ILIM Delay to OutputCS step from 0to 0.6V Time to onset of OUT Transition (90%)Cload =030nsCS Sink Current (clocked)CS =0.3V36mA Soft Start/ShutdownSoftstart Current Source 71013µA Softstart to COMP Offset 0.250.50.75V Shutdown Threshold0.20.450.7VL M 5030 4Electrical Characteristics(Continued)Specifications in standard type face are for T J=+25˚C and those in boldface type apply over the full operating junction tem-perature range.Unless otherwise specified:V IN=48V,V CC=10V,and RT=26.7KΩSymbol Parameter Conditions Min(Note4)Typ(Note5)Max(Note4)UnitsOscillatorFrequency1(RT=26.7K)175200225kHzFrequency2(RT=8.2K)510600690kHzSync threshold 3.2 3.8VPWM ComparatorDelay to Output COMP set to2V CSstepped0to0.4V,Timeto onset of OUT transitionlow30nsMax Duty Cycle Inferred from deadtime47.54950%Min Duty Cycle COMP=0V0%COMP to PWM ComparatorGain0.34COMP Open Circuit Voltage V FB=0V 4.3 5.2 6.1VCOMP Short Circuit Current V FB=0V,COMP=0V0.6 1.1 1.5mASlope CompensationSlope Comp Amplitude Delta increase at PWMComparator to CS80105130mVOutput SectionDeadtime Cload=0,10%to10%85135185nsOutput High Saturation Iout=50mA,V CC-V OUT0.250.75VOutput Low Saturation I OUT=100mA0.250.75VRise Time Cload=1nF16nsFall Time Cload=1nF16nsThermal ShutdownTsd Thermal Shutdown Temp.165˚C Thermal Shutdown Hysteresis15˚C Note1:Absolute Maximum Ratings are limits beyond which damage to the device may occur.Operating Ratings are conditions under which operation of the device is intended to be functional.For guaranteed specifications and test conditions,see the Electrical Characteristics.Note2:The maximum allowable power dissipation is a function of the maximum junction temperature,T J(MAX),the junction-to-ambient thermal resistance,θJA,and the ambient temperature,T A.The maximum allowable power dissipation at any ambient temperture is calculated using:Where the value ofθJA for the mini SO-10(MM)package is200˚C/W.Exceeding the maximum allowable dissipation will cause excessive die temperature,and the device will go into thermal shutdown.Note3:The human body model is a100pF capacitor discharged through a1.5kΩresistor into each pin.The machine model is a200pF capacitor discharged directly into each pin.The machine model ESD rating for pin5and pin6is150V.Note4:Limits are100%production tested at25˚C.Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC)methods.The limits are used to calculate National’s Average Outgoing Quality Level(AOQL).Note5:Typical numbers represent the most likely parametric norm for25˚C operation.LM50305Typical Performance CharacteristicsUnless otherwise specified:T J =25˚C.V CC vs V INV CC vs I CC (V IN =48V)2005810520058107Oscillator Frequency vs RTOscillator Frequency vs TemperatureRT =26.7k Ω2005810820058109Soft Start Current vs Temperature Deadtime vs Temperature2005811020058111L M 5030 6Typical Performance Characteristics Unless otherwise specified:TJ=25˚C.(Continued) Feedback Amplifier Gainphase20058115Detailed Operating DescriptionThe LM5030High Voltage PWM controller contains all of the features needed to implement Push-Pull and Bridge topolo-gies,using current-mode control in a small10pin package. Features included are,startup regulator,dual mode current limit,dual alternating gate drivers,thermal shutdown,soft-start and slope compensation.This high speed IC has total propagation delays<100nS.The Functional Block Diagram of the LM5030is shown in Figure1.The LM5030is designed for Current-Mode Control convert-ers which require alternating outputs,such as Push-Pull and Half/Full Bridge topologies.The features included in the LM5030enable all of the advantages of Current-Mode Con-trol,line feed-forward,cycle by cycle current limit and sim-plified loop compensation.The oscillator ramp is internally buffered and added to the PWM comparator input to provide slope compensation necessary for current mode control at higher duty cycles.High Voltage Start-Up RegulatorThe LM5030contains an internal high voltage startup regu-lator.The input pin(Vin)can be connected directly to line voltages as high as100V.The regulator output is internally current limited to10mA.Upon power up,the regulator is enabled and sources current into an external capacitor con-nected to the V CC pin.The recommended capacitance range for the V CC regulator is0.1µF to50µF.When the voltage on the V CC pin reaches the regulation point of7.7V,the control-ler outputs are enabled.The outputs will remain enabled unless,V CC falls below6.1V or if the SS/SHUTDOWN pin is pulled to ground or an over temperature condition occurs.In typical applications,an auxiliary transformer winding is diode connected to the V CC pin.This winding raises the V CC voltage greater than8V,effectively shutting off the internal startup regulator and saving power while reducing the con-troller dissipation.The external V CC capacitor must be sized such that the self-bias will maintain a V CC voltage greater than6.1V during the initial start-up.During a fault mode when the converter self bias winding is inactive,external current draw on the V CC line should be limited as to not exceed the maximum power dissipation of the controller.An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the V CC and the Vin pins and feeding the external bias voltage(8-15V)to that node.Error AmplifierAn internal high gain error amplifier is provided within theLM5030.The amplifier’s non-inverting reference is tied to1.25V.In non-isolated applications the power converter out-put is connected to the VFB pin via the voltage settingresistors and loop compensation is connected between theCOMP and VFB pins.For most isolated applications the error amplifier function isimplemented on the secondary side ground.Since the inter-nal error amplifier is configured as an open drain output itcan be disabled by connecting VFB to ground.The internal5K pull-up resistor,connected between the5V reference andCOMP,can be used as the pull-up for an optocoupler orother isolation device.PWM ComparatorThe PWM comparator compares the compensated currentramp signal to the loop error voltage from the internal erroramplifier(COMP pin).This comparator is optimized forspeed in order to achieve minimum discernable duty cycles.The comparator polarity is such that zero Volts on the COMPpin will cause a zero duty cycle.Current Limit/Current SenseThe LM5030contains two levels of over-current protection.Ifthe voltage on the current sense comparator exceeds0.5Volts the present cycle is terminated(cycle by cycle currentlimit).If the voltage on the current sense comparator ex-ceeds0.625Volts,the controller will terminate the presentcycle and discharge the softstart capacitor.A small RC filter,located near the controller,is recommended for the CS pin.An internal MOSFET discharges the current sense filtercapacitor at the conclusion of every cycle,to improve dy-namic performance.The LM5030CS and PWM comparators are very fast,andas such will respond to short duration noise youtconsiderations are critical for the current sense filter andsense resistor.The capacitor associated with the CS filtermust be placed very close to the device and connecteddirectly to the pins of the IC(CS and RTN).Also if a currentsense transformer is used,both leads of the transformersecondary should be routed to the sense resistor,whichshould also be located close to the IC.If a current senseresistor located in the drive transistor sources is used,forcurrent sense,a low inductance resistor should be chosen.LM50307Current Limit/Current Sense(Continued)In this case all of the noise sensitive low power grounds should be commoned together around the IC and then a single connection should be made to the power ground (sense resistor ground point).The second level threshold is intended to protect the power converter by initiating a low duty cycle hiccup mode when abnormally high,fast rising currents occur.During excessive loading,the first level threshold will always be reached and the output characteristic of the converter will be that of a current source but this sustained current level can cause excessive temperatures in the power train especially the output rectifiers.If the second level threshold is reached,the softstart capacitor will be fully discharged,a retry will com-mence following the discharge detection.The second level threshold will only be reached when a high dV/dt is present at the current sense pin.The signal must be fast enough to reach the second level threshold before the first threshold detector turns off the driver.This can usually happen for a saturated power inductor or shorted load.Excessive filtering on the CS pin,extremely low value current sense resistor or an inductor that does not saturate with excessive loading may prevent the second level threshold from ever being reached.Oscillator,Shutdown and Sync CapabilityThe LM5030oscillator is set by a single external resistor connected between the RT pin and return.To set a desired oscillator frequency the necessary RT resistor can be calcu-lated as:Each output switches at half the oscillator frequency in a Push-Pull configuration.The LM5030can also be synchro-nized to an external clock.The external clock must be of higher frequency than the free running frequency set by the RT resistor.The clock signal should be capacitively coupled into the RT pin with a 100pF capacitor.A peak voltage level greater than 3Volts with respect to ground is required for detection of the sync pulse.The sync pulse width should be set in the 15to 150nS range by the external components.The RT resistor is always required,whether the oscillator is free running or externally synchronized.The voltage at the RT pin is internally regulated to a nominal 2Volts.The RT resistor should be located very close to the device and connected directly to the pins of the IC (RT and GND).Slope CompensationThe PWM comparator compares the current sense signal to the voltage derived from the COMP pin.The COMP voltage is set by either the internal error amplifier or an external error amplifier through an optocoupler.At duty cycles greater than 50%(composite of alternating outputs)current mode control circuits are prone to subharmonic oscillation.By adding an additional ramp signal to the current sense ramp signal this condition can be avoided.The LM5030integrates this slope compensation by buffering the internal oscillator ramp and summing it internally to the current sense (CS)signal.Addi-tional slope compensation may be added by increasing the source impedance of the current sense signal.Soft Start/ShutdownThe softstart feature allows the converter to gradually reach the initial steady state operating point,thus reducing start-up stresses and surges.An internal 10uA current source and an external capacitor generate a ramping voltage signal which limits the error amplifier output during start-up.In the event of a second level current limit fault,the softstart capacitor will be fully discharged which disables the output drivers.When the fault condition is no longer present,the softstart capaci-tor is released to ramp and gradually restart the converter.The SS pin can also be used to disable the controller.If the SS pin voltage is pulled down below 0.45V (nominal)the controller will disable the outputs and enter a low power state.OUT1,OUT2and Time DelayThe LM5030provides two alternating outputs,OUT1and OUT2.The internal gate drivers can each sink 1.5A peak each.The maximum duty cycle for each output is inherently limited to less than 50%.The typical deadtime between the falling edge of one gate driver output and the rising edge of the other gate driver output is 135ns.Thermal ProtectionInternal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the excessive junction tem-perature.When activated,typically at 165degrees Celsius,the controller is forced into a low power reset state,disabling the output drivers and the bias regulator.This feature is provided to prevent catastrophic failures from accidental device overheating.L M 5030 8T y p i c a l A p p l i c a t i o n C i r c u i tT y p i c a l A p p l i c a t i o n C i r c u i t ,36V -75V I N a n d 3.3V ,10A O U T20058103LM50309ITEM PART NUMBERDESCRIPTIONVALUE C 1C0805C472K5RAC Capacitor,CER,KEMET 4700p,50V C 2C0805C103K5RAC Capacitor,CER,KEMET 0.01µ,50V C 3C4532X7S0G686M Capacitor,CER,TDK 68µ,4V C 4T520D337M006AS4350Capacitor,TANT,KEMET 330µ,6.3V C 5T520D337M006AS4350Capacitor,TANT,KEMET 330µ,6.3V C 6C4532X7R3A103K Capacitor,CER,TDK 0.01µ,1000V C 7C3216X7R2A104K Capacitor,CER,TDK 0.1µ,100V C 8C4532X7R2A105M Capacitor,CER,TDK 1µ,100V C 9C4532X7R2A105M Capacitor,CER,TDK 1µ,100V C 10C0805C102K1RAC Capacitor,CER,KEMET 1000p,100V C 11C1206C223K5RAC Capacitor,CER,KEMET 0.022µ,50V C 12C3216X7R1E105M Capacitor,CER,TDK 1µ,25V C 13C3216COG2J221J Capacitor,CER,TDK 220p,630V C 14C3216COG2J221J Capacitor,CER,TDK 220p,630V C 15C1206C104K5RAC Capacitor,CER,KEMET 0.1µ,50V C 16C0805C101J1GAC Capacitor,CER,KEMET 100p,100V C 17C0805C101J1GAC Capacitor,CER,KEMET 100p,100V C 18C3216X7R1H334K Capacitor,CER,TDK 0.33µ,50µD 1MBRB3030CTL Diode,Schottky,ON D 2CMPD2838-NSA Diode,Signal,Central D 3CMPD2838-NSA Diode,Signal,Central D 4CMPD2838-NSA Diode,Signal,Central D 5CMPD2838-NSA Diode,Signal,Central L 1MSS6132-103Input Choke,Coilcraft 10µH,1.5A L 2A9785-BOutput Choke,Coilcraft 7µH R 1CRCW12061R00F Resistor 1R 2CRCW12064990F Resistor 499R 3CRCW2512101J Resistor 100,1W R 4CRCW2512101J Resistor 100,1W R 5CRCW12064022F Resistor 40.2K R 6CRCW120610R0F Resistor 10R 7CRCW120610R0F Resistor 10R 8CRCW12061002F Resistor 10K R 9CRCW120623R7F Resistor 23.7R 10CRCW12062002F Resistor 20K R 11CRCW120610R0F Resistor 10R 12CRCW12063010F Resistor 301R 13CRCW120610R0F Resistor 10R 14CRCW12061001F Resistor1KTX 1A9784-B POWER XFR,COILCRAFT TX 2P8208T CURRENT XFR,Pulse 100:1U11LM5030REGULATOR,NATIONAL U22MOCD207M OPTO-COUPLER,QT OPTOELECTRONICS U33LM3411AM5-3.3REFERENCE,NATIONAL 651-1727010DUAL TERMINALS,MOUSER 3per ASSY X 1SUD19N20-90FET,N,200V,SILICONIX X2SUD19N20-90FET,N,200V,SILICONIXL M 5030 10Physical Dimensionsinches (millimeters)unless otherwise noted10Lead MSOP Package NS Package Number MUB10ALIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body,or (b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.National Semiconductor Americas Customer Support CenterEmail:new.feedback@ Tel:1-800-272-9959National SemiconductorEurope Customer Support CenterFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)6995086208English Tel:+44(0)8702402171Français Tel:+33(0)141918790National Semiconductor Asia Pacific Customer Support CenterEmail:ap.support@National SemiconductorJapan Customer Support Center Fax:81-3-5639-7507Email:jpn.feedback@ Tel:81-3-5639-7560LM5030100V Push-Pull Current Mode PWM ControllerNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.元器件交易网。

ispXPGA FamilyMarch 2003Preliminary Data SheetTM© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at /legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speci fications and information herein are subject to change without notice.■Non-volatile, In finitely Recon figurable•Instant-on - Powers up in microseconds via on-chip E 2CMOS ® based memory •No external con figuration memory•Excellent design security , no bit stream to intercept •Recon figure SRAM based logic in milliseconds■High Logic Density for System-levelIntegration•139K to 1.25M system gates •160 to 496 I/O•1.8V , 2.5V , and 3.3V V CC operation•Up to 414Kb sysMEM™ embedded memory■High Performance Programmable FunctionUnit (PFU)•Four LUT -4 per PFU supports wide and narrow functions•Dual flip-flops per LUT -4 for extensive pipelining •Dedicated logic for adders, multipliers, multiplex-ers, and counters■Variable-Length Interconnect RoutingTechnology•Optimum speed, power, and flexibility for logic interconnections■ Flexible Memory Resources•Multiple sysMEM Embedded RAM Blocks–Single port, Dual port, and FIFO operation •64-bit distributed memory in each PFU–Single port, Double port, FIFO, and Shift Register operation■ Eight sysCLOCK™ Phase Locked Loops(PLLs) for Clock Management•T rue PLL technology•10MHz to 320MHz operation •Clock multiplication and division •Phase adjustment•Shift clocks in 250ps steps■ sysIO™ for High System Performance•High speed memory support through SSTL and HSTL•Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL•Standard logic supported through LVTTL, LVCMOS 3.3, 2.5, and 1.8•Programmable drive strength for series termination •Programmable bus maintenance■ sysHSI™ Capability for Ultra Fast SerialCommunications•Up to 850Mbps performance •Up to 20 channels per device•Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES)■ Flexible Programming, Recon figuration,and Testing•IEEE 1532 and 1149.1 compliant•Microprocessor con figuration interface•Program E 2 CMOS while operating from SRAMTable 1. ispXPGA Family Selection GuideispXPGA 125ispXPGA 200ispXPGA 500ispXPGA 1200System Gates 139K 210K 476K 1.25M PFUs 48467617643844LUT -4s 19362704705615376Logic FFs 3.8K 5.4K 14.1K 30.7K sysMEM Memory 92K 111K 184K 414K Distributed Memory 30K 43K 112K 246K EBR20244090sysHSI Channels 481220User I/O 160/176160/208336496Packaging256 fpBGA 516 fpBGA 1256 fpBGA 516 fpBGA 1516 fpBGA 1 900 fpBGA680 fpSBGA 1 900 fpBGA1.Thermally enhanced package.Note: LFX1200B/C is preliminary, LFX125/200/500B/C information is advanced.Lattice Semiconductor ispXPGA Family Data SheetispXPGA Family OverviewThe ispXPGA family of devices allows the creation of high-performance logic designs that are both non-volatile andinfinitely re-programmable. Other FPGA solutions force a compromise being either re-programmable or non-vola-tile. This family couples this capability with a mainstream architecture containing the features required for today’ssystem-level design.Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA family with non-volatile capability.These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-tions. This capability also means that expensive external configuration memories are not required and that designs can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if desired. Both the SRAM and E2CMOS cells can be programmed and verified through the IEEE 1532 industry stan-dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG™ peripheral port.The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M systemgates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, provid-ing easy integration into the overall system.The system-level needs of designers are met through the incorporation of sysMEM dual-port memory blocks,sysIO advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications aresupported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serializa-tion (SERDES).The ispLEVER™ design tool from Lattice allows designers easy implementation of designs using the ispXPGAproduct. Synthesis library support is available for the major logic synthesis tools. The ispLEVER tool takes the out-put from these common synthesis packages and place and routes the design in the ispXPGA product. The toolallows floor planning and the management of other constraints within the device. The tool also provides outputs tocommon timing analysis tools for timing analysis.T o increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for theispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while usingpre-designed block to implement standard functions such as bus-interfaces, standard communication-interfaces,and memory-controllers.Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.Certain designs can run at over 300MHz. T able 2 details the performance of several building blocks commonlyused by logic designers.Table 2. ispXPGA Speed Performance for Typical Building BlocksFunction Performance8:1 Asynch MUX150 MHz1:32 Asynch Demultiplexer125 MHz8 x 8 2-LL Piped Multiplier225 MHz32-bit Up/Down Counter290 MHz32-bit Shift Register360 MHzLattice Semiconductor ispXPGA Family Data SheetArchitecture OverviewThe ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIOblocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and thesysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-ily implement their designs, since any logic function can be placed in any section of the device.The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They areoptimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently.The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registeredquickly to minimize setup times for high-speed designs. They also allow connections directly to the different logicelements for fast access to combinatorial functions.The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other stor-age types. They are designed to facilitate both single and dual-port memory for high-speed applications.These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additionalrouting available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers canbe configured to interface with 16 different I/O standards. This allows ispXPGA to interface with other devices with-out the need for external transceivers.The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to850Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery(CDR) logic.The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increasedperformance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block foreach global clock tree in the device.Lattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice SemiconductorispXPGA Family Data SheetTable 5. ispXPGA Supported I/O StandardsTable 6. Differential Interface Standard Support 1sysIO StandardV CCO V REF V TT LVTTL 3.3V N/A N/A LVCMOS-3.3 3.3V N/A N/A LVCMOS-2.5 2.5V N/A N/A LVCMOS-1.8 1.8V N/A N/A PCI 3.3V N/A N/A AGP-1X3.3V N/A N/A SSTL3, Class I, II 3.3V 1.5V 1.5V SSTL2, Class I, II 2.5V 1.25V 1.25V HSTL, Class I 1.5V 0.75V 0.75V HSTL, Class III 1.5V 0.9V 1.5V GTL+N/A 1.0V 1.5V LVPECL 3.3V N/A N/A LVDS 1 2.5V N/A N/A BLVDS2.5VN/AN/A1.V CCO must be2.5V for high speed serial operations (sysHSI block).sysIO Buffer Not Using sysHSI BlocksysIO Buffer Using sysHSI Block LVDS Driver Supported with external resistor network SupportedReceiver Supported with standard termination Supported with standard termination BLVDS Driver Supported with external resistor network Not supportedReceiver Supported (may need termination)Supported (may need termination)LVPECLDriver Supported with external resistor network Not supportedReceiverSupported with terminationSupported with termination1.For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines,available at .Lattice Semiconductor ispXPGA Family Data SheetTable 7. sysHSI Block REFCLK Selections1sysHSI Block Available Global Clock Nets0CLK0, CLK1, CLK2, CLK31CLK0, CLK1, CLK2, CLK42CLK0, CLK1, CLK2, CLK53CLK0, CLK1, CLK3, CLK64CLK0, CLK1, CLK3, CLK75CLK0, CLK3, CLK5, CLK76CLK0, CLK2, CLK5, CLK77CLK0, CLK1, CLK5, CLK68CLK0, CLK5, CLK69CLK0, CLK5, CLK6, CLK71.T able 6 applies to all devices. Ignore sysHSI blocks not availablein a specific device.Configuration and ProgrammingThe ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of memory, Static RAM and non-volatile E2CMOS cells. The static RAM is used to control the functionality of the device during normal operation and the E2CMOS memory cells are used to load the SRAM. The E2CMOS memory module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as the working configura-tion memory. There is a one-to-one relationship between SRAM memory and the E2CMOS cells. The SRAM can be configured either from the E2CMOS memory or from an external source, as shown in Figure 21.Figure 21 shows the different ports and modes that are used in the configuration and programming of the ispXPGA devices. There are two possible ports that can be used for configuration of the SRAM memory: the ISP port which is compliant to the IEEE 1149.1 T est Access Port (T AP) Std. and the ISP port which accommodates bit-wide config-uration. The sysCONFIG port allows byte-wide configuration of the SRAM configuration memory. When program-ming the E2CMOS memory, only the 1149.1 T AP can be used.Configuration and programming done through the 1149.1 T est Access Port (T AP) are fully compliant to both the IEEE Std. 1149.1 Boundary Scan T AP specification and the IEEE Std. 1532 In-System Configuration specification. T o configure or program the device using the 1149.1 T AP the device must be in the ISP mode. T o configure the SRAM memory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the device’s SRAM memory can be configured either from the E2CMOS memory or from an external source through the sysCONFIG mode. Additionally, the SRAM can be re-configured from the E2CMOS memory by executing a “REFRESH.” See Lattice technical note number TN1026, is pXP Configuration Us age Guide, for more in depth information on the different programming modes, timing and wake-up, available at .Absolute Maximum Ratings 1, 2, 31.8V2.5V/3.3VSupply Voltage (V CC ). . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V PLL Supply Voltage (V CCP ) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V Output Supply Voltage (V CCO ). . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V IEEE 1149.1 T AP Supply Voltage (V CCJ ). . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Input Voltage Applied 4 . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Storage T emperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C. . . . . . . . . -65 to 150°C Junction T emperature (T J ) with Power Applied . .-55 to 150°C. . . . . . . . . -55 to 150°C1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci fication is not implied (while programming, following the programming speci fications).2. Compliance with the Lattice Thermal Management technical note is required.3. All voltages referenced to GND.4. Overshoot and undershoot of -2V to (V IH (MAX) + 2) volts is permitted for a duration of <20nsRecommended Operating ConditionsE 2CMOS Erase Reprogram Speci ficationsHot Socketing Characteristics 1, 2, 3, 4SymbolParameterMin Max Units V CCSupply Voltage for 1.8V device1.65 1.95V Supply Voltage for2.5V device 2.3 2.7V Supply Voltage for3.3V device3.0 3.6V V CCPSupply Voltage for PLL block for 1.8V device1.65 1.95V Supply Voltage for PLL block for2.5V device 2.3 2.7V Supply Voltage for PLL block for3.3V device3.0 3.6V V CCJ Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS 1.8V1.65 1.95V Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS2.5V 2.3 2.7V Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS3.3V 3.0 3.6V T J (COM)Junction T emperature Commercial Operation 085C T J (IND)Junction T emperature Industrial Operation-40105CParameterMin Max Units Erase/Reprogram Cycle 11,000—Cycles1.Valid over commercial temperature range.Symbol ParameterConditionMin Typ Max Units I DKInput or I/O Leakage Current0 ≤ V IN ≤ 3.0V—+/-50+/-800µA1. Insensitive to sequence of V CC and V CCO . However, assumes monotonic rise / fall rates for V CC and V CCO .2. LVTTL, LVCMOS only3. 0 < V CC ≤ V CC (MAX), 0 < V CCO ≤ V CCO (MAX)4.I DK is additive to I PU , I PD or I BH . Device defaults to pull-up until fuse circuitry is active.DC Electrical CharacteristicsOver Recommended Operating ConditionsSupply CurrentOver Recommended Operating ConditionsSymbol ParameterConditionMin Typ Max Units I IL , I IH 1Input or I/O Low Leakage 0 ≤ V IN < (V CCO - 0.2V)——10µA (V CCO - 0.2V) ≤ V IN ≤ 3.6V ——40µA I PU I/O Active Pull-up Current 0 ≤ V IN ≤ 0.7 V CCO30—150µA I PD I/O Active Pull-down CurrentV IL (MAX) ≤ V IN ≤ V IH (MAX)30—150µA I BHLS Bus Hold Low Sustaining Current V IN = V IL (MAX)30——µA I BHHS Bus Hold High Sustaining Current V IN = 0.7 V CCO 30——µA I BHLO Bus Hold Low Overdrive Current 0 ≤ V IN ≤ V IH (MAX)——150µA I BHHO Bus Hold High Overdrive Current 0 ≤ V IN ≤ V IH (MAX)——150µA V BHT Bus Hold T rip Points V CCO * 0.35—V CCO * 0.65V C 1I/O Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—8—pf V CC = 1.8V , V IO = 0 to V IH (MAX) ——C 2Clock Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—6—pf V CC = 1.8V , V IO = 0 to V IH (MAX) ——C 3Global Input Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—6—pfV CC = 1.8V , V IO = 0 to V IH (MAX)——1.Input or I/O leakage current is measured with the pin con figured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled.2.T A = 25°C, f = 1.0MHz.Symbol ParameterCondition Min Typ Max Units I CC 1, 2Standby Core Operating Power Supply CurrentV CC = 3.3V —220—mA V CC = 2.5V —220—mA V CC = 1.8V —200—mA I CCO 3Standby Output Power Supply CurrentV CCO = 3.3V— 2.0—mA V CCO = 2.5V — 2.0—mA V CCO = 1.8V — 2.0—mA V CCO = 1.5V — 2.0—mA I CCP 4Standby PLL Operating Supply CurrentV CCP = 3.3V—17.0—mA V CCP = 2.5V —17.0—mA V CCP = 1.8V —15.0—mA I CCJ 5Standby IEEE 1149.1 T AP Power Supply CurrentV CCJ = 3.3V— 2.0—mA V CCJ = 2.5V — 1.5—mA V CCJ = 1.8V—1.0—mA1.T A = 25˚C, frequency = 1.0 MHz, device con figured with 16-bit counters.2.I CC varies with speci fic device con figuration and operating frequency. For more accurate power calculation use the ispXPGA Power Estimator.3.T A = 25˚C, per bank, no DC load, frequency = 0 MHz.4.T A = 25˚C, per PLL, frequency = 10 MHz.5.T A = 25˚CsysIO Differential Standards DC Electrical CharacteristicsParameter Description Test Conditions Min.Typ.Max. LVDS1V INP, V INM Input voltage 0V— 2.4V V THD Differential input threshold+/-100mV——V CM Input Common Mode voltage Half the sum of the two inputs 0.05V— 2.35V I IN Input current Power on or Power off ——+/-10uA V OH Output High Voltage for V OP or V OM RT = 100 Ohm— 1.38V 1.60V V OL Output Low Voltage for V OP or V OM RT = 100 Ohm0.9V 1.03V—V OD Output Voltage Differential|V OP - V OM|, R T = 100 ohm250mV350mV450mV ∆V OD Change in V OD between high and low——50mVV OS Output Voltage Offset|V OP + V OM|/2, R T = 100 ohm 1.125V 1.25V 1.375V ∆V OS Change in V OS between H and L——50mV——24mA I OSD Output short circuit current V OD = 0V Driver outputsshortedBLVDS1V INP, V INM Input voltage 0V— 2.4V V THD Differential input threshold+/-100mV——V CM Input Common Mode voltage Half the sum of the two inputs 0.05V— 2.35V I IN Input current Power on or Power off ——+/-10uA V OH Output High Voltage for V OP or V OM R T = 27Ω— 1.4V 1.80V V OL Output Low Voltage for V OP or V OM R T = 27Ω0.95V 1.1V—V OD Output Voltage Differential|V OP - V OM|, RT = 27Ω240mV300mV460mV ∆V OD Change in V OD Between H and L27mV V OS Output Voltage Offset|V OP + V OM| /2, RT = 27Ω 1.1V 1.3V 1.5V ∆V OS Change in V OS Between H and L27mVI OSD Output Short Circuit Current V OD = 0. Driver Outputs36mA65mAShorted.1.V OP and V OM are the two outputs of the LVDS/BLVDS output buffer.LVPECL1DCParameter Parameter Description Min.Max.Min.Max.Min.Max.Units V CCO 3.0 3.3 3.6V V IH Input Voltage High 1.49 2.72 1.49 2.72 1.49 2.72V V IL Input Voltage Low0.86 2.1250.86 2.1250.86 2.125V V OH Output Voltage High 1.8 2.11 1.92 2.28 2.13 2.41V V OL Output Voltage Low0.96 1.27 1.06 1.43 1.3 1.57V V DIFF Differential Input voltage0.3—0.3—0.3—V 1.These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 22). The V OH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.ispXPGA PFU Timing ParametersOver Recommended Operating ConditionsParameter Description-4-3Units Min.Max.Min.Max.Functional DelaysLUTst LUT44-Input LUT Delay—0.44—0.51ns t LUT55-Input LUT Delay—0.79—0.91ns t LUT66-Input LUT Delay—0.93— 1.07ns Shift Register (LUT)t LSR_S Shift Register Setup Time-0.62—-0.53—ns t LSR_H Shift Register Hold Time0.63—0.72—ns t LSR_CO Shift Register Clock to Output Delay—0.75—0.86ns Arithmetic Functionst LCTHRUR MC (Macro Cell) Carry In to MC Carry Out Delay (Rip-ple)—0.09—0.10ns t LCTHRUL1MC Carry In to MC Carry Out Delay (Look Ahead)—0.05—0.06ns t LSTHRU MC Sum In to MC Sum Out Delay—0.45—0.52ns t LSINCOUT MC Sum In to MC Carry Out Delay—0.31—0.36ns t LCINSOUTR MC Carry In to MC Sum Out Delay (Ripple)—0.39—0.45ns t LCINSOUTL MC Carry In to MC Sum Out Delay (Look Ahead)—0.28—0.32ns Feed-thrut LFT PFU Feed-Thru Delay—0.16—0.18ns Distributed RAMt LRAM_CO Clock to RAM Output— 1.33— 1.53ns t LRAMAD_S Address Setup Time-0.40—-0.34—ns t LRAMD_S Data Setup Time0.22—0.25—ns t LRAMWE_S Write Enable Setup Time0.46—0.53—ns t LRAMAD_H Address Hold Time0.60—0.69—ns t LRAMD_H Data Hold Time0.11—0.13—ns t LRAMWE_H Write Enable Hold Time0.12—0.14—ns t LRAMCPW Clock Pulse Width (High or Low) 3.00— 3.45—ns t LRAMADO Address to Output Delay—0.93— 1.07ns Register/Latch DelaysRegisterst L_CO Register Clock to Output Delay—0.62—0.71ns t L_S Register Setup Time (Data before Clock)0.14—0.16—ns t L_H Register Hold Time (Data after Clock)-0.12—-0.10—ns t LCE_S Register Clock Enable Setup Time-0.11—-0.09—ns t LCE_H Register Clock Enable Hold Time0.11—0.13—ns Latchest L_GO Latch Gate to Output Delay—0.10—0.12ns t LL_S Latch Setup Time0.14—0.16—ns t LL_H Latch Hold Time-0.12—-0.10—ns t LLPD Latch Propagation Delay (T ransparent Mode)—0.10—0.12nsispXPGA PIC Timing ParametersReset/Sett LASSRO Asynchronous Set/Reset to Output — 1.17— 1.35ns t LASSRPW Asynchronous Set/Reset Pulse Width — 4.50— 5.18ns t LASSRR Asynchronous Set/Reset Recovery —0.55—0.63ns t LSSR_S Synchronous Set/Reset Setup Time -0.03—-0.03—ns t LSSR_HSynchronous Set/Reset Hold Time0.03—0.03—ns1.t LCTHRUL quoted bit by bit.Timing v.2.0Parameter Description -4-3UnitsMin.Max.Min.Max.Register/Latch Delays t IO_CO Register Clock to Output Delay— 1.09— 1.25ns t IO_S Register Setup Time (Data before Clock)0.05—0.06—ns t IO_H Register Hold Time (Data after Clock)0.06—0.07—ns t IOCE_S Register Clock Enable Setup Time -0.03—-0.03—ns t IOCE_H Register Clock Enable Hold Time 0.13—0.15—ns t IO_GO Latch Gate to Output Delay —0.91— 1.05ns t IOL_S Latch Setup Time 0.05—0.06—ns t IOL_H Latch Hold Time0.06—0.07—ns t IOLPD Latch Propagation Delay (T ransparent Mode)—0.10—0.12ns t IOASRO Asynchronous Set/Reset to Output — 1.26— 1.45ns t IOASRPW Asynchronous Set/Reset Pulse Width — 4.50— 5.18ns t IOASRR Asynchronous Set/Reset Recovery Time —0.25—0.29ns Input/Output Delayst IOBUF Output Buffer Delay — 1.06— 1.22ns t IOIN Input Buffer Delay —0.76—0.87ns t IOEN Output Enable Delay —0.56—0.64ns t IODIS Output Disable Delay —-0.10—-0.09ns t IOFTFeed-thru Delay—0.20—0.23nsTiming v.2.0ispXPGA PFU Timing Parameters (Continued)Over Recommended Operating ConditionsParameterDescription-4-3Units Min.Max.Min.Max.ispXPGA EBR Timing ParametersParameter Description-4-3Units Min.Max.Min.Max.Synchronous Writet EBSWAD_S Address Setup Delay0.61—0.70—nst EBSWAD_H Address Hold Delay-0.39—-0.33—nst EBSWCPW Clock Pulse Width— 3.40— 3.91nst EBSWWE_S Write Enable Setup Time-0.12—-0.10—nst EBSWWE_H Write Enable Hold Time0.16—0.18—nst EBSWD_S Data Setup Time0.28—0.32—nst EBSWD_H Data Hold Time-0.26—-0.22—ns Synchronous Readt EBSR_CO Clock to Data Delay— 2.19— 2.52nst EBSRAD_S Address Setup Delay0.10—0.12—nst EBSRAD_H Address Hold Delay-0.07—-0.06—nst EBSRCPW Clock Pulse Width— 3.40— 3.91nst EBSRCE_S Clock Enable Setup Time-1.71—-1.45—nst EBSRCE_H Clock Enable Hold Time 1.69— 1.94—nst EBSRWE_S Write Enable Setup Time-0.17—-0.14—nst EBSRWE_H Write Enable Hold Time0.12—0.14—nst EBSRWEEN Write Enable to Data Enable Time— 1.05— 1.21nst EBSRWEDIS Write Enable to Data Disable Time— 1.02— 1.17nst EBSREN Output Enable to Data Enable Time— 1.05— 1.21nst EBSRDIS Output Enable to Data Disable Time—0.86—0.99ns Asynchronous Readt EBARADO Address to New Valid Data Delay— 2.46— 2.83nst EBARAD_H Address to Previous Valid Data Delay— 2.17— 2.50nst EBARWEEN Write Enable to Data Enable Time— 1.04— 1.20nst EBARWEDIS Write Enable to Data Disable Time— 1.01— 1.16nst EBAREN Output Enable to Data Enable Time— 1.05— 1.21nst EBARDIS Output Enable to Data Disable Time—0.86—0.99nsTiming v.2.0ispXPGA Family Timing AddersParameter DescriptionBaseParameter-4-3Units Min.Max.Min.Max.Optional Adderst INDIO Input Delay—— 6.0— 6.9ns t IOI Input AdjustersLVTTL_in Using 3.3V TTL t IOIN— 0.5—0.5ns LVCMOS_18_in Using 1.8V CMOS t IOIN— 0.0—0.0ns LVCMOS_25_in Using 2.5V CMOS t IOIN— 0.3—0.3ns LVCMOS_33_in Using 3.3V CMOS t IOIN— 0.5—0.5ns AGP_1X_in Using AGP 1x t IOIN— 1.0— 1.0ns CTT25_in Using CTT 2.5V t IOIN— 1.0— 1.0ns CTT33_in Using CTT 3.3V t IOIN— 1.0— 1.0ns GTL+_in Using GTL+t IOIN— 0.5—0.5ns HSTL_I_in Using HSTL 2.5V, Class I t IOIN—0.5—0.5ns HSTL_III_in Using HSTL 2.5V, Class III t IOIN—0.5—0.5ns LVDS_in Using Low VoltageDifferential Signaling (LVDS)t IOIN— 0.8—0.8nsBLVDS_in Using Bus Low VoltageDifferential Signaling (BLVDS)t IOIN—0.8—0.8ns LVPECL_in Using Low Voltage PECL t IOIN— 0.8—0.8ns PCI_in Using PCI t IOIN— 1.0— 1.0ns SSTL2_I_in Using SSTL 2.5V, Class I t IOIN— 0.8—0.8ns SSTL2_II_in Using SSTL 2.5V, Class II t IOIN— 0.5—0.5ns SSTL3_I_in Using SSTL 3.3V, Class I t IOIN— 0.8—0.8ns SSTL3_II_in Using SSTL 3.3V, Class II t IOIN— 0.8—0.8ns t IOO Output AdjustersSlow Slew Using Slow Slew (LVTTL andLVCMOS Outputs only)t IOBUF, t IOEN—0.7—0.7nsLVTTL_out Using 3.3V TTL Drive t IOBUF, t IOEN,t IODIS— 1.0 — 1.0 nsLVCMOS_18_4mA_out Using 1.8V CMOS Standard,4mA Drive t IOBUF, t IOEN,t IODIS—0.8—0.8nsLVCMOS_18_5.33mA_out Using 1.8V CMOS Standard,5.33mA Drive t IOBUF, t IOEN,t IODIS—0.6—0.6nsLVCMOS_18_8mA_out Using 1.8V CMOS Standard,8mA Drive t IOBUF, t IOEN,t IODIS—0.0—0.0nsLVCMOS_18_12mA_out Using 1.8V CMOS Standard,12mA Drive t IOBUF, t IOEN,t IODIS—0.2—0.2nsLVCMOS_25_4mA_out Using 2.5V CMOS Standard,4mA Drive t IOBUF, t IOEN,t IODIS—0.7—0.7nsLVCMOS_25_5.33mA_out Using 2.5V CMOS Standard,5.33 mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_8mA_out Using 2.5V CMOS Standard,8mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_12mA_out Using 2.5V CMOS Standard,12mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_16mA_out Using 2.5V CMOS Standard,16mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_33_4mA_outUsing 3.3V CMOS Standard, 4mA Drive t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive t IOBUF , t IOEN,t IODIS — 1.0— 1.0ns LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drivet IOBUF , t IOEN, t IODIS —0.7—0.7ns LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns LVCMOS_33_16mA_out Using 3.3V CMOS Standard, 16mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns LVCMOS_33_24mA_out Using 3.3V CMOS Standard, 24mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns AGP_1X_out Using AGP 1x Standard t IOBUF , t IOEN, t IODIS—0.5—0.5ns CTT25_out Using CTT 2.5V t IOBUF , t IOEN, t IODIS—0.5—0.5ns CTT33_out Using CTT 3.3V t IOBUF , t IOEN, t IODIS—0.5—0.5ns GTL+_out Using GTL+t IOBUF , t IOEN, t IODIS—0.5—0.5ns HSTL_I_out Using HSTL 2.5V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns HSTL_III_out Using HSTL 2.5V , Class III t IOBUF , t IOEN, t IODIS—0.5—0.5ns LVDS_out Using Low Voltage Differen-tial Signaling (LVDS)t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns BLVDS_out Using Bus Low Voltage Differ-ential Signaling (BLVDS)t IOBUF , t IOEN,t IODIS — 1.0— 1.0ns LVPECL_out Using Low Voltage PECL t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns PCI_out Using PCI Standard t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL2_I_out Using SSTL 2.5V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL2_II_out Using SSTL 2.5V , Class II t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL3_I_out Using SSTL 3.3V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL3_II_outUsing SSTL 3.3V , Class IIt IOBUF , t IOEN, t IODIS—0.5—0.5nsTiming v.2.0ispXPGA Family Timing Adders (Continued)ParameterDescriptionBase Parameter-4-3Units Min.Max.Min.Max.。