LY1058_Datasheet.PDF

Data SheetADG633Rev. B | Page 7 of 16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSS2A S3B D3V SS EN S3A S2B GND D2D1S1B A1A2A0S1A V DD 03275-002Figure 2. 16-Lead TSSOP Pin Configuration NOTES 1.THE EXPOSED PADDLE CAN BE LEFT FLOATING OR BE TIED TO V DD , V SS , OR GND.S3B D3S3A EN S1B D1S1A A0V S S G N D A 2A 1S 2B S 2A V D DD 203275-00312111013492657816151413ADG633TOP VIEW (Not to Scale)Figure 3. 16-Lead LFCSP Pin Configuration1 X means the logic state does not matter; it can be either 0 or 1.ADG633Data SheetRev. B | Page 14 of 16OUTLINE DIMENSIONSCOPLANARITY 0.10COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 31. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters4.104.00 SQ 3.900.350.300.25 2.252.10 SQ1.9510.65BSC BOTTOM VIEW TOP VIEW 16589121340.700.600.50SEATING PLANE0.05 MAX 0.02 NOM 0.203 REF 0.25 MINCOPLANARITY 0.08PIN 1INDICATOR 0.800.750.70COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.04-15-2016-A P K G -004025/5112PIN 1INDIC ATOR AREA OPTIONS (SEE DETAIL A)DETAIL A (JEDEC 95)EXPOSED PAD Figure 32. 16-Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-16-23) Dimensions shown in millimetersORDERING GUIDEModel 1Temperature Range Package Description Package Option ADG633YRU−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG633YRU-REEL7−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG633YRUZ−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG633YRUZ-REEL7−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG633YCPZ−40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23 ADG633YCPZ-REEL7−40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23 1 Z = RoHS Compliant Part.。

Ferrite Beads SMDSize: JIS/IEC 1608, EIA 0603TDK has manufactured MPZ2012 type as EMI countermeasure product for power line, and now maximizes impedance to 600Ω (at 100MHz) and rated current to 1A, while minimizes Rdc under 150m Ω as 1608 type.FEATURES•This type is the best for energy-saving in the low DC resistance.•The products contain no lead and also support lead-free soldering.•It is a product conforming to RoHS directive.APPLICATIONSNoise suppression of personal computers, USB/IEEE1394interfaces, HDDs, CD-ROMs, DVDs, DSCs, LCD panels, cellular phones, etc.PRODUCT IDENTIFICATION (1)Series name (2)Dimensions L ×W (3)Material code(4)Nominal impedance 221: 220Ω at 100MHz (5)Characteristic type (6)Packaging style T: TapingELECTRICAL CHARACTERISTICS∗Please refer to the graph of RATED CURRENT vs. TEMPERATURE CHARACTERISTICS(DERATING) about the rating current at 85°C or more in temperature of the product.SHAPES AND DIMENSIONS/RECOMMENDED PC BOARD PATTERNTEMPERATURE RANGESPACKAGING STYLE AND QUANTITIESRATED CURRENT vs. TEMEPERATURE CHARACTERISTICS (DERATING)RECOMMENDED SOLDERING CONDITION REFLOW SOLDERINGPart No.Impedance (Ω)[100MHz]DC resistance(Ω)max.Rated current ∗(A)max.Thickness (T)mm ΩMPZ1608S600A 60±25%0.02 3.50.6MPZ1608S101A 100±25%0.0330.6MPZ1608S601A 600±25%0.1510.8MPZ1608Y151B 150±25%0.07 1.80.8MPZ1608D300B 30±10Ω0.07 1.80.8MPZ1608D101B 100±25%0.15 1.00.8MPZ 1608 S 221A T (1) (2) (3) (4) (5) (6)Thickness(T)Weight Operating/storage–55 to +125°CTaping4000 pieces/reel•Please contact our Sales office when your application are considered the following:The device ’s failure or malfunction may directly endanger human life (e.g. application for automobile/aircraft/medical/nuclear power devices, etc.)•Conformity to RoHS Directive: This means that, in conformity with EU Directive 2002/95/EC, lead, cadmium, mercury, hexavalent chromium, and specific bromine-based flame retardants, PBB and PBDE, have not been used, except for exempted applications.Ferrite Beads SMDSize: JIS/IEC 1608, EIA 0603TYPICAL ELECTRICAL CHARACTERISTICS Z, X, R vs. FREQUENCY CHARACTERISTICS MPZ1608S300A MPZ1608S600AMPZ1608S101AMPZ1608S221AMPZ1608R391AMPZ1608S601AMPZ1608Y600BMPZ1608Y101BMPZ1608Y151BMPZ1608D300BMPZ1608D600BMPZ1608D101B。

Vbat（V） ＝ 4.2＋4.03×10-6×Rx（Ω）
当使用外部电阻调整恒压充电电压时，由于芯片内部和外部的温度不一致及芯片生产时的工艺偏差等 原因，可能导致输出电压的精度变差和温度系数变大。 ● 设定充电电流 在恒流模式，计算充电电流的公式为： ICH = 1250V / RISET 其中，ICH 表示充电电流，单位为安培，RISET 表示ISET管脚到地的电阻，单位为欧姆。 例如，如果需要500毫安的充电电流，可按下面的公式计算： RISET = 1250V/0.5A = 2.5kΩ 为了保证良好的稳定性和温度特性，RISET建议使用精度为1%的金属膜电阻。 通过测量ISET管脚的电 压可以检测充电电流。充电电流可以用下面的公式计算：ICH = (VISET / RISET) × 1250 ● 同时应用 USB 和交流电适配器充电 LN2051不但可以利用USB接口为电池充电，也可以利用墙上适配器为电池充电。图4示出一个同 时使用USB接口和交流电适配器通过LN2051对电池进行充电的例子，当二者共同存在时，交流电适配 器具有优先权。M1为P沟道MOSFET，M1用来阻止电流从墙上适配器流入USB接口，肖特基二极管 D1可防止USB接口通过1K电阻消耗能量。
■ 应用场合
移动电话 数码相机 MP4 播放器 蓝牙应用、 电子词典 便携式设备 各种充电器
-1-
■ 封装形式
SOP-8 MSOP8
上海南麟电子有限公司

1A 具有 USB 接口兼容的线性电池管理芯片 LN2051 系列
图4
同时使用交流电适配器和USB接口
上海南麟电子有限公司
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1A 具有 USB 接口兼容的线性电池管理芯片 LN2051 系列

LM12L458LM12L458 12-Bit + Sign Data Acquisition System with Self-CalibrationLiterature Number: SNAS085ALM12L45812-Bit +Sign Data Acquisition System with Self-CalibrationGeneral DescriptionThe LM12L458is a highly integrated 3.3V Data Acquisition System.It combines a fully-differential self-calibrating (cor-recting linearity and zero errors)13-bit (12-bit +sign)analog-to-digital converter (ADC)and sample-and-hold (S/H)with extensive analog functions and digital functionality.Up to 32consecutive conversions,using two’s complement format,can be stored in an internal 32-word (16-bit wide)FIFO data buffer.An internal 8-word RAM can store the conversion sequence for up to eight acquisitions through the LM12L458’s eight-input multiplexer.The LM12L458can also operate with 8-bit +sign resolution and in a supervisory “watchdog”mode that compares an input signal against two programmable limits.Programmable acquisition times and conversion rates are possible through the use of internal clock-driven timers.All registers,RAM,and FIFO are directly addressable through the high speed microprocessor interface to either an 8-bit or 16-bit data bus.The LM12L458includes a direct memory access (DMA)interface for high-speed conversion data transfer.Additional applications information can be found in applica-tions notes AN-906,AN-947and AN-949.Key Specifications(f CLK =6MHz)n Resolution 12-bit +sign or 8-bit +sign n Single supply +3V to +5.5V n 13-bit conversion time 7.3µs n 9-bit conversion time 3.5µs n 13-bit Through-put rate 106k samples/s (min)n Comparison time (“watchdog”mode) 1.8µs (max)n ILE±1LSB (max)n Power Consumption 15mW (max)n Stand-by mode 5µW (typ)Featuresn Three operating modes:12-bit +sign,8-bit +sign,and “watchdog”n Single-ended or differential inputs n Built-in Sample-and-Holdn Instruction RAM and event sequencer n 8-channel multiplexer n 32-word conversion FIFOn Programmable acquisition times and conversion rates n Self-calibration and diagnostic moden 8-or 16-bit wide data bus microprocessor or DSP interfacen CMOS compatible I/OApplicationsn Data Logging n Process Controln Energy Management nMedical InstrumentationTRI-STATE ®is a registered trademark of National Semiconductor Corporation.©2006National Semiconductor Corporation 01171101*Pin names in ()apply to the obsolete LM12L454,shown for reference only.Order Number LM12L458CIV See NS Package Number V44AFunctional DiagramLM12L45801171103Ordering InformationGuaranteed Guaranteed Order See NS Clock Freq Linearity Error (max)Part Number Package Number6MHz±1.0LSBLM12L458CIVV44A (PLCC)L 2If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V A+and V D+) 6.0V Voltage at Input and Output Pins,except analog inputs−0.3V to(V++0.3V) Voltage at Analog Inputs−5V to(V++5V) |(V A+)−(V D+)|300mV Input Current at Any Pin(Note3)±5mA Package Input Current(Note3)±20mA Power Consumption(T A=25˚C)(Note4)875mW Storage Temperature−65˚C to+150˚C Lead Temperature,Infrared,15sec.+300˚C ESD Susceptibility(Note5) 1.5kVSee AN-450“Surface Mounting Methods and Their Effect on Product Reliability”for other methods of soldering surface mount devices.Package Thermal ResistancesPackageθJA44-Lead PLCC50˚C/WTemperature Range−40˚C≤T A≤85˚C Supply Voltage-V A+,V D++3.0V to+5.5V |V A+−V D+|≤100mV V IN+Input Range GND≤V IN+≤V A+ V IN−Input Range GND≤V IN−≤V A+ V REF+Input Voltage1V≤V REF+≤V A+ V REF−Input Voltage0V≤V REF−≤V REF+−1V V REF+−V REF−1V≤V REF≤V A+ V REF Common ModeRange(Note16)0.1V A+≤V REFCM≤0.6V A+ T J(MAX)150˚CReliability Information-Transistor CountDevice Number P-Chan MOS Transistor12,232 N-Chan MOS Transistor15,457 Parasitic Vertical Bipolar Junction Transistor4 Parasitic Lateral Bipolar Junction Transistor2TOTAL Transistors27,695Converter CharacteristicsThe following specifications apply for V A+=V D+=+3.3V,V REF+=+2.5V,V REF−=0V,12-bit+sign conversion mode,f CLK= 6.0MHz,R S=25Ω,source impedance for V REF+and V REF−≤25Ω,fully-differential input with fixed1.25V common-mode volt-age,and minimum acquisition time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Notes6,7,8,9)Symbol Parameter ConditionsTypical(Note10)Limits(Note11)UnitsILE Integral Linearity Error After Auto-Cal(Notes12,17)±1/2±1LSB(max) TUE Total Unadjusted Error After Auto-Cal(Note12)±1LSB Resolution with No Missing Codes After Auto-Cal(Note12)13Bits(max) DNL Differential Non-Linearity After Auto-Cal±1LSB(max) Zero Error After Auto-Cal(Notes13,17)±1/4±1LSB(max)Positive Full-Scale Error After Auto-Cal(Notes12,17)±1/2±3LSB(max)Negative Full-Scale Error After Auto-Cal(Notes12,17)±1/2±3LSB(max)DC Common Mode Error(Note14)±2±4LSB(max)ILE 8-Bit+Sign and“Watchdog”ModeIntegral Linearity Error(Note12)±1/2LSB(max)TUE 8-Bit+Sign and“Watchdog”ModeTotal Unadjusted ErrorAfter Auto-Zero±1/2±3/4LSB(max) 8-Bit+Sign and“Watchdog”ModeResolution with No Missing Codes9Bits(max)DNL 8-Bit+Sign and“Watchdog”ModeDifferential Non-Linearity±1LSB(max)8-Bit+Sign and“Watchdog”ModeZero ErrorAfter Auto-Zero±1/2LSB(max)8-Bit+Sign and“Watchdog”Full-ScaleError±1/2LSB(max)36.0MHz,R S =25Ω,source impedance for V REF+and V REF−≤25Ω,fully-differential input with fixed 1.25V common-mod age,and minimum acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all o limits T A =T J =25˚C.(Notes 6,7,8,9)SymbolParameterConditionsTypical (Note 10)Limits (Note 11)U8-Bit +Sign and “Watchdog”Mode DC Common Mode Error±1/8Multiplexer Channel-to-Channel Matching±0.05V IN+Non-Inverting Input Range GND VV A +VV IN−Inverting Input RangeGND VV A +VV IN+−V IN−Differential Input Voltage Range −V A +VV A +VCommon Mode Input Voltage Range GND VV A +VPSS Power Supply Sensitivity (Note 15)Zero Error V A +=V D +=+3.3V ±10%±0.2±1.75LSFull-Scale Error V REF+=2.5V,V REF−=GND±0.4±2LSLinearity Error±0.2C REF V REF+/V REF−Input Capacitance 85C INSelected Multiplexer Channel Input Capacitance75Converter AC CharacteristicsThe following specifications apply for V A +=V D +=+3.3V,V REF+=+2.5V,V REF−=0V,12-bit +sign conversion mode,f 6.0MHz,R S =25Ω,source impedance for V REF+and V REF−≤25Ω,fully-differential input with fixed +1.25V common-m voltage,and minimum acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;a limits T A =T J =25˚C.(Notes 6,7,8,9)SymbolParameterConditionsTypical (Note 10)Limits (Note 11)Clock Duty Cycle5040%60%t CConversion Time13-Bit Resolution,Sequencer State S5(Figure 15)44(t CLK )44(t CLK )+50ns 9-Bit Resolution,Sequencer State S5(Figure 15)21(t CLK )21(t CLK )+50ns t AAcquisition TimeSequencer State S7(Figure 15)Built-in minimum for 13-Bits 9(t CLK )9(t CLK )+50ns Built-in minimum for 9-Bits and “Watchdog”mode2(t CLK )2(t CLK )+50ns t Z Auto-Zero Time Sequencer State S2(Figure 15)76(t CLK )76(t CLK )+50ns t CAL Full Calibration Time Sequencer State S2(Figure 15)4944(t CLK )4944(t CLK )+50nsThroughput Rate (Note 18)107106kt WD “Watchdog”Mode Comparison TimeSequencer States S6,S4,and S5(Figure 15)11(t CLK )11(t CLK )+50nst PU Power-Up Time 10t WUWake-Up Time10L 4tion time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Notes 6,7,8)Symbol Parameter ConditionsTypical(Note10)Limits(Note11)UnitsI D+V D+Supply Current CS=“1”0.4 1.0mA(max) I A+V A+Supply Current CS=“1” 2.25 3.5mA(max)I ST Stand-By Supply Current(I D++I A+)Power-DownMode SelectedClock Stopped 1.5 4.5µA(max)6MHz Clock30µA(max)Multiplexer ON-ChannelLeakage CurrentV A+=+3.6VON-Channel=3.6V0.10.3µA(max)OFF-Channel=0VON-Channel=0V0.10.3µA(max)OFF-Channel=3.6VMultiplexer OFF-ChannelLeakage CurrentV A+=+3.6VON-Channel=3.6V0.10.3µA(max)OFF-Channel=0VON-Channel=0VOFF-Channel=3.6V0.10.3µA(max)R ON Multiplexer ON-Resistance V IN=+3.3V8501500ΩV IN=+1.65V13002000ΩV IN=0V8301500ΩMultiplexer Channel-to-Channel R ON matching V IN=+3.3V±1.0%±3.0%ΩV IN=+1.65V±1.0%±3.0%ΩV IN=0V±1.0%±3.0%ΩDigital CharacteristicsThe following specifications apply for V A+=V D+=+3.3V,unless otherwise specified.Boldface limits apply for T A=T J= T MIN to T MAX;all other limits T A=T J=25˚C.(Notes6,7,8)Symbol Parameter ConditionsTypical(Note10)Limits(Note11)UnitsV IN(1)Logical“1”Input Voltage V A+=V D+=+3.6V 2.0V(min)V IN(0)Logical“0”Input Voltage V A+=V D+=+3.0V0.7V(max) ALE,Pin220.6I IN(1)Logical“1”Input Current V IN=+3.3V0.0051.0µA(max)2.0µA(max)I IN(0)Logical“0”Input Current V IN=0V−0.005−1.0µA(max)−2.0µA(max)C IN D0–D15Input Capacitance6pFV OUT(1)Logical“1”Output Voltage V A+=V D+=3.0VI OUT=−360µA 2.4V(min) I OUT=−10µA 2.85V(min)V OUT(0)Logical“0”Output Voltage V A+=V D+=+3.0VI OUT=1.6mA0.4V(max) I OUT=10µA0.1V(max)I OUT TRI-STATE®Output Leakage Current V OUT=0V−0.01−3.0µA(max)V OUT=+3.3V0.01 3.0µA(max) 5unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Notes6Symbol(See Figures10,11,12)Parameter ConditionsTypical(Note10)Limits(Note11)U1,3CS or Address Valid to ALE Low Set-UpTime40ns2,4CS or Address Valid to ALE Low HoldTime20ns5ALE Pulse Width45ns 6RD High to Next ALE High35ns 7ALE Low to RD Low20ns 8RD Pulse Width100ns 9RD High to Next RD or WR Low100ns 10ALE Low to WR Low20ns 11WR Pulse Width60ns 12WR High to Next ALE High75ns 13WR High to Next RD or WR Low140ns 14Data Valid to WR High Set-Up Time40ns 15Data Valid to WR High Hold Time30ns16RD Low to Data Bus Out of TRI-STATE3010ns 70ns17RD High to TRI-STATE R L=1kΩ3010ns 110ns18RD Low to Data Valid(Access Time)3010ns 95ns20Address Valid or CS Low to RD Low20ns 21Address Valid or CS Low to WR Low20ns 19Address Invalid from RD or WR High10ns22INT High from RD Low3010ns 60ns23DMARQ Low from RD Low3010ns 60nsElectrical CharacteristicsNote1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The gu specifications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the li conditions.Note2:All voltages are measured with respect to GND,unless otherwise specified.Note3:When the input voltage(V IN)at any pin exceeds the power supply rails(V IN<GND or V IN>(V A+or V D+)),the current at that pin should be limited The20mA maximum package input current rating allows the voltage at any four pins,with an input current of5mA,to simultaneously exceed the powe voltages.Note4:The maximum power dissipation must be derated at elevated temperatures and is dictated by T Jmax(maximum junction temperature),θJA(package to ambient thermal resistance),and T A(ambient temperature).The maximum allowable power dissipation at any temperature is PD max=(T Jmax−T A)/θnumber given in the Absolute Maximum Ratings,whichever is lower.Note5:Human body model,100pF discharged through a1.5kΩresistor.Note6:Two on-chip diodes are tied to each analog input through a series resistor,as shown below.Input voltage magnitude up to5V above V A+or5V bel will not damage the LM12L458.However,errors in the A/D conversion can occur if these diodes are forward biased by more than100mV.As an exampl is3.0V DC,full-scale input voltage must be≤3.1V DC to ensure accurate conversions.L601171104Note 7:V A +and V D +must be connected together to the same power supply voltage and bypassed with separate capacitors at each V +pin to assure conversion/comparison accuracy.Note 8:Accuracy is guaranteed when operating at f CLK =6MHz.Note 9:With the test condition for V REF =V REF+−V REF−given as +2.5V,the 12-bit LSB is 305µV and the 8-bit/“Watchdog”LSB is 4.88mV.Note 10:Typical figures are at T A =25˚C and represent most likely parametric norm.Note 11:Limits are guaranteed to National’s AOQL (Average Output Quality Level).Note 12:Positive integral linearity error is defined as the deviation of the analog value,expressed in LSBs,from the straight line that passes through positive full-scale and zero.For negative integral linearity error the straight line passes through negative full-scale and zero.(See Figures 7,8).Note 13:Zero error is a measure of the deviation from the mid-scale voltage (a code of zero),expressed in LSB.It is the worst-case value of the code transitions between −1to 0and 0to +1(see Figure 9).Note 14:The DC common-mode error is measured with both inputs shorted together and driven from 0V to +2.5V.The measured value is referred to the resulting output value when the inputs are driven with a 1.25V signal.Note 15:Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with V A +and V D +at the specified extremes.Note 16:V REFCM (Reference Voltage Common Mode Range)is defined as (V REF++V REF−)/2.Note 17:The LM12L458’s self-calibration technique ensures linearity and offset errors as specified,but noise inherent in the self-calibration process will result in a repeatability uncertainty of ±0.10LSB.Note 18:The Throughput Rate is for a single instruction repeated continuously.Sequencer states 0(1clock cycle),1(1clock cycle),7(9clock cycles)and 5(44clock cycles)are used (see Figure 15).One additional clock cycle is used to read the conversion result stored in the FIFO,for a total of 56clock cycles per conversion.The Throughput Rate is f CLK (MHz)/N,where N is the number of clock cycles/conversion.Test Circuits and Waveforms01171115011711160117111701171118FIGURE 1.TRI-STATE Test Circuits and Waveforms701171105V REF =V REF+−V REF−V IN =V IN+−V IN−GND ≤V IN+≤V A +GND ≤V IN−≤V A +FIGURE 2.The General Case of Output Digital Code vs.the Operating Input Voltage Range01171106V REF+−V REF−=2.5V V IN =V IN+−V IN−GND ≤V IN+≤V A +GND ≤V IN−≤V A +FIGURE 3.Specific Case of Output Digital Code vs.the Operating Input Voltage Range for V REF =2.5VL 8FIGURE4.The General Case of the V REF Operating Range01171108FIGURE5.The Specific Case of the V REF Operating Range for V A+=3.3V9分销商库存信息: NATIONAL-SEMICONDUCTOR LM12L458CIV/NOPB。