1/3L5510
December 2004 This is preliminary information on a new product now in development. Details are subject to change without notice. 1ATA Host Interface Block■Synchronous DMA (modes 0-4)■Fast IDE PIO modes 0-4■ATA Multiword DMA modes 0-2; supports 60 ns cycle time■Basic level of ATAPI support■IORDY for PIO flow control■Automatic ATA R/W command execution■Automatic ATA task file updates■128-byte host FIFO to/from buffer■LBA or CHS TASK File Modes■Read/write cache support with interrupt suppression■Programmable IRQ automation for different BIOS implementations■Provides logic for daisy chaining two embedded disk drive controllers■Full BIOS compatibility■On-chip selectable 4/8/12 mA host drivers2DSP
Core■60 MIPS operation■16-bit, fixed-point DSP■16x16-bit, 2’s complement parallel multiplier with 32-bit product■Single-cycle multiply and accumulate■36-bit ALU with two 36-bit accumulators■Bit manipulation unit with 2 additional accumulators■6 K words on-chip RAM3Buffer Controller Block■16-bit wide buffer data bus■16 Mbit x 16 SDRAM support; up to 150 Mbyte/s buffer bandwidth■Automated Data Flow Management (ADFM) automates disk/host transfers■Dynamic segment size switching■Auto-Write cache support■Automatic servo split address adjustment■Disk LBA counter4EDAC Block■Optimized ECC with up to six burst on-the-fly (OTF) correction■Programmable 480-bit Reed-Solomon code■Programmable 3-, 4-, or 5-way interleaving with 6 to 12 8-bit symbols per interleave■Optional 3 or 5 byte CRC support■Guarantee up to 233-bit single burst or six 33-bit bursts OTF correction in <3 sector time ■ECC seeding validating servo and head track position■AIC-8381 polynomial support for backward compatibility5Disk Controller Block■Enhanced Headerless Architecture (EDSA)■Up to 450 Mbits/s data rate, byte-wide NRZ■31 x 3 byte flexible high-speed RAM- based sequencer■Defect skipping and/or embedded servo capabilities with Constant Density Recording (CDR)■128-byte disk FIFO to/from buffer■Disk error condition summary bit added to reduce error detection time■Three-index timer■MR and PRML channel support6Servo
©2002 Fairchild Semiconductor CorporationRev. A, August 2002FJV3111R
NPN Epitaxial Silicon Transistor
Absolute Maximum Ratings
Ta=25°C unless otherwise noted
Electrical Characteristics Ta=25°C unless otherwise noted SymbolParameterValueUnitsVCBOCollector-Base Voltage40V
VCEOCollector-Emitter Voltage40V
VEBOEmitter-Base Voltage5V
ICCollector Current 100mA
PCCollector Power Dissipation200mW
TJJunction Temperature150°C
TSTGStorage Temperature-55 ~ 150°C
SymbolParameterTest ConditionMin.Typ.Max.UnitsBVCBOCollector-Base Breakdown VoltageIC=100µA, IE=040V
BVCEOCollector-Emitter Breakdown VoltageIE=1mA, IB=040V
ICBOCollector Cut-off CurrentVCB=30V, IE=00.1µA
hFEDC Current Gain VCE=5V, IC=1mA100600
VCE (sat)Collector-Emitter Saturation VoltageIC=10mA, IB=1mA0.3V
CobOutput CapacitanceVCB=10V, IE=0f=1MHz3.7pF
fTCurrent Gain Bandwidth ProductVCE=10V, IC=5mA250MHz
HZF SeriesSilicon Epitaxial Planar Zener Diodesfor Voltage Controller & Voltage LimitterADE-208-129B(Z)Rev 2Jul. 1997Features• Wide spectrum from 1.88V through 40V of zener voltage provide flexible application.• LRP package is suitable for high density surface mounting and high speed assembly.Ordering InformationType No.MarkPackage CodeHZF SeriesLet to Mark CodeLRPOutline121. Cathode2. AnodeCathode markMark2.0BHZF Series
2Absolute Maximum Ratings (Ta = 25°C)ItemSymbolValueUnitPower dissipationPd0.9WJunction temperatureTj150°CStorage temperatureTstg-55 to +150°CElectrical Characteristics (Ta = 25°C)Zener VoltageReverese CurrentDynamic ResistanceVZ (V)*1TestConditionIR (mA)TestConditionrd (W)TestConditionTypeGradeMinMaxIZ (mA)MaxVR (V)MaxIZ (mA)HZF2.0BP1.882.12402000.52540CP2.002.24HZF2.2BP2.082.33402000.72040CP2.202.45HZF2.4BP2.282.56402001.01540CP2.402.70HZF2.7BP2.52.9402001.01540CP2.73.1HZF3.0BP2.83.2401001.01540CP3.03.4HZF3.3BP3.13.540801.01540CP3.33.7HZF3.6BP3.43.840601.01540CP3.64.0HZF3.9BP3.74.140401.01540CP3.94.4HZF4.3BP4.04.540201.01540CP4.34.8HZF4.7BP4.44.940201.01040CP4.75.2HZF5.1BP4.85.440201.0840CP5.15.7Note:1.Tested with DC.HZF Series
2383BS–WLAN–01/04Features•Wireless Interface Following the IEEE 802.11b Standard•Two Ethernet MAC Units (EMU) Interfaces with 10/100 Mbits Ethernet Physical Layer Transceivers through Standard MII Ports•Dual ARM7TDMI® RISC Processor Architecture•Inter-networking ARM7TDMI (INWARM) with 16 Kbytes Program and Data Cache Controls the Ethernet MAC Units and Provides the Bridging Functions between Ethernet and Wireless Interfaces •WLAN ARM7TDMI (WLANARM) with a Dedicated 32 Kbytes Program Memory Coordinates the 802.11b MAC Functionality•802.11b MAC Unit with 512-byte Transmit and 128-byte Receive FIFOs•SDRAM Interface Supporting up to 256 MBytes of External Memory Shared between Both Processors•32-bit DMA Channels Are Used for Data Packet Transfers between the SDRAM and the MAC Units•Enciphering/Deciphering of Wireless Data On-the-fly Ensures Maximum Privacy of Data•SPI Interface and Eight GPIO Pins that Can Be Used As Slave-Select Pins•A Bootstrap ROM Is Used in the Initialization Phase by the WLAN ARM® to Execute a Code Downloading Procedure from an SPI Flash to Its Internal Program Memory•UART with 16-byte Receive and Transmit FIFO and Programmable Baud Rate up to 921 Kbaud•Supports 802.1f (IAPP) and Tap-Dance™ (Atmel proprietary roaming protocol)•2.5 V for Core and 3.3 V for I/O•Different Packages, Depending on the RequirementsBlock DiagramInter-networkingARM Core(INWARM)Decoder/Arbiter/Bridge #2Timers,InterruptController #2CacheMemoryExternal Memory InterfaceInternalMemory #1Common Memory
