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1Features•Single 2.5V - 3.6V or 2.7V - 3.6V Supply•Serial Peripheral Interface (SPI) Compatible•20 MHz Max Clock Frequency•Page Program Operation–Single Cycle Reprogram (Erase and Program)–4096 Pages (264 Bytes/Page) Main Memory•Supports Page and Block Erase Operations•Two 264-byte SRAM Data Buffers – Allows Receiving of Datawhile Reprogramming of Nonvolatile Memory•Continuous Read Capability through Entire Array–Ideal for Code Shadowing Applications•Low Power Dissipation–4 mA Active Read Current Typical–2 µA CMOS Standby Current Typical•Hardware Data Protection Feature•100% Compatible to AT45DB081 and AT45DB081A• 5.0V-tolerant Inputs: SI, SCK, CS, RESET and WP Pins•Commercial and Industrial Temperature Ranges•Green (Pb/Halide-free) Packaging OptionsDescriptionThe AT45DB081B is a 2.5-volt or 2.7-volt only, serial interface Flash memory ideallysuited for a wide variety of digital voice-, image-, program code- and data-storageapplications. Its 8,650,752 bits of memory are organized as 4096 pages of 264 byteseach. In addition to the main memory, the AT45DB081B also contains two SRAMdata buffers of 264 bytes each. The buffers allow receiving of data while a page in themain memory is being reprogrammed, as well as writing a continuous data stream.TSOP T op ViewT ype 1CBGA Top Viewthrough PackageSOICPin Configurations Pin Name Function CS Chip Select SCK Serial Clock SI Serial Input SO Serial Output WP Hardware Page Write Protect Pin RESET Chip ResetRDY/BUSY Ready/Busy CASON Top View through Package2AT45DB081B2225I–DFLSH–9/05EEPROM emulation (bit or byte alterability) is easily handled with a self-contained threestep Read-Modify-Write operation. Unlike conventional Flash memories that areaccessed randomly with multiple address lines and a parallel interface, the DataFlashuses a SPI serial interface to sequentially access its data. DataFlash supports SPI mode0 and mode 3. The simple serial interface facilitates hardware layout, increases systemreliability, minimizes switching noise, and reduces package size and active pin count.The device is optimized for use in many commercial and industrial applications wherehigh density, low pin count, low voltage, and low power are essential. The device oper-ates at clock frequencies up to 20 MHz with a typical active read current consumption of4 mA.To allow for simple in-system reprogrammability, the AT45DB081B does not requirehigh input voltages for programming. The device operates from a single power supply,2.5V to3.6V or 2.7V to 3.6V, for both the program and read operations. The interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock(SCK).All programming cycles are self-timed, and no separate erase cycle is required beforeprogramming.When the device is shipped from Atmel, the most significant page of the memory arraymay not be erased. In other words, the contents of the last page may not be filled withFFH.Block DiagramMemory Array To provide optimal flexibility, the memory array of the AT45DB081B is divided into threelevels of granularity comprising of sectors, blocks, and pages. The Memory ArchitectureDiagram illustrates the breakdown of each level and details the number of pages persector and block. All program operations to the DataFlash occur on a page-by-pagebasis; however, the optional erase operations can be performed at the block or pagelevel.3AT45DB081B2225I–DFLSH–9/05Memory Architecture DiagramDevice Operation The device operation is controlled by instructions from the host processor. The list ofinstructions and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, tog-gling the SCK pin controls the loading of the opcode and the desired buffer or mainmemory address location through the SI (serial input) pin. All instructions, addressesand data are transferred with the most significant bit (MSB) first.Buffer addressing is referenced in the datasheet using the terminology BFA8-BFA0 todenote the nine address bits required to designate a byte address within a buffer. Mainmemory addressing is referenced using the terminology PA11-PA0 and BA8-BA0where PA11-PA0 denotes the 12address bits required to designate a page addressand BA8-BA0 denotes the nine address bits required to designate a byte addresswithin the page.Read Commands By specifying the appropriate opcode, data can be read from the main memory or fromeither one of the two data buffers. The DataFlash supports two categories of readmodes in relation to the SCK signal. The differences between the modes are in respectto the inactive state of the SCK signal as well as which clock cycle data will begin to beoutput. The two categories, which are comprised of four modes total, are defined asInactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPIMode 3. A separate opcode (refer to Table 1 on page 10 for a complete list) is used toselect which category will be used for reading. Please refer to the “Detailed Bit-levelRead Timing” diagrams in this datasheet for details on the clock cycle sequences foreach mode.CONTINUOUS ARRAY READ: By supplying an initial starting address for the mainmemory array, the Continuous Array Read command can be utilized to sequentiallyread a continuous stream of data from the device by simply providing a clock signal; noadditional addressing information or control signals need to be provided. The DataFlashincorporates an internal address counter that will automatically increment on every clock4AT45DB081B2225I–DFLSH–9/05cycle, allowing one continuous read operation without the need of additional addresssequences. To perform a continuous read, an opcode of 68H or E8H must be clockedinto the device followed by 24 address bits and 32 don’t care bits. The first three bits ofthe 24-bit address sequence are reserved for upward and downward compatibility tolarger and smaller density devices (see Notes under “Command Sequence forRead/Write Operations” diagram). The next 12 address bits (PA11-PA0) specify whichpage of the main memory array to read, and the last nine bits (BA8-BA0) of the 24-bitaddress sequence specify the starting byte address within the page. The 32 don’t carebits that follow the 24 address bits are needed to initialize the read operation. Followingthe 32 don’t care bits, additional clock pulses on the SCK pin will result in serial databeing output on the SO (serial output) pin.care bits, and the reading of data. When the end of a page in main memory is reachedduring a Continuous Array Read, the device will continue reading at the beginning of thenext page with no delays incurred during the page boundary crossover (the crossoverfrom the end of one page to the beginning of the next page). When the last bit in themain memory array has been read, the device will continue reading back at the begin-ning of the first page of memory. As with crossing over page boundaries, no delays willbe incurred when wrapping around from the end of the array to the beginning of thearray.SO pin. The maximum SCK frequency allowable for the Continuous Array Read isdefined by the f CAR specification. The Continuous Array Read bypasses both data buff-ers and leaves the contents of the buffers unchanged.MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read datadirectly from any one of the 4096 pages in the main memory, bypassing both of the databuffers and leaving the contents of the buffers unchanged. To start a page read, anopcode of 52H or D2H must be clocked into the device followed by 24 address bits and32 don’t care bits. The first three bits of the 24-bit address sequence are reserved bits,the next 12 address bits (PA11-PA0) specify the page address, and the next nineaddress bits (BA8-BA0) specify the starting byte address within the page. The 32 don’tcare bits which follow the 24 address bits are sent to initialize the read operation. Fol-lowing the 32 don’t care bits, additional pulses on SCK result in serial data being output opcode, the address bits, the don’t care bits, and the reading of data. When the end of apage in main memory is reached during a Main Memory Page Read, the device will con-will terminate the read operation and tri-state the SO pin.BUFFER READ: Data can be read from either one of the two buffers, using differentopcodes to specify which buffer to read from. An opcode of 54H or D4H is used to readdata from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. Toperform a Buffer Read, the eight bits of the opcode must be followed by 15 don’t carebits, nine address bits, and eight don’t care bits. Since the buffer size is 264 bytes, nineaddress bits (BFA8-BFA0) are required to specify the first byte of data to be read from bits, the don’t care bits, and the reading of data. When the end of a buffer is reached,the device will continue reading back at the beginning of the buffer. A low-to-high transi-STATUS REGISTER READ: The status register can be used to determine the device’sReady/Busy status, the result of a Main Memory Page to Buffer Compare operation, orthe device density. To read the status register, an opcode of 57H or D7H must be5AT45DB081B2225I–DFLSH–9/05loaded into the device. After the last bit of the opcode is shifted in, the eight bits of thestatus register, starting with the MSB (bit 7), will be shifted out on the SO pin during thenext eight clock cycles. The five most significant bits of the status register will containdevice information, while the remaining three least-significant bits are reserved for futureuse and will have undefined values. After bit 0 of the status register has been shifted gled) starting again with bit 7. The data in the status register is constantly updated, soeach repeating sequence will output new data.Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then thedevice is not busy and is ready to accept the next command. If bit 7 is a 0, then thedevice is in a busy state. The user can continuously poll bit 7 of the status register bystopping SCK at a low level once bit 7 has been output. The status of bit 7 will continueto be output on the SO pin, and once the device is no longer busy, the state of SO willchange from 0 to 1. There are eight operations which can cause the device to be in abusy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Com-pare, Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main MemoryPage Program without Built-in Erase, Page Erase, Block Erase, Main Memory PageProgram, and Auto Page Rewrite.The result of the most recent Main Memory Page to Buffer Compare operation is indi-cated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memorypage matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in themain memory page does not match the data in the buffer.The device density is indicated using bits 5, 4, 3 and 2 of the status register. For theAT45DB081B, the four bits are 1, 0, 0 and 1. The decimal value of these four binary bitsdoes not equate to the device density; the three bits represent a combinational coderelating to differing densities of Serial DataFlash devices, allowing a total of sixteen dif-ferent density configurations.Program and EraseCommands BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 or buffer 2.To load data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, mustbe followed by 15 don’t care bits and nine address bits (BFA8-BFA0). The nineaddress bits specify the first byte in the buffer to be written. The data is entered followingthe address bits. If the end of the data buffer is reached, the device will wrap aroundback to the beginning of the buffer. Data will continue to be loaded into the buffer until a BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data writteninto either buffer 1 or buffer 2 can be programmed into the main memory. To start theoperation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be followed by thethree reserved bits, 12 address bits (PA11-PA0) that specify the page in the mainmemory to be written, and nine additional don’t care bits. When a low-to-high transition and then program the data stored in the buffer into the specified page in the main mem-ory. Both the erase and the programming of the page are internally self-timed andshould take place in a maximum time of t EP . During this time, the status register will indi-cate that the part is busy.Status Register Format Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0RDY/BUSY COMP 1001X X6AT45DB081B2225I–DFLSH–9/05BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: Apreviously erased page within main memory can be programmed with the contents ofeither buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or89H for buffer 2, must be followed by the three reserved bits, 12 address bits(PA11-PA0) that specify the page in the main memory to be written, and nine addi-program the data stored in the buffer into the specified page in the main memory. It isnecessary that the page in main memory that is being programmed has been previouslyerased. The programming of the page is internally self-timed and should take place in amaximum time of t P . During this time, the status register will indicate that the part isbusy.Successive page programming operations without doing a page erase are not recom-mended. In other words, changing bytes within a page from a “1” to a “0” during multiplepage programming operations without erasing that page is not recommended.PAGE ERASE: The optional Page Erase command can be used to individually eraseany page in the main memory array allowing the Buffer to Main Memory Page Programwithout Built-in Erase command to be utilized at a later time. To perform a Page Erase,an opcode of 81H must be loaded into the device, followed by three reserved bits,12address bits (PA11-PA0), and nine don’t care bits. The 12 address bits are used tospecify which page of the memory array is to be erased. When a low-to-high transition internally self-timed and should take place in a maximum time of t PE . During this time,the status register will indicate that the part is busy.BLOCK ERASE: A block of eight pages can be erased at one time allowing the Bufferto Main Memory Page Program without Built-in Erase command to be utilized to reduceprogramming times when writing large amounts of data to the device. To perform aBlock Erase, an opcode of 50H must be loaded into the device, followed by threereserved bits, nine address bits (PA11-PA3), and 12 don’t care bits. The nine addressbits are used to specify which block of eight pages is to be erased. When a low-to-high 1s. The erase operation is internally self-timed and should take place in a maximumtime of t BE . During this time, the status register will indicate that the part is busy.Block Erase Addressing PA11PA10PA9PA8PA7PA6PA5PA4PA3PA2PA1PA0Block00000000X X X 0000000001X X X 1000000010X X X 2000000011X X X 3•••••••••••••••••••••••••••••••••••••••111111100X X X 508111111101X X X 509111111110X X X 510111111111X X X 5117AT45DB081B2225I–DFLSH–9/05MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combina-tion of the Buffer Write and Buffer to Main Memory Page Program with Built-in Eraseoperations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then pro-grammed into a specified page in the main memory. To initiate the operation, an 8-bitopcode, 82H for buffer 1 or 85H for buffer 2, must be followed by the three reserved bitsand 21 address bits. The 12 most significant address bits (PA11-PA0) select the pagein the main memory where data is to be written, and the next nine address bits(BFA8-BFA0) select the first byte in the buffer to be written. After all address bits areshifted in, the part will take data from the SI pin and store it in one of the data buffers. Ifthe end of the buffer is reached, the device will wrap around back to the beginning of the selected page in main memory to all 1s and then program the data stored in the bufferinto the specified page in the main memory. Both the erase and the programming of thepage are internally self-timed and should take place in a maximum of time t EP . Duringthis time, the status register will indicate that the part is busy.Additional Commands MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferredfrom the main memory to either buffer 1 or buffer 2. To start the operation, an 8-bitopcode, 53H for buffer 1 and 55H for buffer 2, must be followed by the three reservedbits, 12 address bits (PA11-PA0) which specify the page in main memory that is to be to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer sitions from a low to a high state. During the transfer of a page of data (t XFR ), the statusregister can be read to determine whether the transfer has been completed or not.MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory canbe compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode,60H for buffer 1 and 61H for buffer 2, must be followed by 24 address bits consisting ofthe three reserved bits, 12 address bits (PA11-PA0) which specify the page in the main be low while toggling the SCK pin to load the opcode, the address bits, and the don’t selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2.During this time (t XFR ), the status register will indicate that the part is busy. On comple-tion of the compare operation, bit 6 of the status register is updated with the result of thecompare.AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page ormultiple pages of data are modified in a random fashion. This mode is a combination oftwo operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory PageProgram with Built-in Erase. A page of data is first transferred from the main memory tobuffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmedback into its original page of main memory. To start the rewrite operation, an 8-bitopcode, 58H for buffer 1 or 59H for buffer 2, must be followed by the three reserved bits,12 address bits (PA11-PA0) that specify the page in main memory to be rewritten, and part will first transfer data from the page in main memory to a buffer and then programthe data from the buffer back into same page of main memory. The operation is inter-nally self-timed and should take place in a maximum time of t EP . During this time, thestatus register will indicate that the part is busy.8AT45DB081B2225I–DFLSH–9/05If a sector is programmed or reprogrammed sequentially page-by-page, then the pro-gramming algorithm shown in Figure 1 on page 26 is recommended. Otherwise, ifmultiple bytes in a page or several pages are programmed randomly in a sector, thenthe programming algorithm shown in Figure 2 on page 27 is recommended. Each pagewithin a sector must be updated/rewritten at least once within every 10,000 cumulativepage erase/program operations in that sector.Operation ModeSummary The modes described can be separated into two groups – modes which make use of theFlash memory array (Group A) and modes which do not make use of the Flash memoryarray (Group B).Group A modes consist of:1.Main Memory Page Read2.Main Memory Page to Buffer 1 (or 2) Transfer3.Main Memory Page to Buffer 1 (or 2) Compare4.Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase5.Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase6.Page Erase7.Block Erase8.Main Memory Page Program through Buffer9.Auto Page RewriteGroup B modes consist of:1.Buffer 1 (or 2) Read2.Buffer 1 (or 2) Write3.Status Register ReadIf a Group A mode is in progress (not fully completed) then another mode in Group Ashould not be started. However, during this time in which a Group A mode is inprogress, modes in Group B can be started.This gives the Serial DataFlash the ability to virtually accommodate a continuous datastream. While data is being programmed into main memory from buffer 1, data can beloaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s SerialDataFlash”) for more details.Pin Descriptions SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data into thedevice. The SI pin is used for all data input including opcodes and address sequences.SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data outfrom the device.SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flowof data to and from the DataFlash. Data is always clocked into the device on the risingedge of SCK and clocked out of the device on the falling edge of SCK.device is not selected, data will not be accepted on the SI pin, and the SO pin will operation.9AT45DB081B2225I–DFLSH–9/05WRITE PROTECT:cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drivethe protect pin high and then use the program commands previously mentioned. If this externally.and reset the internal state machine to an idle state. The device will remain in the reset The device incorporates an internal power-on reset circuit, so there are no restrictions This open drain output pin will be driven low when the device is busy inan internally self-timed operation. This pin, which is normally in a high state (througha 1k Ω external pull-up resistor), will be pulled low during programming operations, com-pare operations, and during page-to-buffer transfers.The busy status indicates that the Flash memory array and one of the buffers cannot beaccessed; read and write operations to the other buffer can still be performed.Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, thedevice will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruc-tion. The SPI mode will be automatically selected on every falling edge of CS bysampling the inactive clock state. After power is applied and V CC is at the minimumdatasheet value, the system should wait 20 ms before an operational mode is started.10AT45DB081B2225I–DFLSH–9/05Note:In T ables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock PolarityLow, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3).Table 1. Read CommandsCommandSCK Mode Opcode Continuous Array Read Inactive Clock Polarity Low or High68H SPI Mode 0 or 3E8H Main Memory Page Read Inactive Clock Polarity Low or High52H SPI Mode 0 or 3D2H Buffer 1 Read Inactive Clock Polarity Low or High54H SPI Mode 0 or 3D4H Buffer 2 Read Inactive Clock Polarity Low or High56H SPI Mode 0 or 3D6H Status Register ReadInactive Clock Polarity Low or High57H SPI Mode 0 or 3D7H Table 2. Program and Erase Commands CommandSCK Mode Opcode Buffer 1 WriteAny 84H Buffer 2 WriteAny 87H Buffer 1 to Main Memory Page Program with Built-in EraseAny 83H Buffer 2 to Main Memory Page Program with Built-in EraseAny 86H Buffer 1 to Main Memory Page Program without Built-in EraseAny 88H Buffer 2 to Main Memory Page Program without Built-in EraseAny 89H Page EraseAny 81H Block EraseAny 50H Main Memory Page Program through Buffer 1Any 82H Main Memory Page Program through Buffer 2Any 85HTable 3. Additional CommandsCommandSCK Mode Opcode Main Memory Page to Buffer 1 TransferAny 53H Main Memory Page to Buffer 2 TransferAny 55H Main Memory Page to Buffer 1 CompareAny 60H Main Memory Page to Buffer 2 CompareAny 61H Auto Page Rewrite through Buffer 1Any 58H Auto Page Rewrite through Buffer 2Any 59H11AT45DB081B2225I–DFLSH–9/05P = Page Address BitB = Byte/Buffer Address Bit x = Don’t CareTable 4. Detailed Bit-level Addressing SequenceOpcode OpcodeAddress ByteAddress ByteAddress ByteAdditional Don’t Care Bytes Required50H 01010000r r r P P P P P P P P P x x x x x x x x x x x x N/A 52H 01010010r r r P P P P P P P P P P P P B B B B B B B B B 4 Bytes 53H 01010011r r r P P P P P P P P P P P P x x x x x x x x x N/A 54H 01010100x x x x x x x x x x x x x x x B B B B B B B B B 1 Byte 55H 01010101r r r P P P P P P P P P P P P x x x x x x x x x N/A 56H 01010110x xxxx xxxxxxxx xxBBBBBB BBB1 Byte 57H 01010111N/AN/AN/AN/A58H 01011000r r r P P P P P P P P P P P P x x x x x x x x x N/A 59H 01011001r r r P P P P P P P P P P P P x x x x x x x x x N/A 60H 01100000r r r P P P P P P P P P P P P x x x x x x x x x N/A 61H 01100001r r r P P P P P P P P P P P P x x x x x x x x x N/A 68H 01101000r r r P P P P P P P P P P P P B B B B B B B B B 4 Bytes 81H 10000001r r r P P P P P P P P P P P P x x x x x x x x x N/A 82H 10000010r r r P P P P P P P P P P P P B B B B B B B B B N/A 83H 10000011r r r P P P P P P P P P P P P x x x x x x x x x N/A 84H 10000100x x x x x x x x x x x x x x x B B B B B B B B B N/A 85H 10000101r r r P P P P P P P P P P P P B B B B B B B B B N/A 86H 10000110r r r P P P P P P P P P P P P x x x x x x x x x N/A 87H 10000111x x x x x x x x x x x x x x x B B B B B B B B B N/A 88H 10001000r r r P P P P P P P P P P P P x x x x x x x x x N/A 89H 10001001r r r P P P P P P P P P P P P x x x x x x x x x N/A D2H 11010010r r r P P P P P P P P P P P P B B B B B B B B B 4 Bytes D4H 11010100x x x x x x x x x x x x x x x B B B B B B B B B 1 Byte D6H 11010110x xxxx xxxxxxxx xxBBBBBB BBB1 Byte D7H 11010111N/AN/AN/AN/AE8H11101000rr r P P P P P P P P P P P P B B B B B BBBB4 BytesR e s e r v e dR e s e r v e dR e s e r v e dP A 11P A 10P A 9P A 8P A 7P A 6P A 5P A 4P A 3P A 2P A 1P A 0B A 8B A 7B A 6B A 5B A 4B A 3B A 2B A 1B A 012AT45DB081B2225I–DFLSH–9/05Note:1.After power is applied and V CC is at the minimum specified datasheet value, the system should wait 20 ms before an opera-tional mode is started.Note:1.I cc1 during a buffer read is 20mA maximum.Absolute Maximum Ratings*T emperature under Bias ................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature.....................................-65°C to +150°C All Input Voltages (including NC Pins)with Respect to Ground...................................-0.6V to +6.25V All Output Voltageswith Respect to Ground.............................-0.6V to V CC + 0.6VDC and AC Operating RangeAT45DB081B (2.5V Version)AT45DB081B Operating T emperature (Case)Com.0°C to 70°C0°C to 70°C Ind.–-40°C to 85°C V CC Power Supply (1) 2.5V to 3.6V2.7V to3.6VDC CharacteristicsSymbol Parameter ConditionMinTyp Max Units I SB Standby Current CS, RESET, WP = V CC , all inputs at CMOS levels210µA I CC1(1)Active Current, Read Operationf = 20 MHz; I OUT = 0 mA; V CC = 3.6V 410mA I CC2Active Current,Program/Erase Operation V CC = 3.6V 1535mA I LI Input Load Current V IN = CMOS levels 1µA I LO Output Leakage Current V I/O = CMOS levels1µA V IL Input Low Voltage 0.6V V IH Input High Voltage 2.0V V OL Output Low Voltage I OL = 1.6 mA; V CC = 2.7V 0.4V V OH Output High VoltageI OH = -100 µAV CC - 0.2VV。
TECHNICAL DATA138Quad 2-Input AND GateHigh-Voltage Silicon-Gate CMOSThe IW4081B AND gates provide the system designer with direct emplementation of the AND function.• Operating Voltage Range: 3.0 to 18 V• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C• Noise margin (over full package temperature range):********************************************************IW4081BLOGIC DIAGRAMPIN 14 =V CC PIN 7 = GNDPIN ASSIGNMENTFUNCTION TABLEInputsOutput A B Y L L L L H L H L L HHHIW4081B139MAXIMUM RATINGS *Symbol ParameterValue Unit V CC DC Supply Voltage (Referenced to GND)-0.5 to +20V V IN DC Input Voltage (Referenced to GND)-0.5 to V CC +0.5V V OUT DC Output Voltage (Referenced to GND)-0.5 to V CC +0.5V I IN DC Input Current, per Pin±10mA P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+750500mW P D Power Dissipation per Output Transistor 100mW Tstg Storage Temperature-65 to +150°C T LLead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)260°C*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°CSOIC Package: : - 7 mW/°C from 65° to 125°CRECOMMENDED OPERATING CONDITIONSSymbol ParameterMin Max Unit V CC DC Supply Voltage (Referenced to GND)3.018V V IN , V OUTDC Input Voltage, Output Voltage (Referenced to GND)0V CC V T AOperating Temperature, All Package Types-55+125°CThis device contains protection circuitry to guard against damage due to high static voltages or electricfields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND ≤(V IN or V OUT )≤V CC .Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ).Unused outputs must be left open.IW4081B140DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)V CCGuaranteed Limit Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125°C Unit V IHMinimum High-Level Input VoltageV OUT =0.5V or V CC - 0.5V V OUT =1.0V or V CC - 1.0V V OUT =1.5V or V CC - 1.5V5.01015 3.5711 3.5711 3.5711VV ILMaximum Low -Level Input Voltage V OUT =0.5V V OUT =1.0VV OUT =1.5V 5.01015 1.534 1.534 1.534VV OH Minimum High-Level Output Voltage V IN =V CC5.01015 4.959.9514.95 4.959.9514.95 4.959.9514.95VV OL Maximum Low-Level Output Voltage V IN =GND or V CC 5.010150.050.050.050.050.050.050.050.050.05VI IN Maximum Input Leakage Current V IN = GND or V CC 18±0.1±0.1±1.0µA I CCMaximum Quiescent Supply Current (per Package)V IN = GND or V CC5.01015200.250.51.05.00.250.51.05.07.51530150µAI OLMinimum Output Low (Sink) Current V IN = GND or V CC U OL =0.4 VU OL =0.5 V U OL =1.5 V 5.010150.641.64.20.511.33.40.360.92.4mAI OHMinimum Output High (Source) Current V IN = GND or V CC U OH =2.5 VU OH =4.6 V U OH =9.5 V U OH =13.5 V5.05.01015-2.0-0.64-1.6-4.2-1.6-0.51-1.3-3.4-1.15-0.36-0.9-2.4mAIW4081B141AC ELECTRICAL CHARACTERISTICS (C L =50pF, R L =200k Ω, Input t r =t f =20 ns)V CCGuaranteed Limit Symbol ParameterV ≥-55°C25°C ≤125°C Unit t PLH , t PHLMaximum Propagation Delay, Input A or B to Output Y (Figure 1)5.010152501209025012090500240180nst TLH , t THL Maximum Output Transition Time, Any Output (Figure 1)5.010152001008020010080400200160nsC IN Maximum Input Capacitance-7.5pFFigure 1. Switching WaveformsEXPANDED LOGIC DIAGRAM(1/4 of the Device)。
