VINVOUT1.8VL1ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityTLV62565,TLV62566SLVSBC1B–OCTOBER2013–REVISED DECEMBER2014 TLV6256x1.5-A High Efficiency Step-Down Converters in SOT-235-Pin Package1Features3DescriptionThe TLV62565/6devices are synchronous step-down • 2.7-V to5.5-V Input Voltage Rangeconverters optimized for small solution size and high • 1.5-MHz Typical Switching Frequency efficiency.The devices integrate switches capable of•Output Current up to1.5A(Max)delivering an output current up to1.5A.•Adaptive On-Time Current Control The devices are based on an adaptive on time with •Power Save Mode for Light Load Efficiency valley current mode control scheme.Typicaloperating frequency is1.5MHz at medium to heavy •50-µA Operating Quiescent Currentloads.The devices are optimized to achieve very low •Up to95%Efficiencyoutput voltage ripple even with small external •Over Current Protection components and feature an excellent load transientresponse.•95%Maximum Duty Cycle•Excellent AC and Transient Load Response During a light load,the TLV62565/6automaticallyenter into Power Save Mode at the lowest quiescent •Power Good Output,TLV62566current(50μA typ)to maintain high efficiency over •Internal Soft Startup of250µs(Typ)the entire load current range.In shutdown,the •Adjustable Output Voltage current consumption is reduced to less than1μA.•Thermal Shutdown ProtectionThe TLV62565/6provide an adjustable output voltage •Available in SOT-235-Pin Package via an external resistor divider.The output voltagestart-up ramp is controlled by an internal soft start, 2Applications typically250µs.Power sequencing is possible byconfiguring the Enable(TLV62565)and Power Good •Portable Devices(TLV62566)pins.Other features like over current •DSL Modems protection and over temperature protection are built-•Hard Disk Drivers in.The TLV62565/6devices are available in a SOT-235-pin package.•Set Top Box•Tablet Device Information(1)PART NUMBER PACKAGE BODY SIZE(NOM)TLV62565,SOT-23(5) 2.90mm×1.60mmTLV62566(1)For all available packages,see the orderable addendum atthe end of the datasheet.4Simplified SchematicEfficiency vs Load CurrentTLV62565,TLV62566SLVSBC1B–OCTOBER2013–REVISED Table of Contents10.3Feature Description (11)1Features (1)10.4Device Functional Modes (12)2Applications (1)11Application and Implementation (13)3Description (1)11.1Application Information (13)4Simplified Schematic (1)11.2Typical Application (13)5Revision History (2)12Power Supply Recommendations (17)6Device Comparison Table (3)13Layout (18)7Pin Configuration and Functions (3)13.1Layout Guidelines (18)8Specifications (4)13.2Layout Example (18)8.1Absolute Maximum Ratings (4)13.3Thermal Considerations (18)8.2ESD Ratings (4)14Device and Documentation Support (19)8.3Recommended Operating Conditions (4)14.1Device Support (19)8.4Thermal Information (4)14.2Documentation Support (19)8.5Electrical Characteristics (5)14.3Related Links (19)8.6Typical Characteristics (6)14.4Trademarks (19)9Parameter Measurement Information (8)14.5Electrostatic Discharge Caution (19)10Detailed Description (9)14.6Glossary (19)10.1Overview (9)15Mechanical,Packaging,and Orderable10.2Functional Block Diagrams...................................10Information.. (19)5Revision HistoryNOTE:Page numbers for previous revisions may differ from page numbers in the current version.Changes from Revision A(November2014)to Revision B Page •Added Storage temperature to Absolute Maximum Ratings (4)•Changed Handling Ratings to ESD Ratings (4)•Deleted Storage temperature from ESD Ratings (4)•Changed Thermal Information to Thermal Considerations and moved to Layout section (18)Changes from Original(October2013)to Revision A Page •Changed Added Handling Rating table,Feature Description section,Device Functional Modes,Application and Implementation section,Power Supply Recommendations section,Layout section,Device and DocumentationSupport section,and Mechanical,Packaging,and Orderable Information section (1)•Added"T A=-40°C to85°C"to the V FB,Feedback regulation voltage Test Conditions (5)•Added V FB,Feedback regulation voltage Test Conditions and values for"PWM operation,T A=85°C" (5)2Submit Documentation Feedback Copyright©2013–2014,Texas Instruments Incorporated12345VIN SWGND FB EN/PG TLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 20146Device Comparison TablePART NUMBER FUNCTIONTLV62566EN TLV62566PG7Pin Configuration and Functions5-Pin SOT-23DBV Package (Top View)Pin FunctionsPINNUMBERI/O/PWRDESCRIPTIONNAME TLV62565TLV62566Device enable logic input.Logic HIGH enables the device,logic low disables the device EN 1—I and turns it into shutdown.Feedback pin for the internal control loop.Connect this pin to the external feedback FB 55I divider.GND 22PWR Ground pin.Power Good open drain output.This pin is high impedance if the output voltage is within PG —1O regulation.It is pulled low if the output is below its nominal value.It is also in logic low when V IN below UVLO or thermal shutdown triggers.Switch pin connected to the internal MOSFET switches and inductor terminal.Connect SW 33PWR the inductor of the output filter to this pin.VIN44PWRPower supply voltage input.Copyright ©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback 3TLV62565,TLV62566SLVSBC1B–OCTOBER2013–REVISED 8Specifications8.1Absolute Maximum RatingsOver operating free-air temperature range(unless otherwise noted)(1)MIN MAX UNITVIN,EN,PG–0.37V Voltage(2)SW–0.3V IN+0.3VFB–0.3 3.6V Sink current,I PG PG660µA Continuous total power dissipation See Thermal InformationOperating junction temperature,T J–40150°C Storage temperature,T stg–65150°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.(2)All voltage values are with respect to network ground terminal.8.2ESD RatingsVALUE UNIT Human-body model(HBM),per ANSI/ESDA/JEDEC JS-001(1)±2000V ElectrostaticV(ESD)discharge Charged-device model(CDM),per JEDEC specification JESD22-C101(2)±500V(1)JEDEC document JEP155states that500-V HBM allows safe manufacturing with a standard ESD control process.(2)JEDEC document JEP157states that250-V CDM allows safe manufacturing with a standard ESD control process.8.3Recommended Operating Conditions(1)MIN TYP MAX UNIT V IN Input voltage,VIN 2.7 5.5VT A Operating ambient temperature–4085°C (1)Refer to the Application and Implementation section for further information.8.4Thermal InformationTLV62565,TLV62566THERMAL METRIC(1)UNITDBV(5Pins)RθJA Junction-to-ambient thermal resistance208.3RθJC(top)Junction-to-case(top)thermal resistance73.7RθJB Junction-to-board thermal resistance36.1°C/WψJT Junction-to-top characterization parameter 2.3ψJB Junction-to-board characterization parameter35.3RθJC(bot)Junction-to-case(bottom)thermal resistance N/A(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.4Submit Documentation Feedback Copyright©2013–2014,Texas Instruments IncorporatedTLV62565,TLV62566 SLVSBC1B–OCTOBER2013–REVISED DECEMBER20148.5Electrical CharacteristicsOver recommended free-air temperature range,V IN=3.6V,T A=-40°C to85°C,typical values are at T A=25°C(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLYV IN Input voltage 2.7 5.5VI Q Quiescent current into VIN pin I OUT=0mA,Not switching50uAUnder voltage lock out V IN falling 2.2 2.3VV UVLOUnder voltage lock out hysteresis200mVThermal shutdown Junction temperature rising150T JSD°C Thermal shutdown hysteresis Junction temperature falling below T JSD20LOGIC INTERFACE,TLV62565V IH High-level input voltage 2.7V≤V IN≤5.5V 1.2VV IL Low-level input voltage 2.7V≤V IN≤5.5V0.4VI SD Shutdown current into VIN pin EN=LOW0.11µAI EN,LKG EN leakage current0.010.16µA POWER GOOD,TLV62566Power Good low threshold V FB falling referenced to V FB nominal90%V PGPower Good high threshold V FB risng referenced to V FB nominal95%V L Low level voltage I sink=500µA0.4VI PG,LKG PG Leakage current V PG=5.0V0.010.17µA OUTPUTV OUT Output voltage0.6D MAX.V IN VPWM operation,T A=-40°C to85°C0.5880.60.612VV FB Feedback regulation voltage PWM operation,T A=85°C0.5940.60.606VPFM comparator threshold0.9%I FB Feedback input bias current V FB=0.6V10100nAHigh-side FET on resistance I SW=500mA,V IN=3.6V173R DS(on)mΩLow-side FET on resistance I SW=500mA,V IN=3.6V105I LIM,LS Low-side FET valley current limit 1.5AI LIM,HS High-side FET peak current limit 1.8Af SW Switching frequency 1.5MHzD MAX Maximum duty cycle95%t OFF,MIN Minimum off time40ns Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback5TLV62565,TLV62566SLVSBC1B–OCTOBER2013–REVISED 8.6Typical CharacteristicsTable1.Table of GraphsFIGURE vs Load current(V OUT=1.8V,V IN=2.7V,3.6V,5.5V)Figure1 Efficiency vs Load current(V OUT=1.2V,V IN=2.7V,3.6V,5.5V)Figure2 vs Load current(V OUT=3.3V,V IN=4.2V,5.5V)Figure3vs Input voltage(Line regulation,V OUT=1.8V,Load=0.5A,1A,1.5A)Figure4 Output voltagevs Load current(Load regulation,V OUT=1.8V,V IN=2.7V,3.6V,5.5V)Figure5 Quiescent current vs Input voltage Figure6vs Input voltage,High-Side FET Figure7R DS(on)vs Input voltage,Low-Side FET Figure8 Switching frequency vs Load current,V OUT=1.8V Figure96Submit Documentation Feedback Copyright©2013–2014,Texas Instruments IncorporatedTLV62565,TLV62566 SLVSBC1B–OCTOBER2013–REVISED DECEMBER2014Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback7V INV OUTL1TLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 20149Parameter Measurement InformationTable 2.List of ComponentsREFERENCEDESCRIPTIONMANUFACTURERC1 4.7µF,Ceramic Capacitor,6.3V,X5R,size 0603,GRM188R60J475ME84Murata C210µF,Ceramic Capacitor,6.3V,X5R,size 0603,GRM188R60J106ME84Murata L1 2.2µH,Power Inductor,2.5A,size 4mmx4mm,LQH44PN2R2MP0Murata R1,R2Chip resistor,1%,size 0603Std.8Submit Documentation Feedback Copyright ©2013–2014,Texas Instruments IncorporatedPWMValley LS TLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 201410Detailed Description10.1OverviewThe TLV62565/6device family includes two high-efficiency synchronous step-down converters.Each device operates with an adaptive on-time control scheme,which is able to dynamically adjust the on-time duration based on the input voltage and output voltage so that it can achieve relative constant frequency operation.The device operates at typically 1.5-MHz frequency pulse width modulation (PWM)at moderate to heavy load currents.Based on the V IN /V OUT ratio,a simple circuit sets the required on time for the high-side MOSFET.It makes the switching frequency relatively constant regardless of the variation of input voltage,output voltage,and load current.At the beginning of each switching cycle,the high-side switch is turned on and the inductor current ramps up to a peak current that is defined by on time and inductance.In the second phase,once the on time expires,the high-side switch is turned off while the low-side switch is being turned on.The current through the inductor then decays until triggering the valley current limit determined by the output of the error amplifier.Once this occurs,the on timer is set to turn the high-side switch back on again and the cycle is repeated.The TLV62565/6device family offers excellent load transient response with a unique fast response constant on-time valley current mode.The switching frequency changes during load transition so that the output voltage comes back in regulation faster than a traditional fixed PWM control scheme.Figure 10shows the operation principles of the load transient response of the TLV62565/6.Internal loop compensation is integrated which simplifies the design process while minimizing the number of external components.At light load currents the device automatically operates in Power Save Mode with pulse frequency modulation (PFM).Figure 10.Operation in Load TransientCopyright ©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback 9V INPGGNDFBSWV INGNDFBENSWTLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 201410.2Functional Block DiagramsFigure 11.TLV62565Functional Block DiagramFigure 12.TLV62566Functional Block Diagram10Submit Documentation Feedback Copyright ©2013–2014,Texas Instruments IncorporatedOutput tTLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 201410.3Feature Description10.3.1Power Save ModeThe device integrates a Power Save Mode with PFM to improve efficiency at light load.In Power Save Mode,the device only switches when the output voltage trips below a set threshold voltage.It ramps up the output voltage with several pulses and stops switching when the output voltage is higher than the set threshold voltage.PFM is exited and PWM mode entered in case the output current can no longer be supported in Power Save Mode.The threshold of the PFM comparator is typically 0.9%higher than the normal reference voltage.Figure 13shows the details of PFM/PWM mode transition.Figure 13.Output Voltage in PFM/PWM Mode10.3.2Enabling/Disabling the DeviceThe device is enabled by setting the EN input to a logic HIGH.Accordingly,a logic LOW disables the device.If the device is enabled,the internal power stage starts switching and regulates the output voltage to the set point voltage.The EN input must be terminated and should not be left floating.10.3.3Soft StartAfter enabling the device,internal soft-start circuitry monotonically ramps up the output voltage which reaches nominal output voltage during a soft-start time of 250µs (typical).This avoids excessive inrush current and creates a smooth output voltage rise slope.It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance.If the output voltage is not reached within the soft-start time,such as in the case of a heavy load,the converter enters regular operation.The TLV62565/6are able to start into a pre-biased output capacitor.The converter starts with the applied bias voltage and ramps the output voltage to its nominal value.10.3.4Switch Current LimitThe switch current limit prevents the device from high inductor current and drawing excessive current from a battery or input voltage rail.Excessive current might occur with a heavy load or shorted output circuit condition.The TLV62565/6adopt valley current control by sensing the current of the low-side MOSFET.Once the low-side valley switch current limit is tripped,the low-side MOSFET is turned off and limits the inductor's valley current.The high-side current is also limited which is determined by the on time of the high-side MOSFET and inductor value calculated by Equation 1.For example,with 3.6V IN to 1.8V OUT and 2.2-µH specification,the peak current limit is approximately 1.97A with a typical valley current limit of 1.7A.Additionally,there is a secondary high-side current limit (typical 2A)to prevent the current from going too high,which is shown in Figure 14.Due to the internal propagation delay,the real current limit value might be higher than the static current limit in the electrical characteristics table.Copyright ©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback 11SWOUT L L IT VALLEY,LIM PEAK,LIMIT f D)(L V ΔI ΔI I I -´=+=1Inductortload currentlimit TLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 2014Feature Description (continued)Figure 14.Switch Current Limitwhere:•I PEAK,LIMIT is the high-side peak current limit •I VALLEY,LIMIT is the low-side valley current limit(1)10.3.5Power GoodThe TLV62566integrates a Power Good output going low when the output voltage is below its nominal value.The Power Good output stays high impedance once the output is above 95%of the regulated voltage and is low once the output voltage falls below typically 90%of the regulated voltage.The PG pin is an open drain output and is specified to sink typically up to 0.5mA.The Power Good output requires a pull-up resistor connected to any voltage lower than 5.5V.When the device is off due to UVLO or thermal shutdown,the PG pin is pulled to logic low.10.4Device Functional Modes10.4.1Under Voltage LockoutTo avoid mis-operation of the device at low input voltages,under voltage lockout is implemented that shuts down the device at voltages lower than V UVLO with V HYS_UVLO hysteresis.10.4.2Thermal ShutdownThe device enters thermal shutdown once the junction temperature exceeds typically T JSD .Once the device temperature falls below the threshold with hysteresis,the device returns to normal operation automatically.Power Good is pulled low when thermal protection is triggered.12Submit Documentation Feedback Copyright ©2013–2014,Texas Instruments IncorporatedVINVOUT1.2VL1TLV62565,TLV62566 SLVSBC1B–OCTOBER2013–REVISED DECEMBER2014 11Application and ImplementationNOTEInformation in the following applications sections is not part of the TI componentspecification,and TI does not warrant its accuracy or completeness.TI’s customers areresponsible for determining suitability of components for their purposes.Customers shouldvalidate and test their design implementation to confirm system functionality.11.1Application InformationThe TLV6256x devices are synchronous step-down converters optimized for small solution size and high efficiency.The devices integrate switches capable of delivering an output current up to1.5A.11.2Typical ApplicationTLV625652.7-V to5.5-V input,1.2-V output converter.Figure15.TLV625651.2-V Output Application11.2.1Design Requirements11.2.1.1Output Filter DesignThe inductor and output capacitor together provide a low-pass frequency filter.To simplify this process,Table3 outlines possible inductor and capacitor value combinations.Table3.Matrix of Output Capacitor and Inductor CombinationsC OUT[µF](2)(3)L[µH](1)4.710224710012.2+(4)+(4)+(4)4.7(1)Inductor tolerance and current de-rating is anticipated.The effective inductance can vary by+20%and-30%.(2)Capacitance tolerance and bias voltage de-rating is anticipated.The effective capacitance can vary by+20%and-50%.(3)For low output voltage applications(≤1.2V),more output capacitance is recommended(usually≥22µF)for smaller ripple.(4)Typical application configuration.'+'indicates recommended filter combinations.Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback13SWINOUT OUT L LMAX ,OUT MAX ,L f L V V 1V I 2II I ´-´=D D +=TLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 201411.2.1.2Inductor SelectionThe main parameters for inductor selection is inductor value and then saturation current of the inductor.To calculate the maximum inductor current under static load conditions,Equation 2is given:where:•I OUT,MAX is the maximum output current •ΔI L is the inductor current ripple •f SW is the switching frequency •L is the inductor value(2)It is recommended to choose a saturation current for the inductor that is approximately 20%to 30%higher than I L,MAX .In addition,DC resistance and size should also be taken into account when selecting an appropriate inductor.The recommended inductors are listed in Table 4.Table 4.List of Recommended InductorsINDUCTANCECURRENT RATINGDIMENSIONS DC RESISTANCETYPE MANUFACTURER[µH][mA]L x W x H [mm 3][m Ωtyp]2.225004x3.7x 1.6549LQH44PN2R2MP0Murata 2.230004x 4x 1.850NRS4018T2R2MDGJTaiyo Yuden11.2.1.3Input and Output Capacitor SelectionThe input capacitor is the low impedance energy source for the converter that helps provide stable operation.The closer the input capacitor is placed to the V IN and GND pins,the lower the switch ring.A low ESR multilayer ceramic capacitor is recommended for best filtering.For most applications,4.7-µF input capacitance is sufficient;a larger value reduces input voltage ripple.The architecture of the TLV62565/6allow use of tiny ceramic-type output capacitors with low equivalent series resistance (ESR).These capacitors provide low output voltage ripple and are thus recommended.To keep its resistance up to high frequencies and to achieve narrow capacitance variation with temperature,it is recommended to use X7R or X5R dielectric.The TLV62565/6are designed to operate with an output capacitance of 10µF to 47µF,as outlined in Table 3.14Submit Documentation Feedback Copyright ©2013–2014,Texas Instruments Incorporated)16.0(2)1(21-´=-´=V V R V VR R OUT FB OUT W ===k AV I V R FB FB 12056.02m ÷øöçèæ+´=÷øöçèæ+´=2116.0211R R V R R V V FB OUT TLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 201411.2.2Detailed Design Procedure 11.2.2.1Setting the Output VoltageAn external resistor divider is used to set output voltage.By selecting R1and R2,the output voltage is programmed to the desired value.When the output voltage is regulated,the typical voltage at the FB pin is V FB .Equation 3,Equation 4,and Equation 5can be used to calculate R1and R2.When sizing R2,in order to achieve low quiescent current and acceptable noise sensitivity,use a minimum of 5μA for the feedback current I FB .Larger currents through R2improve noise sensitivity and output voltage accuracy but increase current consumption.(3)(4)(5)11.2.2.2Loop StabilityThe first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:•Switching node,SW •Inductor current,I L•Output ripple voltage,V OUT(AC)These are the basic signals that need to be measured when evaluating a switching converter.When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations,the regulation loop may be unstable.This is often a result of board layout and/or L-C combination.Applications with the recommended L-C combinations in Table 3are designed for good loop stability as well as fast load transient response.As a next step in the evaluation of the regulation loop,the load transient response is illustrated.The TLV62565/6use a constant on time with valley current mode control,so the on time of the high-side MOSFET is relatively consistent from cycle to cycle when a load transient occurs.Whereas the off time adjusts dynamically in accordance with the instantaneous load change and brings V OUT back to the regulated value.During recovery time,V OUT can be monitored for settling time,overshoot,or ringing which helps judge the stability of the converter.Without any ringing,the loop usually has more than 45°of phase margin.Copyright ©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback 15oA/div0.1 V/div oA/divinductor V V = 1.8 VIN O = 3.6 V L=2.2 uH, C =10 uF Load: 1.3A to 0.3Ao 4.0 µs/divG008EN 1 V/div V V = 1.8 VIN O = 3.6 V 400 µs/divG004SW 2 V/div V V = 1.8 V/10mAIN O = 3.6 V10 µs/divG003oA/div0.1 V/div oA/divinductor V V = 1.8 VIN O = 3.6 V L=2.2 uH,C =10 uF Load: 0.3A to 1.3Ao 4.0 µs/divG007V V = 1.8 VIN O = 3.6 V 0.4 µs/divG001SW 2 V/div V V = 1.8 V/100mAIN O = 3.6 V2.0 µs/divG002TLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 201411.2.3Application Performance CurvesFigure 16.Typical Application (PWM Mode)Figure 17.Typical Application (PFM Mode)Figure 18.Typical Application (PFM Mode)Figure 19.Load TransientFigure 20.Load Transient Figure 21.Start Up16Submit Documentation Feedback Copyright ©2013–2014,Texas Instruments IncorporatedPG 1 V/div1 V/div o 1A/div inductor V V = 1.8 V IN O = 3.6 V Load= 0A400 µs/divG005IN 5 V/divA/divV V = 1.8 VIN O = 3.6 V 2.0 µs/divG006TLV62565,TLV62566SLVSBC1B –OCTOBER 2013–REVISED DECEMBER 2014Figure 22.Start Up (Power Good)Figure 23.Short Circuit Protection12Power Supply RecommendationsThe power supply to the TLV62565and TLV62566needs to have a current rating according to the supply voltage,output voltage and output current of the TLV62565and TLV62566.Copyright ©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback 17TLV62565,TLV62566SLVSBC1B–OCTOBER2013–REVISED 13Layout13.1Layout GuidelinesThe PCB layout is an important step to maintain the high performance of the TLV62565devices.•The input/output capacitors and the inductor should be placed as close as possible to the IC.•This keeps the traces short.Routing these traces direct and wide results in low trace resistance and low parasitic inductance.•A common power GND should be used.•The low side of the input and output capacitors must be connected properly to the power GND to avoid a GND potential shift.•The sense traces connected to FB is a signal trace.•Special care should be taken to avoid noise being induced.By a direct routing,parasitic inductance can be kept small.•GND layers might be used for shielding.•Keep these traces away from SW nodes.13.2Note:13.3typically requires special coupling,airflow, convection dissipation limits of a givenTwo basic approaches for enhancing thermal performance are listed below:•Improving the power dissipation capability of the PCB design•Introducing airflow in the systemFor more details on how to use the thermal parameters,see the application notes:Thermal Characteristics Application Notes SZZA017and SPRA953.18Submit Documentation Feedback Copyright©2013–2014,Texas Instruments IncorporatedTLV62565,TLV62566 SLVSBC1B–OCTOBER2013–REVISED DECEMBER201414Device and Documentation Support14.1Device Support14.1.1Third-Party Products DisclaimerTI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY,REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES,EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.14.2Documentation Support14.2.1Related DocumentationSemiconductor and IC Package Thermal Metrics Application Report(SPRA953)Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report (SZZA017)14.3Related LinksThe table below lists quick access links.Categories include technical documents,support and community resources,tools and software,and quick access to sample or buy.Table5.Related LinksTECHNICAL TOOLS&SUPPORT& PARTS PRODUCT FOLDER SAMPLE&BUYDOCUMENTS SOFTWARE COMMUNITY TLV62565Click here Click here Click here Click here Click here TLV62566Click here Click here Click here Click here Click here 14.4TrademarksAll trademarks are the property of their respective owners.14.5Electrostatic Discharge CautionThese devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.14.6GlossarySLYZ022—TI Glossary.This glossary lists and explains terms,acronyms,and definitions.15Mechanical,Packaging,and Orderable InformationThe following pages include mechanical,packaging,and orderable information.This information is the most current data available for the designated devices.This data is subject to change without notice and revision of this document.For browser-based versions of this data sheet,refer to the left-hand navigation.Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback19。
