SATA20硬盘数据加解密系统设计与实现

SATA20硬盘数据加解密系统设计与实现 AB STRACT Information security has become an important

issue in 2 1 th

century,especially

computer information security,arousing more and more attentation．

Hard disks with SATA2．0 interface possess higher transmission rate，reliable，

suppoting NCQ，port multiplexing and interleaving start-up merits to enable them instead of IDE Hard disks to become a main stream，being the carrier of information，it

is extensively

accepted by both enterprise class

and individual class

users．

In this thesis firstly introduces the background of research，and then to analyse

SATA2．0 protocol and ATA command transmission protocol，the focal points are the command

and data tranmission protocol that releated with our design，and diffculties and

problems

of the design．And the followiing expounding the whole architecture of design and analysing

functions of each module．And then it gives detailed explaination of data path design and the solutions to those difficulties problems，at the same time，it

gives the verified results，

and to analyse simply．Next，the thesis explains

the eneryption

and decryption

arithmetic which

are used for hard disk，this part we use a configurable

arithmetic based on CBC

and ECB

mode to complete the e：ncryption and deeryption successfully．And at the last，it gives

the testing platform and testing solutions to whole design，and give analysis to the results．

This SATA 2．0 hard disk encryption and decryption circuit has been tested in Virtex 5 XC5VLX50T FPGA of XILINX Corporation．The system works on a high

performance

and meets all requirements of the design．And it Can transplant to other

platform and

call configure varied encryption and decryption arithmetic，it possess

research meaning and economy meaning．

Keywords：Serial ATA，computer security,hardware encryption

arithmetic

II 图目录 图目录 图2．1 SATA体系结构 6 图2．2 S朋阪物理层功能框图 ．．7 图2—3 8b／1

0b编解码过程 ．12

图2-4 PIO读命令协议执行步骤 ．．1

5

图2．5 PIO写命令协议执行过程 一1

6

图2-6 DMA读命令协议执行过程 1 7

图2．7 DMA写命令协议执行过程 1 8

图2—8 Set Device Bits FIS ．．21 图2-9 NCQ队列命令执行过程 24

图3．1加解密过程 26 图3—2非对称加密算法 27 图3．3短块填充 ．28 图3．4状态矩阵 29 图3．5 AES加密算法框图 ．30 图3-6字节替换 31 图3．7行移位 ．．32 图3．8轮密钥加 33 图3-9轮密钥产生1 ．34 图3。10轮密钥产生2 ．34 图3．11轮密钥产生3 34 图3．12 Rcon矩阵内容 。34

图3．13基于ECB模式AES加密算法 35 图3．14基于CBC模式AES加解密算法 ．．36 图4—1逻辑框图 38 图4．2系统框图 ．．38 图4．3密钥加载流向 ．．41 图4-4非加密数据路由 41 图4。5非解密数据路由 ．．42

VII 图目录 4．6加密数据路由 43 4．7解密数据路由 ．．44

5．1 P1U模块设计框图 45 5．2加扰器实现框图 ～46 5．3加扰时序 ．．46 5．4加扰器仿真结果．．二 ．47 5．5 PIU仿真波形 47 5—6提取帧内数据时序 49 5．7出现CONT原语 ．50 5．8 CONT原语前插入ALIGN原语 ．50 5．9 CONT后插入ALIGN原语 50 5．10 ALIGN插入位置 51 5．11 EOF原语前插入ALIGN数据 ．52 5．12 SOF原语后无ALIGN插入 ．52 5．13 SoF后插入ALIGN原语 ．．53 5．14解扰模块 53 5．15 CRC实现结构图 54 5。16 CRC校验正确 54 5．17 CRC校验错误 55 5．1 8 CRC仿真波形 55 5—19数据、原语判断测试用例 56 5—20 ALIGN原语测试用例 。56

5．21 CRC结果判断测试用例 57 5．22 EOF前未插入ALIGN原语时去除CRC ．58

5．23 EOF前插入ALIGN原语时去除CRC 59 5．24加解密指示信号判断时序 61 5．25 ALIGN随机插入时加解密指示信号判断时序 ．．62 5．26 NCQ命令检测时序1 ．63 5—27 NCQ命令检测时序2 ．63 5．28 NCQ命令协议下数据加解密指示信号判断 64 5．29 Routing功能实现框图 65 图图图图图图图图图图图图图图图图图图图图图图图图图图图图图图图图 5—30 CRC Gen

B寸序 65

VⅢ 图目录 图5．3 1 FIFO内部逻辑框图 66 图5．32 Test

casel仿真结果 66

图5．33 Test

case2仿真结果 ．．67

图5．34 Test

case3仿真结果 ．．67

图5．35 Test

case4仿真结果 ．．68

图5．36 Test

case5仿真结果 ．．68

图5．37 Test case6仿真结果 ．．69 图5．38帧重组时序l ．71 图5—39扰码数据和帧内数据区分 71 图5．40帧重组时序2 一72 图5．4 1扰码器框图 ．73 图5．42原语发送测试用例 73 图5-43定时插入ALIGN原语测试用例(a) ．74 图5．44定时插入ALIGN原语测试用例(b) 74 图5．45 CONT原语后扰码产生测试用例 ．75 图5．46未采用ALIGN原语浮现总线内容 ．75 图5．47采用ALIGN原语浮现总线内容 ．75 图6．1可配置AES算法实现框图 78 图6．2可配置AES解密算法实现框图 79 图6．3 ECB模式AES算法验证 80 图6．4 Test

easel仿真结果 80

图6．5 Test

case2仿真结果 8l

图6-6比较结果 81 图6．7 CBC模式AES算法验证 j 82 图6—8比较结果 82 图6-9算法资源占用情况 ．83 图6．10最大允许时钟频率 83 图6．11测试模型 84 图6．12 ML505实物图 85 图6．13 FPGA芯片 86 图6—14硬件测试平台 86 图6．15系统正确安装测试 ．88

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