MAX5841MEUB中文资料

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General DescriptionThe MAX5841 is a quad, 10-bit voltage output, digital-to-analog converter (DAC) with an I 2C™-compatible, 2-wire interface that operates at clock rates up to 400kHz. The device operates from a single 2.7V to 5.5V supply and draws only 230µA at V DD = 3.6V. A power-down mode decreases current consumption to less than 1µA. The MAX5841 features three software-selec-table power-down output impedances: 100k Ω, 1k Ω,and high impedance. Other features include internal precision Rail-to-Rail ®output buffers and a power-on reset (POR) circuit that powers up the DAC in the 100k Ωpower-down mode.The MAX5841 features a double-buffered I 2C-compati-ble serial interface that allows multiple devices to share a single bus. All logic inputs are CMOS-logic compati-ble and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5841 minimizes digital noise feedthrough by disconnecting the clock (SCL) signal from the rest of the device when an address mismatch is detected.The MAX5841 is specified over the extended tempera-ture range of -40°C to +85°C and is available in a miniature 10-pin µMAX package. Refer to the MAX5842data sheet for the 12-bit version.ApplicationsDigital Gain and Offset Adjustments Programmable Voltage and Current Sources Programmable Attenuation VCO/Varactor Diode Control Low-Cost Instrumentation Battery-Powered Equipment ATEFeatureso Ultra-Low Supply Current230µA at V DD = 3.6V 280µA at V DD = 5.5Vo 300nA Low-Power Power-Down Mode o Single 2.7V to 5.5V Supply Voltage o Fast 400kHz I 2C-Compatible 2-Wire Serial Interface o Schmitt-Trigger Inputs for Direct Interfacing to Optocouplers o Rail-to-Rail Output Buffer Amplifierso Three Software-Selectable Power-Down Output Impedances100k Ω, 1k Ω, and High Impedance o Read-Back Mode for Bus and Data Checking o Power-On Reset to Zero o 10-Pin µMAX PackageMAX5841Quad, 10-Bit, Low-Power, 2-Wire, SerialVoltage-Output DAC________________________________________________________________Maxim Integrated Products 1Pin ConfigurationOrdering InformationTypical Operating Circuit19-1777; Rev 0; 1/02For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .I 2C is a trademark of Philips Corp.M A X 5841Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(V= +2.7V to +5.5V, GND = 0, V = V , R = 5k Ω, C = 200pF, T = T to T , unless otherwise noted. Typical values are Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V DD , SCL, SDA to GND............................................-0.3V to +6V OUT_, REF, ADD to GND..............................-0.3V to V DD + 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (T A = +70°C)10-Pin µMAX (derate 5.6mW above +70°C)................444mWOperating Temperature Range ...........................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Maximum Junction Temperature.....................................+150°C Lead Temperature (soldering 10s)..................................+300°CMAX5841Quad, 10-Bit, Low-Power, 2-Wire, SerialVoltage-Output DAC_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS (continued)(V DD = +2.7V to +5.5V, GND = 0, V REF = V DD , R L = 5k Ω, C L = 200pF, T A = T MIN to T MAX , unless otherwise noted. Typical values areM A X 5841Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 4_______________________________________________________________________________________INTEGRAL NONLINEARITYvs. INPUT CODEM A X 5841 t o c 01INPUT CODEI N L (L S B )768512256-0.75-0.50-0.2500.250.500.751.00-1.001024INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGEM A X 5841 t o c 02SUPPLY VOLTAGE (V)I N L (L S B )4.84.13.40.250.500.751.001.2502.75.5INTEGRAL NONLINEARITY vs. TEMPERATUREM A X 5841 t o c 03TEMPERATURE (°C)I N L (L S B )603510-150.250.500.751.001.250-4085DIFFERENTIAL NONLINEARITYvs. INPUT CODEM A X 5841 t o c 04INPUT CODED N L (L S B )768512256-0.75-0.50-0.2500.250.500.751.00-1.001024DIFFERENTIAL NONLINEARITYvs. SUPPLY VOLTAGEM A X 5841 t o c 05SUPPLY VOLTAGE (V)D N L (L S B )4.84.13.4-0.4-0.3-0.2-0.10-0.52.75.5DIFFERENTIAL NONLINEARITYvs. TEMPERATUREM AX 5841 t o c 06TEMPERATURE (°C)D N L (L S B )603510-15-0.4-0.3-0.2-0.1-0.5-4085Typical Operating Characteristics(V DD = +5V, R L = 5k Ω, T A = +25°C.)ELECTRICAL CHARACTERISTICS (continued)(V = +2.7V to +5.5V, GND = 0, V = V , R = 5k Ω, C = 200pF, T = T to T , unless otherwise noted. Typical values are Note 1:All devices are 100% production tested a at T A = +25°C and are guaranteed by design for T A = T MIN to T MAX .Note 2:Static specifications are tested with the output unloaded.Note 3:Linearity is guaranteed from codes 29 to 995.Note 4:Offset and gain error limit the FSR.Note 5:Guaranteed by design. Not production tested.MAX5841Quad, 10-Bit, Low-Power, 2-Wire, SerialVoltage-Output DAC_______________________________________________________________________________________5ZERO-CODE ERROR vs. SUPPLY VOLTAGEM A X 5841 t o c 07SUPPLY VOLTAGE (V)Z E R O -C O D E E R R O R (m V )4.84.13.424681002.75.5NO LOADZERO-CODE ERROR vs. TEMPERATUREM A X 5841 t o c 08TEMPERATURE (°C)Z E R O -C O D E E R R O R (m V )603510-152468100-4085NO LOADGAIN ERROR vs. SUPPLY VOLTAGEM A X 5841 t o c 09SUPPLY VOLTAGE (V)G A I N E R R O R (%F S R )4.84.13.4-0.4-0.8-1.2-1.6-2.02.75.5NO LOADGAIN ERROR vs. TEMPERATUREM A X 5841 t o c 10TEMPERATURE (°C)G A I N E R R O R (%F S R )603510-15-0.4-0.8-1.2-1.6-2.00-4085NO LOADDAC OUTPUT VOLTAGEvs. OUTPUT SOURCE CURRENT (NOTE 6)OUTPUT SOURCE CURRENT (mA)D A C O U T P U T V O L T A GE (V )8642123456010DAC OUTPUT VOLTAGEvs. OUTPUT SINK CURRENT (NOTE 6)OUTPUT SINK CURRENT (mA)D A C O U T P U T V O L T A GE (V )86420.51.01.52.02.510SUPPLY CURRENT vs. INPUT CODEM A X 5841 t o c 13INPUT CODES U P P L Y C U R R E N T (µA )8206154102052602803003202401024SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (µA )603510-15260280300320240-4085SUPPLY CURRENT vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (µA )4.84.13.42602803003202402.75.5Typical Operating Characteristics (continued)(V DD = +5V, R L = 5k Ω, T A = +25°C.)M A X 5841Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 6_______________________________________________________________________________________POWER-DOWN SUPPLY CURRENTvs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)P O WE R -D O W N S UP P L YC U R R E N T (nA )4.84.13.410020030040050002.75.5POWER-UP GLITCHMAX5841 toc17100µs/divV DDOUT_5V10mV/divEXITING SHUTDOWN2µs/divOUT_500mV/div MAJOR CARRY TRANSITION(POSITIVE)2µs/divOUT_5mV/divMAJOR CARRY TRANSITION(NEGATIVE)2µs/divOUT_5mV/div Typical Operating Characteristics (continued)(V DD = +5V, R L = 5k Ω, T A = +25°C.)SETTLING TIME (POSITIVE)2µs/divOUT_500mV/divC LOAD = 200pFCODE = 100 hex TO 300 hexMAX5841Quad, 10-Bit, Low-Power, 2-Wire, SerialVoltage-Output DAC_______________________________________________________________________________________7SETTLING TIME (NEGATIVE)2µs/divOUT_500mV/divDIGITAL FEEDTHROUGH40µs/divOUT_2mV/divSCL 2mV/divCROSSTALKMAX5841 toc244µs/divV OUTB1mV/divV OUTA 2V/divTypical Operating Characteristics (continued)(V DD = +5V, R L = 5k Ω, T A = +25°C.)Note 6:The ability to drive loads less than 5k Ωis not implied.M A X 5841Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 8_______________________________________________________________________________________Detailed DescriptionThe MAX5841 is a quad, 10-bit, voltage-output DAC with an I 2C/SMBus-compatible 2-wire interface. The device consists of a serial interface, power-down cir-cuitry, four input and DAC registers, four 10-bit resistor string DACs, four unity-gain output buffers, and output resistor networks. The serial interface decodes the address and control bits, routing the data to the proper input or DAC register. Data can be directly written to the DAC register, immediately updating the device out-put, or can be written to the input register without changing the DAC output. Both registers retain data as long as the device is powered.DAC OperationThe MAX5841 uses a segmented resistor string DAC architecture, which saves power in the overall system and guarantees output monotonicity. The MAX5841’s input coding is straight binary, with the output voltage given by the following equation:where N = 10 (bits), and D = the decimal value of the input code (0 to 1023).Output BufferThe MAX5841 analog outputs are buffered by preci-sion, unity-gain followers that slew 0.5V/µs. Each buffer output swings rail-to-rail, and is capable of driving 5k Ωin parallel with 200pF. The output settles to ±0.5LSB within 4µs.Power-On ResetThe MAX5841 features an internal POR circuit that ini-tializes the device upon power-up. The DAC registerswith the output buffers disabled and the outputs pulled to GND through the 100k Ωtermination resistor.Following power-up, a wake-up command must be initi-ated before any conversions are performed.Power-Down ModesThe MAX5841 has three software-controlled low-power power-down modes. All three modes disable the output buffers and disconnect the DAC resistor strings from REF, reducing supply current draw to 1µA and the ref-erence current draw to less than 1µA. I n power-down mode 0, the device output is high impedance. I n power-down mode 1, the device output is internally pulled to GND by a 1k Ωtermination resistor. In power-down mode 2, the device output is internally pulled to GND by a 100k Ωtermination resistor. Table 1 shows the power-down mode command words.Upon wake-up, the DAC output is restored to its previ-ous value. Data is retained in the input and DAC regis-ters during power-down mode.Digital InterfaceThe MAX5841 features an I 2C/SMBus-compatible 2-wire interface consisting of a serial data line (SDA)and a serial clock line (SCL). The MAX5841 is SMBus compatible within the range of V DD = 2.7V to 3.6V. SDA and SCL facilitate bidirectional communication between the MAX5841 and the master at rates up to 400kHz.Figure 1 shows the 2-wire interface timing diagram. The MAX5841 is a transmit/receive slave-only device, rely-ing upon a master to generate a clock signal. The mas-ter (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer.A master device communicates to the MAX5841 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed-MAX5841Quad, 10-Bit, Low-Power, 2-Wire, SerialVoltage-Output DAC_______________________________________________________________________________________9by a START (S) or REPEATED START (S r ) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.The MAX5841 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor to generate, a logic high voltage (see Typical Operating Circuit ). Series resistors R S are optional. These series resistors protect the input stages of the MAX5841 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.Bit TransferOne data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see STAR T andSTOP Conditions ). Both SDA and SCL idle high when the I 2C bus is not busy.START and STOP ConditionsWhen the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issu-ing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high (Figure 2). A START condition from the master signals the beginning of a transmission to the MAX5841. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see Acknowledge Bit (ACK)). The STOP condition frees the bus. I f a repeated START condition (S r ) is generated instead of a STOP condition, the bus remains active.When a STOP condition or incorrect address is detect-ed, the MAX5841 internally disconnects SCL from the serial interface until the next START condition, minimiz-ing digital noise and feedthrough.Early STOP ConditionsThe MAX5841 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I 2C format; at least one clock pulse must separate any START and STOP conditions.Repeated START ConditionsA REPEATED START (S r ) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. S r may also be used when the bus master is writing to several I 2C devices and does not want to relinquish control of the bus. The MAX5841 ser-ial interface supports continuous write operations with or without an S r condition separating them. ContinuousM A X 5841Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 10read operations require S r conditions because of the change in direction of data flow.Acknowledge Bit (ACK)The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The MAX5841 generates an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data,the MAX5841 waits for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuc-cessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. I n the event of an unsuccessful data transfer, the bus master should reattempt communica-tion at a later time.Slave AddressA bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address (Figure 4). When idle, the MAX5841waits for a START condition followed by its slaveaddress. The serial interface compares each address value bit by bit, allowing the interface to power down immediately if an incorrect address is detected. The LSB of the address word is the Read/Write (R/W ) bit.R/W indicates whether the master is writing to or read-ing from the MAX5841 (R/W = 0 selects the write condi-tion, R/W = 1 selects the read condition). After receiving the proper address, the MAX5841 issues an ACK by pulling SDA low for one clock cycle.The MAX5841 has four different factory/user-pro-grammed addresses (Table 2). Address bits A6through A1 are preset, while A0 is controlled by ADD.Connecting ADD to GND sets A0 = 0. Connecting ADD to VDD sets A0 = 1. This feature allows up to four MAX5841s to share the same bus.In write mode (R/W = 0), data that follows the address byte controls the MAX5841 (Figure 5). Bits C3–C0 con-figure the MAX5841 (Table 3). Bits D9–D0 are DAC data. Bits S0 and S1 are sub-bits and are always zero.Input and DAC registers update on the falling edge of SCL during the acknowledge bit. Should the write cycle be prematurely aborted, data is not updated and the write cycle must be repeated. Figure 6 shows two example write data sequences.Extended Command ModeThe MAX5841 features an extended command mode that is accessed by setting C3–C0 = 1 and D9–D6 = 0.The next data byte writes to the shutdown registers (Figure 7). Setting bits A, B, C, or D to 1 sets that DACFigure 2. START and STOP ConditionsFigure 3. Early STOP ConditionsMAX5841Quad, 10-Bit, Low-Power, 2-Wire, SerialVoltage-Output DAC______________________________________________________________________________________11to the selected power-down mode based on the states of PD0 and PD1 (Table 1). Any combination of the four DACs can be controlled with a single write sequence.Read Data FormatIn read mode (R/W = 1), the MAX5841 writes the con-tents of the DAC register to the bus. The direction of data flow reverses following the address acknowledge by the MAX5841. The device transmits the first byte of data, waits for the master to acknowledge, then trans-mits the second byte. Figure 8 shows an example read data sequence.I 2C CompatibilityThe MAX5841 is compatible with existing I 2C systems.SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The Typical Operating Circuit shows a typ-ical I 2C application. The communication protocol sup-ports the standard I 2C 8-bit communications. The general call address is ignored. The MAX5841 address is compatible with the 7-bit I 2C addressing protocol only. No 10-bit address formats are supported.Digital Feedthrough SuppressionWhen the MAX5841 detects an address mismatch, the serial interface disconnects the SCL signal from the core circuitry. This minimizes digital feedthrough caused by the SCL signal on a static output. The serial interface reconnects the SCL signal once a valid START condition is detected.Applications InformationDigital Inputs and Interface LogicThe MAX5841 2-wire digital interface is I 2C/SMBus compatible. The two digital inputs (SCL and SDA) load the digital input serially into the DAC. Schmitt-trigger buffered inputs allow slow-transition interfaces such as optocouplers to interface directly to the device. The digital inputs are compatible with CMOS logic levels.Power-Supply Bypassing and GroundManagementCareful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the power-supply ground is short and low impedance. Bypass V DD with a 0.1µF capacitor to ground as close to the device as possible.Chip InformationTRANSISTOR COUNT: 17,213PROCESS: BiCMOSFigure 6. Example Write Command SequencesM A X 5841Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 12______________________________________________________________________________________MAX5841Quad, 10-Bit, Low-Power, 2-Wire, SerialVoltage-Output DAC______________________________________________________________________________________13Table 3. Command Byte Definitions (continued)Figure 8. Example Read Word Data SequenceM A X 5841Quad, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 14______________________________________________________________________________________Functional DiagramMAX5841Quad, 10-Bit, Low-Power, 2-Wire, SerialVoltage-Output DACMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________15©2002 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.Package Information。

MAX3490EESA+中文资料

General DescriptionDevices in the MAX3483E family (MAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E) are ±15kV ESD-protected, +3.3V, low-power transceivers for RS-485 and RS-422 communications. Each device con-tains one driver and one receiver. The MAX3483E and MAX3488E feature slew-rate-limited drivers that minimize EMI and reduce reflections caused by improperly termi-nated cables, allowing error-free data transmission at data rates up to 250kbps. The partially slew-rate-limited MAX3486E transmits up to 2.5Mbps. The MAX3485E,MAX3490E, and MAX3491E transmit at up to 12Mbps.All devices feature enhanced electrostatic discharge (ESD) protection. All transmitter outputs and receiver inputs are protected to ±15kV using IEC 1000-4-2 Air-Gap Discharge, ±8kV using IEC 1000-4-2 Contact Discharge, and ±15kV using the Human Body Model.Drivers are short-circuit current limited and are protect-ed against excessive power dissipation by thermal shutdown circuitry that places the driver outputs into a high-impedance state. The receiver input has a fail-safe feature that guarantees a logic-high output if both inputs are open circuit.The MAX3488E, MAX3490E, and MAX3491E feature full-duplex communication, while the MAX3483E,MAX3485E, and MAX3486E are designed for half-duplex communication.ApplicationsTelecommunicationsIndustrial-Control Local Area Networks Transceivers for EMI-Sensitive Applications Integrated Services Digital Networks Packet SwitchingFeatureso ESD Protection for RS-485 I/O Pins±15kV—Human Body Model±8kV—IEC 1000-4-2, Contact Discharge ±15kV—IEC 1000-4-2, Air-Gap Discharge o Operate from a Single +3.3V Supply—No Charge Pump Required o Interoperable with +5V Logic o Guaranteed 12Mbps Data Rate (MAX3485E/MAX3490E/MAX3491E)o Slew-Rate Limited for Errorless Data Transmission (MAX3483E/MAX3488E) o 2nA Low-Current Shutdown Mode(MAX3483E/MAX3485E/MAX3486E/MAX3491E)o -7V to +12V Common-Mode Input Voltage Range o Full-Duplex and Half-Duplex Versions Available o Industry-Standard 75176 Pinout (MAX3483E/MAX3485E/MAX3486E)o Current-Limiting and Thermal Shutdown for Driver Overload ProtectionMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers________________________________________________________________Maxim Integrated Products119-1474; Rev 0; 4/99Selector GuideOrdering InformationOrdering Information continued at end of data sheet.For free samples & the latest literature: , or phone 1-800-998-8800.For small orders, phone 1-800-835-8769.M A X 3483E /M A X 3485E /M A X 3486E /M A X 3488E /M A X 3490E /M A X 3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceiversABSOLUTE MAXIMUM RATINGSDC ELECTRICAL CHARACTERISTICS(V = +3.3V ±0.3V, T = T to T , unless otherwise noted. Typical values are at T = +25°C.)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Supply Voltage (V CC ).............................................................+7V Control Input Voltage (RE , DE).................................-0.3V to +7V Driver Input Voltage (DI)...........................................-0.3V to +7V Driver Output Voltage (A, B, Y, Z).......................-7.5V to +12.5V Receiver Input Voltage (A, B)..............................-7.5V to +12.5V Receiver Output Voltage (RO)....................-0.3V to (V CC + 0.3V)Continuous Power Dissipation (T A = +70°C)8-Pin SO (derate 5.88mW/°C above +70°C)..................471mW 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C).....727mW14-Pin SO (derate 8.33mW/°C above +70°C)................667mW 14-Pin Plastic DIP (derate 10mW/°C above +70°C)......800mW Operating Temperature RangesMAX34_ _ EC_ _...................................................0°C to +70°C MAX34_ _ EE_ _.................................................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10sec).............................+300°CMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceiversDC ELECTRICAL CHARACTERISTICS (continued)(V CC = +3.3V ±0.3V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)DRIVER SWITCHING CHARACTERISTICS—MAX3485E/MAX3490E/MAX3491E(V = +3.3V, T = +25°C.)DRIVER SWITCHING CHARACTERISTICS—MAX3486E(V = +3.3V, T = +25°C.)*MAX3488E and MAX3491E will be compliant to ±8kV per IEC 1000-4-2 Contact Discharge by September 1999.M A X 3483E /M A X 3485E /M A X 3486E /M A X 3488E /M A X 3490E /M A X 3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers4_______________________________________________________________________________________DRIVER SWITCHING CHARACTERISTICS—MAX3483E/MAX3488E(V CC = +3.3V, T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICS(V CC = +3.3V, T A = +25°C.)Note 1:∆V OD and ∆V OC are the changes in V OD and V OC , respectively, when the DI input changes state.Note 2:Measured on |t PLH (Y) - t PHL (Y)|and |t PLH (Z) - t PHL (Z)|.Note 3:The transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80ns, thedevices are guaranteed not to enter shutdown. If the inputs are in this state for at least 300ns, the devices are guaranteed to have entered shutdown. See Low-Power Shutdown Mode section.MAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers_______________________________________________________________________________________5Typical Operating Characteristics(V CC = +3.3V, T A = +25°C, unless otherwise noted.)252015105000.51.01.52.02.53.53.0OUTPUT CURRENT vs.RECEIVER OUTPUT LOW VOLTAGEM A X 3483E -01OUTPUT LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )-20-18-16-14-12-10-8-6-4-2000.51.01.52.02.53.53.0OUTPUT CURRENT vs.RECEIVER OUTPUT HIGH VOLTAGEM A X 3483E -02OUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )3.003.053.103.153.203.253.30-40-20020406010080RECEIVER OUTPUT HIGH VOLTAGEvs. TEMPERATURETEMPERATURE (°C)O U T P U T H I G H V O L T A G E (V )00.10.20.30.40.50.60.70.8-40-2020406010080RECEIVER OUTPUT LOW VOLTAGEvs. TEMPERATURETEMPERATURE (°C)O U T P U T L O W V O L T A G E (V )2505075100125150175024681012OUTPUT CURRENT vs.DRIVER OUTPUT LOW VOLTAGEM A X 3483E -07OUTPUT LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )100908070605040302010000.5 1.0 1.5 2.0 2.5 3.53.0DRIVER OUTPUT CURRENT vs.DIFFERENTIAL OUTPUT VOLTAGEM A X 3483E -05DIFFERENTIAL OUTPUT VOLTAGE (V)O U T P U T C U R R E N T (m A )1.61.71.81.92.02.12.22.32.42.62.5-40-20020406010080DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURETEMPERATURE (°C)D I F FE R E N T I A L O U T P U T V O L T A G E (V )-100-80-60-40-20543210-7-6-3-4-5-2-1OUTPUT CURRENT vs.DRIVER OUTPUT HIGH VOLTAGEM A X 3483E -08OUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )M A X 3483E /M A X 3485E /M A X 3486E /M A X 3488E /M A X 3490E /M A X 3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers0.80.70.91.01.11.2-40-2020406010080SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (m A )Typical Operating Characteristics (continued)(V CC = +3.3V, T A = +25°C, unless otherwise noted.)0102030405060708010090-40-2020406010080SHUTDOWN CURRENT vs. TEMPERATUREM A X 3483E -10TEMPERATURE (°C)S H U T D O W N C U R R E N T (n A )Pin DescriptionMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers_______________________________________________________________________________________7Figure 2. MAX3488E/MAX3490E Pin Configuration and Typical Operating CircuitFigure 3. MAX3491E Pin Configuration and Typical Operating CircuitFigure 1. MAX3483E/MAX3485E/MAX3486E Pin Configuration and Typical Operating CircuitM A X 3483E /M A X 3485E /M A X 3486E /M A X 3488E /M A X 3490E /M A X 3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers8_______________________________________________________________________________________Figure 4. Driver V OD and V OC Figure 7. Driver Differential Output Delay and Transition TimesFigure 6. Receiver V OH and V OLFigure 5. Driver V OD with Varying Common-Mode VoltageMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers_______________________________________________________________________________________9Figure 8. Driver Propagation TimesFigure 9. Driver Enable and Disable Times (t PZH , t PSH , t PHZ )Figure 10. Driver Enable and Disable Times (t PZL , t PSL , t PLZ )M A X 3483E /M A X 3485E /M A X 3486E /M A X 3488E /M A X 3490E /M A X 3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers10______________________________________________________________________________________Figure 11. Receiver Propagation DelayFigure 12. Receiver Enable and Disable TimesNote 4: The input pulse is supplied by a generator with the following characteristics: f = 250kHz, 50% duty cycle, t r ≤6.0ns, Z O = 50Ω.Note 5: C L includes probe and stray capacitance._____________________Function TablesDevices with Receiver/Driver Enable(MAX3483E/MAX3485E/MAX3486E/MAX3491E)Table 1. Transmitting* B and A outputs are Z and Y, respectively, for full-duplex part (MAX3491E).X = Don’t care; High-Z = High impedanceTable 2. Receiving* DE is a “don’t care” (x) for the full-duplex part (MAX3491E).X = Don’t care; High-Z = High impedanceDevices without Receiver/Driver Enable(MAX3488E/MAX3490E)Table 3. TransmittingTable 4. Receiving___________Applications InformationThe MAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E are low-power transceivers for RS-485 and RS-422 communications. The MAX3483E and MAX3488E can transmit and receive at data rates up to 250kbps, the MAX3486E at up to 2.5Mbps, and the MAX3485E/MAX3490E/MAX3491E at up to 12Mbps. The MAX3488E/MAX3490E/MAX3491E are full-duplex trans-ceivers, while the MAX3483E/MAX3485E/MAX3486E are half-duplex. Driver Enable (DE) and Receiver Enable (RE ) pins are included on the MAX3483E/MAX3485E/MAX3486E/MAX3491E. When disabled, the driver and receiver outputs are high impedance.Reduced EMI and Reflections (MAX3483E/MAX3486E/MAX3488E)The MAX3483E/MAX3488E are slew-rate limited, mini-mizing EMI and reducing reflections caused by improp-erly terminated cables. Figure 13 shows the driver output waveform of a MAX3485E/MAX3490E/MAX3491E transmitting a 125kHz signal, as well as the Fourier analysis of that waveform. High-frequency harmonics with large amplitudes are evident. Figure 14 shows the same information, but for the slew-rate-limited MAX3483E/MAX3488E transmitting the same signal. The high-frequency harmonics have much lower amplitudes,and the potential for EMI is significantly reduced.Low-Power Shutdown Mode(MAX3483E/MAX3485E/MAX3486E/MAX3491E)A low-power shutdown mode is initiated by bringing both RE high and DE low. The devices will not shut down unless both the driver and receiver are disabled (high impedance). In shutdown, the devices typically draw only 2nA of supply current.For these devices, the t PSH and t PSL enable times assume the part was in the low-power shutdown mode;the t PZH and t PZL enable times assume the receiver or driver was disabled, but the part was not shut down.MAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers______________________________________________________________________________________11INPUTS OUTPUT A, B RO ≥+0.2V 1≤-0.2V 0Inputs Open1INPUT OUTPUTS DI Z Y 101015MHz 500kHz/div 05MHz500kHz/div Figure 13. Driver Output Waveform and FFT Plot of MAX3485E/MAX3490E/MAX3491E Transmitting a 125kHz Signal Figure 14. Driver Output Waveform and FFT Plot of MAX3483E/ MAX3488E Transmitting a 125kHz SignalM A X 3483E /M A X 3485E /M A X 3486E /M A X 3488E /M A X 3490E /M A X 3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers12______________________________________________________________________________________Figure 17. MAX3483E/MAX3488E Driver Propagation Delay Figure 19. MAX3483E/MAX3488E System Differential Voltage at 125kHz Driving 4000 Feet of Cable Figure 20. MAX3485E/MAX3490E/MAX3491E System Differential Voltage at 125kHz Driving 4000 Feet of CableDriver-Output Protection Excessive output current and power dissipation caused by faults or by bus contention are prevented by two mechanisms. A foldback current limit on the output stage provides immediate protection against short circuits over the whole common-mode voltage range (see Typical Operating Characteristics). In addition, a thermal shut-down circuit forces the driver outputs into a high-imped-ance state if the die temperature rises excessively.Propagation Delay Figures 15–18 show the typical propagation delays. Skew time is simply the difference between the low-to-high and high-to-low propagation delay. Small driver/receiver skew times help maintain a symmetrical mark-space ratio (50% duty cycle).The receiver skew time, |t PRLH- t PRHL|, is under 10ns (20ns for the MAX3483E/MAX3488E). The driver skew times are 8ns for the MAX3485E/MAX3490E/MAX3491E, 12ns for the MAX3486E, and typically under 50ns for the MAX3483E/MAX3488E.Line Length vs. Data Rate The RS-485/RS-422 standard covers line lengths up to 4000 feet. For line lengths greater than 4000 feet, see Figure 21 for an example of a line repeater.Figures 19 and 20 show the system differential voltage for parts driving 4000 feet of 26AWG twisted-pair wire at 125kHz into 120Ωloads.For faster data rate transmission, please consult the fac-tory.±15kV ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX3483E family of devices have extra protection against static electricity. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, Maxim’s E versions keep working without latchup or damage.ESD protection can be tested in various ways; the transmitter outputs and receiver inputs of this product family are characterized for protection to the following limits:1)±15kV using the Human Body Model2)±8kV using the Contact-Discharge method specifiedin IEC 1000-4-23)±15kV using IEC 1000-4-2’s Air-Gap method.ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results.Human Body Model Figure 22a shows the Human Body Model and Figure 22b shows the current waveform it generates when dis-charged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of inter-est, which is then discharged into the test device through a 1.5kΩresistor.IEC 1000-4-2 The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifi-cally refer to integrated circuits. The MAX3483E family of devices helps you design equipment that meets Level 4 (the highest level) of IEC 1000-4-2, without the need for additional ESD-protection components.The major difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak current in IEC 1000-4-2, because series resistance is lower in the IEC 1000-4-2 model. Hence, the ESD with-stand voltage measured to IEC 1000-4-2 is generally lower than that measured using the Human Body Model. Figure 23a shows the IEC 1000-4-2 model, and Figure 23b shows the current waveform for the ±8kV IEC 1000-4-2, Level 4 ESD contact-discharge test.Figure 21. Line Repeater for MAX3488E/MAX3490E/MAX3491EMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers ______________________________________________________________________________________13M A X 3483E /M A X 3485E /M A X 3486E /M A X 3488E /M A X 3490E /M A X 3491EThe air-gap test involves approaching the device with a charged probe. The contact-discharge method connects the probe to the device before the probe is energized.Machine ModelThe Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resis-tance. Its objective is to emulate the stress caused when I/O pins are contacted by handling equipment during test and assembly. Of course, all pins require this protection, not just RS-485 inputs and outputs.Typical ApplicationsThe MAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E transceivers are designed for bidirectional data communications on multipoint bus transmission lines. Figures 24 and 25 show typical net-work applications circuits. These parts can also be used as line repeaters, with cable lengths longer than 4000 feet, as shown in Figure 21.To minimize reflections, the line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possible. The slew-rate-limited MAX3483E/MAX3488E and the partially slew-rate-limited MAX3486E are more tolerant of imperfect termination.3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers14______________________________________________________________________________________Figure 22a. Human Body ESD Test ModelFigure 22b. Human Body Current WaveformFigure 23a. IEC 1000-4-2 ESD Test ModelFigure 23b. IEC 1000-4-2 ESD Generator Current WaveformMAX3483E/MAX3485E/MAX3486E/MAX3488E/MAX3490E/MAX3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceivers______________________________________________________________________________________15Figure 25. MAX3488E/MAX3490E/MAX3491E Full-Duplex RS-485 NetworkFigure 24. MAX3483E/MAX3485E/MAX3486E Typical RS-485 NetworkM A X 3483E /M A X 3485E /M A X 3486E /M A X 3488E /M A X 3490E /M A X 3491E3.3V-Powered, ±15kV ESD-Protected, 12Mbps and Slew-Rate-Limited T rue RS-485/RS-422 T ransceiversTRANSISTOR COUNT: 761Chip InformationOrdering Information (continued)Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.16____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©1999 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.。

MAX5498ETE中文资料

Features
♦ Wiper Position Stored in Nonvolatile Memory and Recalled Upon Power-Up ♦ 16-Pin, 5mm x 5mm x 0.8mm TQFN Package ♦ 35ppm/°C End-to-End Resistance Temperature Coefficient ♦ 5ppm/°C Ratiometric Temperature Coefficient ♦ 10kΩ and 50kΩ End-to-End Resistor Values ♦ 3-Wire SPI-Compatible Serial Interface ♦ Reliability (TA = +85°C) 50,000 Wiper Store Cycles 50 Years Wiper Data Retention ♦ 1.5µA (max) Standby Current ♦ Single +2.7V to +5.25V Supply Operation ♦ Dual ±2.5V Supply Operation
元器件交易网
19-3562; Rev 1; 6/05
10-Bit, Dual, Nonvolatile, Linear-Taper Digital Potentiometers
General Description
The MAX5494–MAX5499 10-bit (1024-tap), dual, nonvolatile, linear-taper, programmable voltage-dividers and variable resistors perform the function of a mechanical potentiometer, but replace the mechanics with a 3-wire SPI™-compatible serial interface. The MAX5494/MAX5495 are dual, 3-terminal, programmable voltage-dividers; the MAX5496/MAX5497 are dual, 2-terminal variable resistors; and the MAX5498/ MAX5499 include one 2-terminal variable resistor and one 3-terminal programmable voltage-divider. The MAX5494–MAX5499 feature an internal, nonvolatile, electrically erasable programmable read-only memory (EEPROM) that stores the wiper position for initialization during power-up. The 3-wire SPI-compatible serial interface allows communication at data rates up to 7MHz. The MAX5494–MAX5499 are ideal for applications requiring digitally controlled potentiometers. End-to-end resistance values of 10kΩ and 50kΩ are available with a 35ppm/°C end-to-end temperature coefficient. The ratiometric temperature coefficient is 5ppm/°C for each channel, making these devices ideal for applications requiring low-temperature-coefficient programmable voltagedividers such as low-drift, programmable-gain amplifiers. The MAX5494–MAX5499 operate with either a single power supply (+2.7V to +5.25V) or dual power supplies (±2.5V). The devices consume 400µA (max) of supply current when writing data to the nonvolatile memory and 1.5µA (max) of standby supply current. The devices are available in space-saving (5mm x 5mm x 0.8mm), 16-pin TQFN package and are specified over the extended (-40°C to +85°C) temperature range.

HMC5843资料

3-Axis Digital Compass IC HMC5843The Honeywell HMC5843 is a surface mount multi-chip module designed for low field magnetic sensing with a digital interface for applications such as low cost compassing and magnetometry. The HMC5843 includes our state of the art 1043 series magneto -resistive sensors plus Honeywell developed ASIC containing amplification, strap drivers, offset cancellation, 12-bit ADC and an I 2C serial bus interface. The HMC5843 is in a 4.0 by 4.0 by 1.3mm surface mount leadless chip carrier (L CC). Applications for the HMC5843 include Consumer Electronics, Auto Navigation Systems, Personal Navigation Devices, and Magnetometers.The HMC5843 utilizes Honeywell’s Anisotropic Magnetoresistive (AMR) technology that provides advantages over other magnetic sensor technologies. The sensors feature precision in-axis sensitivity and linearity, solid-state construction with very low cross-axis sensitivity designed to measure both direction and magnitude of Earth’s magnetic fields, from tens of micro-gauss to 6 gauss. Honeywell’s Magnetic Sensors are among the most sensitive and reliable low-field sensors in the industry.Honeywell continues to maintain product excellence and performance by introducing innovative solid-state magnetic sensor solutions. These are highly reliable, top performance products that are delivered when promised. Honeywell’s magnetic sensor solutions provide real solutions you can count on.FEATURES BENEFITS43-Axis Magnetoresistive Sensors andASIC in a Single Package4Small Size for Highly Integrated Products. Just Add a Micro- Controller Interface, Plus Two External SMT Capacitors4Low Cost4Designed for High Volume, Cost Sensitive OEM Designs44.0 x 4.0 x 1.3mm Low Height Profile LCC Surface Mount Package4Easy to Assemble & Compatible with High Speed SMT Assembly4Low Voltage Operations (2.5 to 3.3V) 4Compatible for Battery Powered Applications4Built-In Strap Drive Circuits4Set/Reset and Offset Strap Drivers for Degaussing, Self Test, andOffset Compensation4I 2C Digital Interface4Popular Two-Wire Serial Data Interface for Consumer Electronics4Lead Free Package Construction4Complies with Current Environmental Standards4Wide Magnetic Field Range (+/-6 Oe)4Sensors Can Be Used in Strong Magnetic Field Environments4Available in Tape & Reel Packaging4High Volume OEM Assembly元器件交易网SPECIFICATIONS (* Tested at 25°C except stated otherwise.)Characteristics Conditions* Min Typ Max Units Power SupplySupply Voltage AVDD Referenced to AGNDDVDD Referenced to DGND 2.51.6 1.83.32.0VoltsVoltsCurrent Draw Sleep Mode (dual supplies)Idle Mode (dual supplies)Measurement ModeAVDD = 2.5 volts, DVDD = 1.8 voltsSleep Mode (single supply)Idle Mode (single supply)Measurement ModeAVDD = 2.5 volts ------2.52400.81103400.9------uAuAmAuAuAmAPerformanceField Range Full scale (FS) – total applied field -4 +4 gauss Cross-Axis Sensitivity Cross field = 0.5 gauss,Happlied = ±3 gauss±0.2%%FS/gaussDisturbing Field Sensitivity starts to degrade.Use S/R pulse to restore sensitivity.20 gaussMax. Exposed Field No perming effect on zero reading 10000 gaussMeasurement Period Output Rate = 50Hz (10Hz typ.) - 10 msecI2C Address 7-bit address8-bit read address8-bit write address 0x1E0x3D0x3ChexhexhexI2C Rate Controlled by I2C Master -10 +10 %I2C bus pull-up Internal passive resistors50 kilo-ohms I2C Hysteresis Hysteresis of Schmitt trigger inputs on SCLand SDA - Fall (DVDD=1.8V) Rise (DVDD=1.8V) 0.6031.108VoltsVoltsSelf Test Positive and Negative Bias Mode ±0.55 gauss Mag Dynamic Range 3-bit gain control ±0.7 ±1.0 ±4.0 gauss Linearity Full scale input range 0.1 ±% FS Gain Tolerance All gain/dynamic range settings±5 %Bandwidth -3dB point10 kHzResolution AVDD=3.0V, GN 7 milli-gauss Signal-to Noise Ratio 70 dBTurn-on Time 200 us GeneralESD Voltage 700 VOperating Temperature Ambient-30 85 °CStorage Temperature Ambient, unbiased -40 125 °CWeight Nominal 50 milli-gramsPIN CONFIGURATIONS(Arrow indicates direction of applied field that generates a positive output voltage after a SET pulse.)Pin Name Description1 SCL Serial Clock – I2C Master/Slave Clock2 SDAP Serial Data Pull-up Resistor – 50k-ohm to VDD3 SCLP Serial Clock Pull-up Resistor – 50k-ohm to VDD4 NC No Connection5 NC No Connection6 OFFP Offset Strap Positive7 OFFN Offset Strap Negative8 NC No Connection9 SETP Set/Reset Strap Positive – S/R Capacitor (C2) Connection 10 SETN Set/Reset Strap Negative – Test Point 11 SVDD Sensor Supply – Test Point 12 DGND Digital Supply Ground/Return 13 C1 Reservoir Capacitor (C1) Connection 14 SETC S/R Capacitor (C2) Connection – Driver Side 15 DVDD Digital Positive Supply16 VRENVoltage Regulator Enable, (GND = Dual Supply, AVDD = Single Supply) 17 AGND Analog Supply Ground/Return 18 AVDD Analog Positive Supply 19 DRDY Data Ready – Test Point20SDASerial Data – I2C Master/Slave DataTable 1: Pin Configurations1234567891011121314151617181920HMC5843 –bottom viewSCLSDAPSCLPTP1TP0OFFP OFFN NC SETP SETNSVDDDGNDC1SETCDVDDVREN AGND AVDD DRDY SDAPACKAGE OUTLINESPACKAGE DRAWING HMC 5843 (20-PIN LPCC, dimensions in millimeters)MOUNTING CONSIDERATIONSThe following is the recommend printed circuit board (PCB) footprint f or the HMC 5843.PCB Pad Definition and TracesThe HMC5843 is a fine pitch LCC package with a 0.50mm pin pitch (spacing), with the pin pads defined as 0.40mm by 0.25mm in size. PCB pads are recommended to be oversized by 0.025mm from each pad for a short dimension oversize of 0.05mm. The interior PCB pad is recommended to be 0.05mm oversized per pin with an exterior oversize of 0.20mm for proper package centering and to permit test probing. Size the traces between the HMC5843 and the external capacitors (C1 and C2) to handle the 1 ampere peak current pulses with low voltage drop on the traces.Stencil Design and Solder PasteA 4 mil stencil and 100% paste coverage is recommended for the electrical contact pads.Pick and PlacePlacement is machine dependant and no restrictions are recommended, and have been tested with mechanical centering. Placement force should be equivalent 1206 SMT resistors and enough force should be used to squeeze the paste out from the package/contact pad overlap and to keep the package pin contacts vertical.Reflow and ReworkNo special profile is required for the HMC5843 and compatible with lead eutectic and lead-free solder paste reflow profiles. Honeywell recommends the adherence to solder paste manufacturer’s guidelines. The HMC 5843 may be reworked with soldering irons, but extreme care must be taken not to overheat the copper pads from the part’s fiberglass substrate. Irons with a tip temperature no greater than 315°C should be used. Excessive rework risks the copper pads pulling away into the molten solder.Sym Min Nom Max A 1.20-1.46D4.0 BSC D22.25D3 0.25 x 20 pins E4.0 BSC E22.25 e0.50 Basic L0.40 x 20 pinsHMC5843 –bottom viewEAINTERNAL SCHEMATIC DIAGRAM HMC5843DUAL SUPPLY REFERENCE DESIGNSINGLE SUPPLY REFERENCE DESIGNBASIC DEVICE OPERATIONAnisotropic Magneto-Resistive SensorsThe Honeywell HMC5843 magnetoresistive sensor circuit is a trio of sensors and application specific support circuits to measure magnetic fields. With power supply applied, the sensor converts any incident magnetic field in the sensitive axis directions to a differential voltage output. The magnetoresistive sensors are made of a nickel-iron (Permalloy) thin-film and patterned as a resistive strip element. In the presence of a magnetic field, a change in the bridge resistive elements causes a corresponding change in voltage across the bridge outputs.These resistive elements are aligned together to have a common sensitive axis (indicated by arrows on the pinouts) that will provide positive voltage change with magnetic fields increasing in the sensitive direction. Because the output only is in proportion to the one-dimensional axis (the principle of anisotropy) and its magnitude, additional sensor bridges placed at orthogonal directions permit accurate measurement of arbitrary field direction.Self TestAn offset strap is designed for self test function. The offset strap measures nominally 13 ohms, and requires 10mA for each gauss of induced field. The straps will easily handle currents to buck or boost fields through the ±4 gauss linear measurement range, but designers should note the extreme thermal heating on the sensor die when doing so.Power ManagementThis device is capable of operating with a single supply (AVDD) or dual supplies (AVDD and DVDD). Pin VREN makes this selection by enabling the internal digital supply voltage regulator. When VREN is tied to AVDD, the device is in single supply operation; this device is powered from AVDD; and the internal voltage regulator is enabled. When VREN is tied to AGND this devices operates with both AVDD and DVDD as supplies. The table below shows the modes available at the various power supply conditions.Table 2: Operational Modes and Supply StatesNote the continuous current draw versus data update rate in micro-amperes shown in the graph below. Under 10Hz, the current stays below 1mA.DVDD AVDD Pin VREN Modes SupportedDescriptionHighHighAGNDAll, except OffInternal voltage regulator: Disabled.Digital I/O pins: Range from DGND to DVDD. Device fully functional. Digital logic blocks are powered from DVDD supply, including all on-board clocks.High Low AGND IdleInternal voltage regulator: Disabled.Digital I/O pins: Range from DGND to DVDD. Device Measurement functionality not supported.Device I 2C bus and register access supported. Internally regulatedHigh AVDDAll, except OffInternal voltage regulator: EnabledDigital I/O pins: Range from AGND to AVDD Device fully functional. Digital logic blocks are powered through on-board regulator. Low Low -- OffDevice in off mode.Voltage RegulatorThis ASIC has an internal voltage regulator which, depending on the application needs, may be used instead of supplying voltage to pin DVDD. If DVDD pin is used, the internal voltage regulator is not engaged. When both supplies are used, DVDD is typically high before AVDD, but no latch-up conditions will exist if DVDD is brought high after AVDD.Power on ResetPower on reset (POR) circuit shall return the device to the power-on default state. All registers shall be returned to their default values. Circuitry shall return to it default state, such as, but not limited to: MUX channel, ADC state machine, and bias current.I2C InterfaceControl of this device is carried out via the I2C bus. This device will be connected to this bus as a slave device under the control of a master device, such as the processor.This device shall be compliant with I2C-Bus Specification, document number: 9398 393 40011. As an I2C compatible device, this device has a 7-bit serial address and supports I2C protocols. This device shall support standard and fast modes, 100kHz and 400kHz respectively, but cannot support the high speed mode (Hs). External pull-up resistors are required to support these standard and fast speed modes. Depending on the application, the internal pull-ups may be used to support slower data speeds than specified by I2C standards. This device does not contain 50nsec spike suppression as required by fast mode operation in the I2C-Bus Specification, “Table 4 Characteristics of the SDA and SCL I/O stages for F/S-mode I2C-bus devices”.Activities required by the master (register read and write) have priority over internal activities, such as the measurement. The purpose of this priority is to not keep the master waiting and the I2C bus engaged for longer than necessary.I2C Pull-up ResistorsPull-up resistors are placed on the two I2C bus lines. Typically these resistors are off-chip, but, to conserve board space in specific low clock speed applications, they are internal to this device.Internal ClockThe device has an internal clock for internal digital logic functions and timing management.H-Bridge for Set/Reset Strap DriveThe ASIC contains large switching FETs capable of delivering a large but brief pulse to the Set / Reset strap of the sensor. This strap is largely a resistive load.Charge Current LimitThe current that reservoir capacitor (C1) can draw when charging is limited. When using dual supplies this device shall limit the current drawn from DVDD source to charge this capacitor. When only a single supply is used, Pin DVDD is externally tied to pin C1. In this configuration, current is still limited. For example, the internal voltage regulator will limit this current draw.Bias Current GeneratorThe bias current generator is used to apply a bias current to the offset strap of the magneto-resistive sensor, which creates an artificial magnetic field bias on the sensor. This function is enabled and the polarity is set by bits MS[n] in the configuration register. The bias current generator generate s dc current supplied from the AVDD supply.MODES OF OPERATIONThis device has several modes whose primary purpose is power management. This section describes these modes. Continuous-Measurement ModeDuring continuous-measurement mode, the device continuously makes measurements and places measured data in data output registers. Settings in the configuration register affect the data output rate (bits DO[n]), the measurement configuration (bits MS[n]), and the gain (bits GN[n]) when in continuous-measurement mode. To conserve current between measurements, the device is placed in a state similar to idle mode, but the mode is not changed to idle mode. That is, MD[n] bits are unchanged. Data can be re-read from the data output registers if necessary; however, if the master does not ensure that the data register is accessed before the completion of the next measurement, the new measurement may be lost. All registers maintain values while in continuous-measurement mode. The I2C bus is enabled for use by other devices on the network in while continuous-measurement mode.Single-Measurement ModeThis is the default single supply power-up mode. In dual supply configuration this is the default mode when AVDD goes high. During single-measurement mode, the device makes a single measurement and places the measured data in data output registers. Settings in the configuration register affect the measurement configuration (bits MS[n]), and the gain (bits GN[n]) when in single-measurement mode. After the measurement is complete and output data registers are updated, the device is placed sleep mode, and the mode register is changed to sleep mode by setting MD[n] bits. All registers maintain v alues while in single-measurement mode. The I2C bus is enabled for use by other devices on the network while in single-measurement mode.Idle ModeDuring this mode the device is accessible through the I2C bus, but major sources of power consumption are disabled, such as, but not limited to, the ADC, the amplifier, the SVDD pin, and the sensor bias current. All registers maintain values while in idle mode. The I2C bus is enabled for use by other devices on the network while in idle mode.Sleep ModeThis is the default dual supply power-up mode when only DVDD goes high and AVDD remains low. During sleep mode the device functionality is limited to listening to the I2C bus. The internal clock is not running and register values are not maintained while in sleep mode. The only functionality that exists during this mode is the device is able to recognize and execute any instructions specific to this device but does not change from sleep mode due to other traffic on the I2C bus. The I2C bus is enabled f or use by other devices on the network while in sleep mode. This mode has two practical differences from idle mode. First this state will create less noise on system since the clock is disabled, and secondly this state is a lower current consuming state since the clock is disabled.Off ModeDuring off mode device is off. No device functionality exists. Both AVDD and DVDD are low. The I2C bus is enabled for use by other devices on the network in off mode. In this mode the I2C pins shall be in a high impedance state.REGISTERSThis device is controlled and configured via a number of on-chip registers, which are described in this section. In the following descriptions, set implies a logic 1, and reset or clear implies a logic 0, unless stated otherwise.Register ListThe table below lists the registers and their access. All address locations are 8 bits.Address Location Name Access00 Configuration Register A Read/Write01 Configuration Register B Read/Write02 Mode Register Read/Write03 Data Output X MSB Register Read04 Data Output X LSB Register Read05 Data Output Y MSB Register Read06 Data Output Y LSB Register Read07 Data Output Z MSB Register Read08 Data Output Z LSB Register Read09 Status Register Read10 Identification Register A Read11 Identification Register B Read12 Identification Register C ReadTable 5: Register ListRegister AccessThis section describes the process of reading from and writing to this device. The devices uses an address pointer to indicate which register location is to be read from or written to. These pointer locations are sent from the master to this slave device and succeed the 7-bit address plus 1 bit read/write identifier.To minimize the communication between the master and this device, the address pointer updated automatically without master intervention. This automatic address pointer update has two additional features. First when address 12 or higher is accessed the pointer updates to address 00 and secondly when address 09 is reached, the pointer rolls back to address 03. Logically, the address pointer operation functions as shown below.If (address pointer = 09) then address pointer = 03Else if (address pointer >= 12) then address pointer = 0Else (address pointer) = (address pointer) + 1The address pointer value itself cannot be read via the I2C bus.Any attempt to read an invalid address location returns 0’s, and any write to an invalid address location or an undefined bit within a valid address location is ignored by this device.The configuration register is used to configure the device for setting the data output rate and measurement configuration. CRA0 through CRA7 indicate bit locations, with CRA denoting the bits that are in the configuration register. CRA7 denotes the first bit of the data stream. The number in parenthesis indicates the default value of that bit.CRA7 CRA6 CRA5 CRA4 CRA3 CRA2 CRA1 CRA0(0) (0) (0) DO2 (1) DO1 (0) DO0 (0) MS1 (0) MS0 (0)Table 6: Configuration Register ALocation Name DescriptionCRA7 to CRA5 0 These bits must be cleared for correct operation.CRA4 to CRA2 DO2 to DO0 Data Output Rate Bits. These bits set the rate at which data is written to all three data output registers.CRA1 to CRA0 MS1 to MS0 Measurement Configuration Bits. These bits define the measurement flow of the device, specifically whether or not to incorporate an applied bias to the sensor into the measurement.Table 7: Configuration Register A Bit DesignationsThe Table below shows minimum output data rates given PVT conditions. All three channels shall be measured within a given data rate.DO2 DO1 DO0 Minimum Data Output Rate (Hz)0 0 0 0.50 0 1 10 1 0 20 1 1 51 0 0 10 (default)1 0 1 201 1 0 501 1 1 Not usedTable 8: Data Output RatesMS1 MS0 Mode0 0 Normal measurement configuration (default). In normal measurement configuration the device follows normal measurement flow. Pins BP and BN are left floating and high impedance.0 1 Positive bias configuration. In positive bias configuration, a positive current is forced across the resistive load on pins BP and BN.1 0 Negative bias configuration. In negative bias configuration, a negative current is forced across the resistive load on pins BP and BN.1 1 This configuration is not used.Table 9: Measurement ModesThe configuration register B for setting the device gain. CRB0 through CRB7 indicate bit locations, with CRB denoting the bits that are in the configuration register. CRB7 denotes the first bit of the data stream. The number in parenthesis indicates the default value of that bit.CRB7 CRB6 CRB5 CRB4 CRB3 CRB2 CRB1 CRB0GN2 (0) GN1 (0) GN0 (1) (0) (0) (0) (0) (0)Table 10: Configuration B RegisterLocation Name DescriptionCRB7 to CRB5 GN2 to GN0 Gain Configuration Bits. These bits configure the gain for the device. The gain configuration is common for all channels.CRB4 to CRB0 0 This bit must be cleared for correct operation.Table 11: Configuration Register B Bit DesignationsThe table below shows nominal gain settings.GN2 GN1 GN0 Sensor Input FieldRange:Gain(counts/milli-gauss)Output Range0 0 0 ±0.7Ga 1620 0xF800–0x07FF (-2048–2047 )0 0 1 ±1.0Ga (default) 1300 0xF800–0x07FF (-2048–2047 )0 1 0 ±1.5Ga 970 0xF800–0x07FF (-2048–2047 )0 1 1 ±2.0Ga 780 0xF800–0x07FF (-2048–2047 )1 0 0 ±3.2Ga 530 0xF800–0x07FF (-2048–2047 )1 0 1 ±3.8Ga 460 0xF800–0x07FF (-2048–2047 )1 1 0 ±4.5Ga 390 0xF800–0x07FF (-2048–2047 )1 1 1 ±6.5Ga(Not Recommended)2800xF800–0x07FF(-2048–2047 ) Table 12: Gain SettingsThe resolution of the HMC5843 is based on the gain selection (zero to 7) and the influence of the analog power supply rail (AVDD). The following graph shows the interaction.Mode RegisterThe mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to select the operating mode of the device. MR0 through MR7 indicate bit locations, with MR denoting the bits that are in the mode register. MR7 denotes the first bit of the data stream. The number in parenthesis indicates the default value of that bit.MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0(0) (0) (0) (0) (0) (0) MD1 (1) MD0 (0)Table 14: Mode RegisterLocation Name DescriptionMR7 toMR20 These bits must be cleared for correct operation.MR1 to MR0 MD1 toMD0Mode Select Bits. These bits select the operation mode ofthis device.Table 15: Mode Register Bit DesignationsMD1 MD0 Mode0 0 Continuous-Conversion Mode. In continuous-conversion mode, the device continuously performs conversions an places the result in the data register. RDY goes high when new data is placed in all three registers. After a power-on or a write to the mode or configuration register, the first measurement set is available from all three data output registers after a period of 2/f DO and subsequent measurements are available at a frequency of f DO, where f DO is the frequency of data output.0 1 Single-Conversion Mode. When single-conversion mode is selected, device performs a single measurement, sets RDY high and returned to sleep mode. Mode register returns to sleep mode bit values. The measurement remains in the data output register and RDY remains high until the data output register is read or another conversion is performed.1 0 Idle Mode. Device is placed in idle mode.1 1 Sleep Mode. Device is placed in sleep mode.Table 16: Operating ModesData Output X Registers A and BThe data output X registers are two 8-bit registers, data output register A and data output register B. These registers store the measurement result from channel X. Data output X register A contains the MSB from the measurement result, and data output X register B contains the LSB from the measurement result. The value stored in these two registers is a 16-bit value in 2’s complement form, whose range is 0xF800 to 0x07FF. DXRA0 through DXRA7 and DXRB0 through DXRB7 indicate bit locations, with DXRA and DXRB denoting the bits that are in the data output X registers. DXRA7 and DXRB7 denote the first bit of the data stream. The number in parenthesis indicates the default value of that bit.In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias measurement, this data register will contain the value -4096 in 2’s complement form. This register value will clear when after the next valid measurement is made.DXRA7 DXRA6 DXRA5 DXRA4 DXRA3 DXRA2 DXRA1 DXRA0(0) (0) (0) (0) (0) (0) (0) (0)DXRB7 DXRB6 DXRB5 DXRB4 DXRB3 DXRB2 DXRB1 DXRB0(0) (0) (0) (0) (0) (0) (0) (0)Table 17: Data Output X Registers A and BData Output Y Registers A and BThe data output Y registers are two 8-bit registers, data output register A and data output register B. These registers store the measurement result from channel Y. Data output Y register A contains the MSB from the measurement result, and data output Y register B contains the LSB from the measurement result. The value stored in these two registers is a 16-bit value in 2’s complement form, whose range is 0xF800 to 0x07FF. DYRA0 through DYRA7 and DYRB0 through DYRB7 indicate bit locations, with DYRA and DYRB denoting the bits that are in the data output Y registers. DYRA7 and DYRB7 denote the first bit of the data stream. The number in parenthesis indicates the default value of that bit.In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias measurement, this d ata register will contain the value -4096 in 2’s complement form. This register value will clear when after the next valid measurement is made.DYRA7 DYRA6 DYRA5 DYRA4 DYRA3 DYRA2 DYRA1 DYRA0(0) (0) (0) (0) (0) (0) (0) (0)DYRB7 DYRB6 DYRB5 DYRB4 DYRB3 DYRB2 DYRB1 DYRB0(0) (0) (0) (0) (0) (0) (0) (0)Table 18: Data Output Y Registers A and BData Output Z Registers A and BThe data output Z registers are two 8-bit registers, data output register A and data output register B. These registers store the measurement result from channel Z. Data output Z register A contains the MSB from the measurement result, and data output Z register B contains the LSB from the measurement result. The value stored in these two registers is a 16-bit value in 2’s complement form, whose range is 0xF800 to 0x07FF. DZRA0 through DZRA7 and DZRB0 through DZRB7 indicate bit locations, with DZRA and DZRB denoting the bits that are in the data output Z registers. DZRA7 and DZRB7 denote the first bit of the data stream. The number in parenthesis indicates the default value of that bit.In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias measurement, this data register will contain the value -4096 in 2’s complement form. This register value will clear when after the next valid measurement is made.DZRA7 DZRA6 DZRA5 DZRA4 DZRA3 DZRA2 DZRA1 DZRA0(0) (0) (0) (0) (0) (0) (0) (0)DZRB7 DZRB6 DZRB5 DZRB4 DZRB3 DZRB2 DZRB1 DZRB0(0) (0) (0) (0) (0) (0) (0) (0)Table 19: Data Output Z Registers A and BData Output Register OperationWhen one or more of the output registers are read, new data cannot be placed in any of the output data registers until all six data output registers are read. This requirement also impacts DRDY and RDY, which cannot be cleared until new data is placed in all the output registers.Status RegisterThe status register is an 8-bit read-only register. This register is used to indicate device status. SR0 through SR7 indicate bit locations, with SR denoting the bits that are in the status register. SR7 denotes the first bit of the data stream.SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0(0) (0) (0) (0) (0) REN (0) LOCK (0) RDY(0)Table 20: Status Register。

MAX3378EEUD中文资料

General DescriptionThe MAX3372E–MAX3379E and MAX3390E–MAX3393E ±15kV ESD-protected level translators provide the level shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, V CC and V L , set the logic levels on either side of the device. A low-voltage logic signal present on the V L side of the device appears as a high-voltage logic signal on the V CC side of the device, and vice-versa. The MAX3374E/MAX3375E/MAX3376E/MAX3379E and MAX3390E–MAX3393E unidi-rectional level translators level shift data in one direction (V L →V CC or V CC →V L ) on any single data line. The MAX3372E/MAX3373E and MAX3377E/MAX3378E bidi-rectional level translators utilize a transmission-gate-based design (Figure 2) to allow data translation in either direction (V L ↔V CC ) on any single data line. The MAX3372E–MAX3379E and MAX3390E–MAX3393E accept V L from +1.2V to +5.5V and V CC from +1.65V to +5.5V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems.All devices in the MAX3372E–MAX3379E, MAX3390E–MAX3393E family feature a three-state output mode that reduces supply current to less than 1µA, thermal short-circuit protection, and ±15kV ESD protection on the V CC side for greater protection in applications that route sig-nals externally. The MAX3372E/MAX3377E operate at a guaranteed data rate of 230kbps. Slew-rate limiting reduces EMI emissions in all 230kbps devices. The MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E operate at a guaranteed data rate of 8Mbps over the entire specified operating voltage range. Within specific voltage domains, higher data rates are possible. (See Timing Characteristics .)The MAX3372E–MAX3376E are dual level shifters available in 3 x 3 UCSP™ and 8-pin SOT23-8 pack-ages. The MAX3377E/MAX3378E/MAX3379E and MAX3390E–MAX3393E are quad level shifters avail-able in 3 x 4 UCSP and 14-pin TSSOP packages.________________________ApplicationsSPI™, MICROWIRE™, and I 2C™ Level TranslationLow-Voltage ASIC Level Translation Smart Card Readers Cell-Phone Cradles Portable POS SystemsPortable Communication Devices Low-Cost Serial Interfaces Cell Phones GPSTelecommunications EquipmentFeatureso Guaranteed Data Rate Options230kbps8Mbps (+1.2V ≤V L ≤V CC ≤+5.5V)10Mbps (+1.2V ≤V L ≤V CC ≤+3.3V)16Mbps (+1.8V ≤V L ≤V CC ≤+2.5V and +2.5V ≤V L ≤V CC ≤+3.3V)o Bidirectional Level Translation (MAX3372E/MAX3373E and MAX3377E/MAX3378E)o Operation Down to +1.2V on V Lo ±15kV ESD Protection on I/O V CC Lineso Ultra-Low 1µA Supply Current in Three-State Output Modeo Low-Quiescent Current (130µA typ)o UCSP, SOT, and TSSOP Packages o Thermal Short-Circuit ProtectionMAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSP________________________________________________________________Maxim Integrated Products1Pin Configurations19-2328; Rev 3; 9/03For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Ordering InformationUCSP is a trademark of Maxim Integrated Products, Inc.SPI is a trademark of Motorola, Inc.I 2C is a trademark of Phillips Corp.MICROWIRE is a trademark of National Semiconductor Corp.Ordering Information continued at end of data sheet.Selector Guide appears at end of data sheet.M A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.All Voltages Referenced to GNDV CC ...........................................................................-0.3V to +6V I/O V CC_......................................................-0.3V to (V CC + 0.3V)I/O V L_...........................................................-0.3V to (V L + 0.3V)THREE-STATE ...............................................-0.3V to (V L + 0.3V)Short-Circuit Duration I/O V L , I/O V CC to GND...........Continuous Short-Circuit Duration I/O V L or I/O V CC to GND Driven from 40mA Source(except MAX3372E and MAX3377E).....................ContinuousContinuous Power Dissipation (T A = +70°C)8-Pin SOT23 (derate 8.9mW/°C above +70°C)...........714mW 3 x 3 UCSP (derate 4.7mW/°C above +70°C)............379mW 3 x 4 UCSP (derate 6.5mW/°C above +70°C)............579mW 14-Pin TSSOP (derate 9.1mW/°C above +70°C)........727mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSP_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS (continued)(V CC = +1.65V to +5.5V, V L = +1.2V to (V CC + 0.3V), GND = 0, I/O V L_and I/O V CC_unconnected, T A = T MIN to T MAX , unless other-M A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP 4_______________________________________________________________________________________TIMING CHARACTERISTICS(V CC = +1.65V to +5.5V, V L = +1.2V to (V CC + 0.3V), GND = 0, R LOAD = 1M Ω, I/O test signal of Figure 1, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +3.3V, V L = +1.8V, T A = +25°C, unless otherwise noted.) (Notes 1, 2)MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSP_______________________________________________________________________________________5and not production tested.Note 2:For normal operation, ensure V L < (V CC + 0.3V). During power-up, V L > (V CC + 0.3V) will not damage the device. Note 3:To ensure maximum ESD protection, place a 1µF capacitor between V CC and GND. See Applications Circuits .Note 4:10% to 90% Note 5:90% to 10%TIMING CHARACTERISTICS (continued)(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, R = 1M Ω, I/O test signal of Figure 1, T = T to T , unlessM A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP 6_______________________________________________________________________________________Typical Operating Characteristics(R L = 1M Ω, T A = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps TOCs apply to MAX3373E –MAX3376E/MAX3378E/MAX3379E and MAX3390E –MAX3393E only.)V L SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O V L , V CC = +3.3V, V L = +1.8V)V CC (V)S U P P L Y C U R R E N T (µA )4.954.403.853.302.752.2010020030040050060001.655.50V CC SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O V L , V CC = +3.3V, V L = +1.8V)V CC (V)S U P P L Y C U R R E N T (m A )4.954.403.853.302.752.200.51.01.52.02.53.03.501.65 5.50V L SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/O V CC , V CC = +3.3V, V L = +1.8V)TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )6035-151050100150200250300350400-4085V CC SUPPLY CURRENT vs. TEMPERATURE(DRIVING I/O V CC , V CC = +3.3V, V L = +1.8V)TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )6035-151020040060080010001200140016000-4085V L SUPPLY CURRENT vs. CAPACITIVE LOAD (DRIVING I/O V L , V CC = +3.3V, V L= +1.8V)CAPACITIVE LOAD (pF)S U P P L Y C U R R E N T (µA )857055402550100150200250300350010100V CC SUPPLY CURRENT vs. CAPACITIVE LOAD (DRIVING I/O V L , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)S U P P L Y C U R R E N T (µA )8570554025500100015002000250010100RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V L , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )908070605040305001000150020002500020100RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V L , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )454030352025152468101214161801050RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V L , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )454035302520155010015020025001050MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSP_______________________________________________________________________________________7PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O V L , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)P R O P A G A T I O N D E L A Y (n s )90807060504030100200300400500600700020100PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O V L , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)P R O P A G A T I O N D E L A Y (n s )4540353025201536912151050PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O V L , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)P R O P A G A T I O N D E L A Y (n s )454035302520155010015020025030001050RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V L , V CC = +2.5V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )908070605040305001000150020002500020100RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V L, V CC = +2.5V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )4540353025201524681012141050RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V CC , V CC = +2.5V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )45403530252015501001502002503001050RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V CC , V CC= +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )908070605040305001000150020002500020100RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V CC , VCC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )454035302520152468101201050RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V CC , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )454035302520155010015020025030001050Typical Operating Characteristics (continued)(R L = 1M Ω, T A = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps TOCs apply to MAX3373E –MAX3376E/MAX3378E/MAX3379E and MAX3390E –MAX3393E only.)M A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP 8_______________________________________________________________________________________Typical Operating Characteristics (continued)(R L = 1M Ω, T A = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps TOCs apply to MAX3373E –MAX3376E/MAX3378E/MAX3379E and MAX3390E –MAX3393E only.)PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O V CC , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)P R O P A G A T I O N D E L A Y (n s )90807060504030100200300400500600700020100PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O V CC , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)P R O P A G A T I O N D E L A Y (n s )4540353025201512345601050PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING I/O V CC , V CC = +3.3V, V L = +1.8V)CAPACITIVE LOAD (pF)P R O P A G A T I O N D E L A Y (n s )454035302520155010015020025030001050RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V CC , V CC = +2.5V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )908070605040305001000150020002500020100RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V CC , V CC = +2.5V, V L = +1.8V)CAPACITIVE LOAD (pF)R I S E /F A L L T I M E (n s )403020246810121050RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING I/O V CC , V CC = +2.5V, V L = +1.8V)CAPACITIVE LOAD (pF)RI S E /F A L l T I M E (n s )403020501001502002503003501050RAIL-TO-RAIL DRIVING(DRIVING I/O V L , V CC = +3.3V, V L = +1.8V,C L = 50pF, DATA RATE = 230kbps)M A X 3372E t o c 25I/O V L_I/O V CC_1V/div 2V/div 1µs/div RAIL-TO-RAIL DRIVING(DRIVING I/O V L , V CC = +3.3V, V L = +1.8V,C L = 15pF, DATA RATE = 8Mbps)M A X 3372E t o c 26I/O V L_I/O V CC_1V/div2V/div200ns/divMAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSP_______________________________________________________________________________________9Typical Operating Characteristics (continued)(R L = 1M Ω, T A = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps TOCs apply to MAX3373E –MAX3376E/MAX3378E/MAX3379E and MAX3390E –MAX3393E only.)EXITING THREE-STATE OUTPUT MODE (V CC = +3.3V, V L = +1.8V, C L = 50pF)MAX3372E toc28I/O V L_I/O V CC_2µs/divTHREE-STATE2V/div1V/div1V/divConfigurations for input/output configurations.OPEN-DRAIN DRIVING(DRIVING I/O V L , V CC = +3.3V, V L = +1.8V,C L = 15pF, DATA RATE = 500kbps)M A X 3372E t o c 27I/O V L_I/O V CC_1V/div2V/div200ns/divM A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP 10______________________________________________________________________________________Detailed DescriptionThe MAX3372E –MAX3379E and MAX3390E –MAX3393E ESD-protected level translators provide the level shifting necessary to allow data transfer in a multivoltage system.Externally applied voltages, V CC and V L , set the logic lev-els on either side of the device. A low-voltage logic signal present on the V L side of the device appears as a high-voltage logic signal on the V CC side of the device, and vice-versa. The MAX3374E/MAX3375E/MAX3376E/MAX3379E and MAX3390E –MAX3393E unidirectional level translators level shift data in one direction (V L →V CC or V CC →V L ) on any single data line. The MAX3372E/MAX3373E and MAX3377E/MAX3378E bidi-rectional level translators utilize a transmission-gate-based design (see F igure 2) to allow data translation in either direction (V L ↔V CC ) on any single data line. The MAX3372E –MAX3379E and MAX3390E –MAX3393E accept V L from +1.2V to +5.5V and V CC from +1.65V to +5.5V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems.All devices in the MAX3372E –MAX3379E, MAX3390E –MAX3393E family feature a three-state output mode that reduces supply current to less than 1µA, thermal short-circuit protection, and ±15kV ESD protection on the V CC side for greater protection in applications that route sig-nals externally. The MAX3372E/MAX3377E operate at a guaranteed data rate of 230kbps. Slew-rate limiting reduces EMI emissions in all 230kbps devices. The MAX3373E –MAX3376E/MAX3378E/MAX3379E and MAX3390E –MAX3393E operate at a guaranteed data rate of 8Mbps over the entire specified operating voltage range. Within specific voltage domains, higher data rates are possible. (See Timing Characteristics .)Level TranslationFor proper operation ensure that +1.65V ≤V CC ≤+5.5V,+1.2V ≤V L ≤+5.5V, and V L ≤(V CC + 0.3V). During power-up sequencing, V L ≥(V CC + 0.3V) will not damage the device. During power-supply sequencing, when V CC is floating and V L is powering up, a current may be sourced, yet the device will not latch up. The speed-upFigure 1a. Rail-to-Rail Driving I/O V LFigure 1b. Rail-to-Rail Driving I/O V CCRail-to-Rail is a registered trademark of Nippon Motorola, Ltd.MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSPcircuitry limits the maximum data rate for devices in the MAX3372E –MAX3379E, MAX3390E –MAX3393E family to 16Mbps. The maximum data rate also depends heavily on the load capacitance (see Typical Operating Characteristics ), output impedance of the driver, and the operational voltage range (see Timing Characteristics).Speed-Up CircuitryThe MAX3373E –MAX3376E/MAX3378E/MAX3379E and MAX3390E –MAX3393E feature a one-shot generator that decreases the rise time of the output. When triggered,MOSFETs PU1 and PU2 turn on for a short time to pull up I/O V L_and I/O V CC_to their respective supplies (see Figure 2b). This greatly reduces the rise time and propa-gation delay for the low-to-high transition. The scope photo of Rail-to-Rail Driving for 8Mbps Operation in the Typical Operating Characteristics shows the speed-up circuitry in operation.Three-State Output ModePull THREE-STATE low to place the MAX3372E –MAX3379E and MAX3390E –MAX3393E in three-state out-put mode. Connect THREE-STATE to V L (logic high) for normal operation. Activating the three-state output mode disconnects the internal 10k Ωpullup resistors on the I/O V CC and I/O V L lines. This forces the I/O lines to a high-impedance state, and decreases the supply current to less than 1µA. The high-impedance I/O lines in three-state output mode allow for use in a multidrop network.When in three-state output mode, do not allow the voltage at I/O V L_to exceed (V L + 0.3V), or the voltage at I/O V CC_to exceed (V CC + 0.3V).Thermal Short-Circuit ProtectionThermal overload detection protects the MAX3372E –MAX3379E and MAX3390E –MAX3393E from short-circuit fault conditions. In the event of a short-circuit fault, when the junction temperature (T J ) reaches +152°C, a thermal sensor signals the three-state output mode logic to force the device into three-state output mode. When T J has cooled to +142°C, normal operation resumes.Figure 1c. Open-Drain Driving I/O V CC Figure 1d. Open-Drain Driving I/O V LM A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPFigure 2a. Functional Diagram, MAX3372E/MAX3377E (1I/O line)Figure 2b. Functional Diagram, MAX3373E/MAX3378E (1I/O line)MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSP±15kV ESD ProtectionAs with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly.The I/O V CC lines have extra protection against static electricity. Maxim ’s engineers have developed state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD structures withstand high ESD in all states: normal operation, three-state out-put mode, and powered down. After an ESD event,Maxim ’s E versions keep working without latchup,whereas competing products can latch and must be powered down to remove latchup.ESD protection can be tested in various ways. The I/O V CC lines of this product family are characterized for protection to the following limits:1)±15kV using the Human Body Model2)±8kV using the Contact Discharge method specified in IEC 1000-4-23)±10kV using IEC 1000-4-2’s Air-Gap Discharge method ESD Test ConditionsESD performance depends on a variety of conditions.Contact Maxim for a reliability report that documents test setup, test methodology, and test results.Human Body ModelFigure 3a shows the Human Body Model and Figure 3b shows the current waveform it generates when dis-charged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of inter-est, which is then discharged into the test device through a 1.5k Ωresistor.IEC 1000-4-2The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifi-cally refer to integrated circuits. The MAX3372E –MAX3379E and MAX3390E–MAX3393E help to design equipment that meets Level 3 of IEC 1000-4-2, without the need for additional ESD-protection components.The major difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak cur-rent in IEC 1000-4-2, because series resistance is lower in the IEC 1000-4-2 model. Hence, the ESD withstand voltage measured to IEC 1000-4-2 is generally lower than that measured using the Human Body Model. Figure 4a shows the IEC 1000-4-2 model, and Figure 4b shows the current waveform for the ±8kV, IEC 1000-4-2, Level 4,ESD contact-discharge test.The air-gap test involves approaching the device with a charged probe. The contact-discharge method connects the probe to the device before the probe is energized.Machine ModelThe Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resis-tance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. Of course, all pins require this protec-tion during manufacturing, not just inputs and outputs.Therefore, after PC board assembly, the Machine Model is less relevant to I/O ports.Figure 3a. Human Body ESD Test Model Figure 3b. Human Body Current WaveformM A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPApplications InformationPower-Supply DecouplingTo reduce ripple and the chance of transmitting incor-rect data, bypass V L and V CC to ground with a 0.1µF capacitor. See Typical Operating Circuit. To ensure full ±15kV ESD protection, bypass V CC to ground with a 1µF capacitor. Place all capacitors as close to the power-supply inputs as possible.I 2C Level TranslationThe MAX3373E –MAX3376E, MAX3378E/MAX3379E and MAX3390E –MAX3393E level-shift the data present on the I/O lines between +1.2V and +5.5V, making them ideal for level translation between a low-voltageASIC and an I 2C device. A typical application involves interfacing a low-voltage microprocessor to a 3V or 5V D/A converter, such as the MAX517.Push-Pull vs. Open-Drain DrivingAll devices in the MAX3372E –MAX3379E and MAX3390E –MAX3393E family may be driven in a push-pull configuration. The MAX3373E –MAX3376E/MAX3378E/MAX3379E and MAX3390E –MAX3393E include internal 10k Ωresistors that pull up I/O V L_and I/O V CC_to their respective power supplies, allowing operation of the I/O lines with open-drain devices. See Timing Characteristics for maximum data rates when using open-drain drivers.Figure 4b. IEC 1000-4-2 ESD Generator Current WaveformFigure 4a. IEC 1000-4-2 ESD Test Model Typical Operating CircuitMAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSPApplications CircuitsM A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Applications Circuits (continued)±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPApplications Circuits (continued)MAX3372E–MAX3379E/MAX3390E–MAX3393EM A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPApplications Circuits (continued)MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSPApplications Circuits (continued)M A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP Selector Guide*Higher data rates are possible (see Timing Characteristics).Ordering Information (continued)*Future product —contact factory for availability.MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSPPin Configurations (continued)M A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPPin Configurations (continued)MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSPPin Configurations (continued)M A X 3372E –M A X 3379E /M A X 3390E –M A X 3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP 24______________________________________________________________________________________Chip InformationTRANSISTOR COUNT:MAX3372E –MAX3376E: 189MAX3377E –MAX3379E, MAX3390E –MAX3393E:295PROCESS: BiCMOSPackage Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/QuadLow-Voltage Level Translators in UCSPMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________25©2003 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)。

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