EMIStream13项检查项目

Technical Manual(1)EMI Rule Check EMI规则检查EMIStream checks trace and layout information in design data against EMI-related factors and grades the information as passing or failing.The results are visually displayed on the net using colors coded for error frequency so the priority of items that need to be corrected can be identified.EMIStream检查信号布线和设计的布局信息以及和EMI有关的信息。

(2)Plane Resonance Analysis 层阻抗分析The state of plane resonance is calculated from the shape of the power plane to assist in tasks such as layout capacitor investigations as well as determining the layout of components and the strength of decoupling.层阻抗由电源层的大小而计算所得出。

电源层用于辅助电容设计，同时决定了元件以及退耦电容的布局。

EMI Rule CheckOutline of Verification ItemsThe follow ing EMI Rule Check functions are available:以下就是EMI的13项检查(1) Trace Length(布线检查)(2) Via Count(过孔数检查)(3) Traces Near Plane Edge(基板边缘布线检查)(4) Reference Change(参考层改变检查)(5) Return Current Path Discontinuity (不连续回流路径检查)(6) SG Trace(SG布线模式)(7) Estimated Radiation(电场辐射检查)(8) SG Via Spacing(SG模式的过孔距离检查)(9) Grounding Vias Along Plane Outline(层板边缘的接地过孔检查)(10) Filter(滤波器检查)(11) Decoupling Capacitor(退耦电容检查)(12) Differential Signal (差分信号检查)(13) XTalk(串扰检查)Each of these items is described below.以下是详细介绍(1)Trace Length布线检查Objects of Check:The checked object is as follow s:Wire Check TargetNon w ired Length of Manhattan for connections betw een pairsof pinsWired Total length of net w ires网络线的总长The total w ire length refers to the total length of all the trace for the net in question.FIG. 1‑1 Sample Wired DataCo ntents o f Check:The trace length determines if the object item is w ithin the “maximum trace length.”判断实际的布线长度是否在EMI系统设定的最大布线长之内。

Tro ubles ho oting errors:Shorten the trace length by changing the layout of the components or traces.通过改变元件的布局或路径来缩短布线长*If the trace length is too long, there is a higher risk that undesirable electromagnetic radiation w ill increase because of the increase in the current loop area.如果布线长太长，电流回流路径将会增加电磁辐射的危险性会更高。

(2)Via Count过孔数检查Objects of Check:The checked object is as follow s:Wire Check TargetNon wired N/AWired Total via count on the net网络上所有的过孔数FIG. 2‑1 Sample of Wire with ViasCo ntents o f Check:This command checks if the number of vias on the net is w ithin the number of “Maximum via count”电路板上的过孔数量是否小于软件设定的“最大过孔数量”Tro ubles ho oting errors:Decrease the number of vias by changing the layout of the components and traces.通过改变元件的布局和布线布局来替代增加过孔数量* The number of vias needs to be minimized as much as possible because they cause resonance energy in the pow er and ground planes.*过孔数量需要尽可能地最小化，因为它们可能造成在电源层与地层之间造成共振能量*A smaller number of vias also makes it simpler to design the return paths.* 过孔数量少，设计回流路径也会简单许多。

(3)Traces Near Plane Edge基板边缘布线检查Objects of Check:The checked object is as follow s:Wire Check TargetNon wired N/AWired Signal Trace信号走线FIG. 3‑1 Sample PCB Edge Check (PCB Viewed from Top)Co ntents o f Check:This command checks if the target exists farther than the “minimum distance from plane edges” from adjacent pow er and ground plane.待查元件离临近的电源接地层的距离是否比软件设定的“离层边缘最小的距离”要远Tro ubles ho oting errors:Move the trace further from plane outline.移动元件，使之远离层边缘。

* If there is a trace at the plane outline, return current path cannot be kept enough and it causes radiation.如果在层边缘有布线，返回电流路径不能得到保存，将会产生辐射。

(4)Reference Change参考层改变检查Objects of Check:The checked object is as follows:Wire Check TargetNon wired N/AWired Signal Trace信号走线The return current path of the trace on the 1st layer goes to ground plane on the 2nd layer, and the return current path of the trace on the 4th layer goes to power plane on the 3rd layer. In this case, the trace on 1st layer and 4th layer has different return current route, it becomes an error.FIG. 4-1 Sample of Reference Change (PCB Viewed from Side)Co ntents o f Check:This command checks whether the return current path moves to another power and ground plane caused by via existence.这项检查是否由于过孔的存在造成的返回电流路径向其他的电源层和接地层移动。

However, crossing a power or ground plane does not count as an error unless there is a capacitoror via near by discontinued return current path area in order to keep this path.然而，越过电源或者底层会出错，除非在不连续的电流路径周围有电容和过孔来保护这条电流路径。

The capacitor and via to keep return current path against signal via existing within set parameter of “Maximum distance of vias/capacitors to signal trace” becomes check target.在软件设定的“离信号线最大的过孔或者电容距离”范围内，用来使得回流路径排除在存在的信号过孔之外的电容和过孔是检查对象。

Tro ubles ho oting errors:(1) Do not use a via by changing the components and traces layout. 通过改变元件和布线布局来代替使用过孔.(2) Put in a capacitor or via to keep a return current path near the via.放置电容或者过孔来保存电流返回路径* High-speed signal vias are likely to be sources of resonance between power and ground plane.在电源层与地层之间的高速信号过孔可能是产生阻抗的源头.(5)Return Current Path Discontinuity回流路径不连续性检查Objects of Check:The checked object is as follows:Wire Check TargetNon wired N/AWired Signal Trace信号线FIG. 5‑1 Return Current Paths Discontinuity (PCB Viewed from Top)Co ntents o f Check:This command checks whether the return current path running through power/ground plane and SG trace against each net is discontinued.这项检查是否通过电源或者地层和SG线的返回电流路径是不连续的.However, as long as capacitors or SG traces (SG trace vias) exist near the area where return current path is discontinued, these traces are not counted as an error.只要在不连续返回电流路径附近存在电容或者SG线(SG线过孔),这条路径不认为是错误.Capacitors and vias for keeping return current path within the value of “Maximum distance of vias/capacitors to signal trace” becomes target to be checked.More over, even there is a trace crossing over multiple power and ground planes, this command does not count as an error as long as return current path is kept by SG trace.即使有条线通过电源或者地层,旁边有SG线,就不被认为是个错误.Tro ubles ho oting errors:(1) Ignore wires on the slit and SG trace discontinuity by changing components and traces layout.通过改变元件和布线的排版.忽略狭缝上的电线和不连续的SG线Change the component layout and wire path to eliminate discontinuities in the SG trace and wire crossing over slits.改变元件的局部和电线路径来估计在SG布线和跨越狭缝的金属线中存在的不连续性(2) Arrange capacitors to ensure the return path.安置电容确保返回路径的完好.* Discontinuities in the return path increase the area of the current loop.不连续的返回路径会增加电源的环流区域.(6)SG Trace SG布线模式检查Objects of Check:The checked object is as follows:Wire Check TargetNon wired N/AWired Signal Trace(specified in the parameter setting)信号走线FIG. 6-1 Sample SG Trace (PCB Viewed from Top)Co ntents o f Check:This command checks whether SG trace exists along each net. 这项检查是否顺着引脚的周围存在SG布线.Power and ground traces existing within the value of “Maximum spacing between SG traces to signal traces” against target signal trace are considered as SG traces.在SG线和信号线之间的最大空间的范围内存在电源和地布线靠着备查信号线被认为是SG线.The trace being set “ON” by menu [EMI]-[Set Net Property Details] becomes target.路径被设置成”ON”的就是备查的.However, even if there are no SG traces within the value of “(6-3) Permissible area where SG trace does not exist against pins/pads/vias on the signal trace (Set value in all directions)” near pins and pads of the components connected to signal trace and via on the trace, these are not counted as errors.即使在6-3项的数值之内没有SG线的,在路径上连接着信号线和过孔的元件的引脚或基板附近,不存在靠着信号线上的引脚过孔的SG线,不被认为是个错误.Tro ubles ho o ting erro rs:Create SG trace along signal trace.在信号线附近增加SG线* High-speed nets like clock signal are likely to generate radiation and these are required SG trace for suppressing this radiation as well as keeping return current path.高速的信号引脚像时钟信号输入引脚很有可能产生辐射,这些引脚就需要SG线来降低辐射,同时也为了保护返回电流路径.(7)Estimated Radiation 辐射电场检查Objects of Check:The checked object is as follows:Wire Check TargetNon wired The Manhattan length and center point of pin pairsconnected to the net引脚对的曼哈顿长和中间点Wired The wire length between pin pairs and trace locationconnected to the net 引脚对之间的电线长度和与NET连接的布线位置Co ntents o f Check:This command calculates the differential mode and common mode radiation, and checks whether both total value exceeds the set value.A pin pair here refers to a pair of 2 pins on the net.这项检查差分模式和相同模式的辐射.检查是否实际植超过设定值(a) Estimated Differential mode radiation估计差分模式的辐射大小This command checks pins as “driver” other than associated with “receiver”.This calculation is given by differential mode radiation calculated by 3 meter method with following parameter values against check target.For frequency, please set up by menu [EMI]-[Set Net Property Details]. If you do not set up details, set value (Default: 20MHz) by 2.1.14 General will be taken.FIG. 7-1 Equivalent Circuit and formula for Differential Mode Radiation(b) Estimated common mode radiation估测共模辐射This calculation is given by differential mode radiation from the trace itself and common mode radiation from the plane with the trace. 从布线本身给出差分模式和从布线层给出共模辐射Common mode radiation here refers to the radiation by swinging plane of the PCB.这里的共模辐射指代的是通过交换PCB层产生的辐射.FIG. 7-2 Common Mode RadiationIt's possible also to calculate common mode radiation with cables.用电缆计算共模辐射也是可能的The electric fields that couple directly to attached cables from a trace can induce common mode currents on these cables resulting in radiated emissions.从一个路径上的两条线直接附加到电线上的电场会产生共模感应产生辐射发射This calculates them based on algorithm of the Clemson University "MR EMC".If there are cable connectors in the PCB data, please change the parameter (7-17-1) to Yes, designate the cable connector property by the Component Property (2.2.2.2) and check it.如果电缆的连接在PCB数据中，请改变7-17-1的参数值为YES.FIG. 7-3 Common Mode Radiation (Include cable connector)This command calculates differential mode radiation and common mode radiation.计算差分辐射和共模辐射When total value exceeds set value by “EMI Limit of Radiation”, it counts as an error.当总的值超过EMI限定的辐射值，将会报错Also you can customize colors by the level of errors.The method of total value is given as follows;整个值的计算过程在下方列举：(DM: Differential Mode, CM: Common Mode)1.Transfer DM and CM value to voltage.2.Following method gives X and Y (Voltage)DM= 20logXCM= 20logY3.Sum X and YTranslate a value given by process 2 to dB valuee.g.) If DM and CM are both 50dB;50=20logX X=316.22776650=20logY Y=316.227766X+Y= 632.455532Therefore,20log(632.45532) = About 56dBTroubleshooting errors:(1)If differential mode is large, shorten trace length.如果差分辐射过大，减短布线长度。