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UG123: SiOCXO1-EVB Evaluation Board User's GuideThe Skyworks SiOCXO1-EVB (kit) is used to help evaluate Skyworks Jitter Attenua-tor and Network Synchronization products for Stratum 3/3E, IEEE 1588 and G.8262EVB FEATURES:SyncE applications.•Flexible Output Termination•Power Supply Filtering•Optional Output Buffer•Optional OCXO Voltage Control AdjustFigure .1. SiOCXO1-EBUG123: SiOCXO1-EVB Evaluation Board User's Guide • Quick Start1. Quick StartRefer to Figure 3.1 Functional Block Diagram on page 4, Figure 3.2 SiOCXO1-EB Shown Populated with an OCXO on page 4, and Figure 4.1 SiOCXO1-EB Configured with Si5348 EVB on page 6 to clarify the instructions below.1.Connect power to J1, and note that start-up current could be on the order of 1 amp. Check the manufacturers warm-up time.2.Connect SiOCXO1-EB output, J2, to the Si5348 REF clock input using the short SMA cable provided with the EVB kit.2. Top Layer View of BoardFigure 2.1. Top Layer View of BoardUG123: SiOCXO1-EVB Evaluation Board User's Guide • Top Layer View of Board3. Functional DescriptionThe SiOCXO1-EB is used in conjunction with Skyworks precision timing devices to facilitate characterization. The SiOCXO1-EB was designed to maximize output termination configurations as well as optional control voltage terminations. Resistors and capacitors are 0603, which makes it simple to remove and add various values. The SiOCXO1-EB bill of materials and PCB layouts are in Section 7. Bill of Materials and Section 6. Schematic. The block diagram for the board is provided below:Figure 3.1. Functional Block DiagramThe SiOCXO1-EB is intended to be a general use board for a 7-pin OCXO with 22x25 nominal package size, such as the Rakon P/N STP3158 12.8 MHz pictured below. See Section 6. Schematic for example measurements carried out using this OCXO.Figure 3.2. SiOCXO1-EB Shown Populated with an OCXO3.1 Power SupplyThe power supply voltage and current requirements are listed in the manufacturers data sheet. A 3.3 V ±5% supply is required. R6 may require modification if other voltages are used. Also, note the OCXO initial current can be on the order of 1A. Power supply filtering has been added to the evaluation board to minimize spurious response.3.2 Output Termination and Optional BufferIn most applications simple R C termination is used, as seen with R1 and C4 in Figure 6.1 SiOCXO1-EB Schematic on page 8. This is a resistor to optimize impedance matching and a capacitor to block DC. Modifications can be made as required.Optionally a buffer can be added to minimize loading on the OCXO’s output, such as when driving cables. In this case U2, J6, C7, C8, R8, and R9 must be populated, while R2 can be depopulated.3.3 Optional OCXO Frequency AdjustSome OCXO’s have an optional control voltage to adjust the output frequency, usually by a small amount such as 1 or 2 ppm. One example would be to discipline the OCXO to reduce the effects of OCXO aging. In this case, J3 and R4 must be populated as a minimum. C6 can be used for filtering or BW frequency limiting. Alternatively, R5 and C6 could be fixed or adjustable resistors to set a DC bias voltage.4. Configuring the SiOCXO-EBFigure 4.1. SiOCXO1-EB Configured with Si5348 EVBThe connection between the SiOCXO-EB and Si5348 EVB should be kept as short as possible. It is recommended to use a UPS Power Supply back-up for long term testing.UG123: SiOCXO1-EVB Evaluation Board User's Guide • Configuring the SiOCXO-EBUG123: SiOCXO1-EVB Evaluation Board User's Guide • SiOCOXO1-EB Functionality Test5. SiOCOXO1-EB Functionality Test1.Connect power to J1 (3.3 V).2.Connect SiOCXO1-EB Output, J2, to an oscilloscope (terminate into 50 Ω).3.Verify that the red LED is illuminated, the current draw matches closely to the specs, and the output matches the OCXO’s datasheet.5.1 Example Measurement Results Using STP3158LF 12.8 MHz OCXO from RakonTable 5.1. Current Specs for Rakon P/N STP3158 12.8 MHz at U1Notes on Current Settling:1.The system (including the LED and OCXO) initially drew 0.72–0.74 A of current from the 3.3 V power supply. At one minute,the current draw slightly decreased by 0.02–0.04A (warm-up time). Around the minute mark the current decreased rapidly to0.32–0.37A. Then, the system decreased slightly to its consistent steady state current of 0.30 A within 20 minutes.2.The LED draws around 10 mA, so subtract this from the power supply (system) current to get the current draw of the OCXO alone.These are the values reflected in the table above.Steady State Output Waveform for Rakon P/N STP3158 12.8 MHz at U1Verify the output is a 12.8 MHz LVCMOS waveform. For example, measure with a Tektronix TDS 20245, 200 MHz oscilloscope terminated with 50 Ω BNC T connector.6. SchematicFigure 6.1. SiOCXO1-EB SchematicUG123: SiOCXO1-EVB Evaluation Board User's Guide • Schematic7. Bill of MaterialsTable 7.1. SiOCXO1-EB Bill of Materials8. LayoutFigure 8.1. Layer 1: Primary SideFigure 8.2. Layer 2: GroundFigure 8.3. Layer 3: PowerFigure 8.4. Layer 4: Secondary SideCopyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. 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128Mb DDR SDRAM Features•Double data rate architecture: two data transfers per clock cycle•Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver•DQS is edge-aligned with data for reads and is center-aligned with data for writes•Differential clock inputs (CK and CK)•Four internal banks for concurrent operation •Data mask (DM) for write data•DLL aligns DQ and DQS transitions with CK transitions •Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS •Burst lengths: 2, 4, or 8•CAS Latency: 2 / 2.5(DDR333), 2.5 / 3(DDR400)•Auto Precharge option for each burst access •Auto Refresh and Self Refresh Modes•7.8µs Maximum Average Periodic Refresh Interval • 2.5V (SSTL_2 compatible) I/O•V DDQ = V DD = 2.6V ± 0.1V(DDR400)•V DDQ = V DD = 2.5V ± 0.2V (DDR333)•-5/-5T Speed sort; Support PC3200/2700/2100 modules •-6K Speed sort: Supports PC2700/PC2100 modules •-75B Speed sort: Supports PC2100 modulesDescriptionThe 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM.The 128Mb DDR SDRAM uses a double-data-rate architec-ture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2n -bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes.The 128Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.Read and write accesses to the DDR SDRAM are burst ori-ented; accesses start at a selected location and continue for a programmed number of locations in a programmedsequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write com-mand. The address bits registered coincident with the Active command are used to select the bank and row to beaccessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access.The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge func-tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.As with standard SDRAMs, the pipelined, multibank architec-ture of DDR SDRAMs allows for concurrent operation,thereby providing high effective bandwidth by hiding row pre-charge and activation time.An auto refresh mode is provided along with a power-saving Power Down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II com-patible.The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.CAS Latency and FrequencyCAS LatencyMaximum Operating Frequency (MHz)*DDR400(-5/-5T)DDR333(-6K)*DDR266B (-75B)2.51661331003200166133* -6K also meets DDR266A Spec (MHz-CL-tRCD -t RP = 133-2.5-3-3)Pin Configuration - 400mil TSOP II (x4 / x8 / x16)123456910111213147815161718192021226665646362615857565554536059525150494847464523242544434226274140282930313233393837363534V DD DQ0V DDQ NC DQ1V SSQ V DDQ NC DQ3V SSQ NC NC NC DQ2V DDQ NC NC V DD NU NC WE CAS RAS CS NC BA0BA1V SS DQ7V SSQ NC DQ6V DDQ V SSQ NC DQ4V DDQ NC NC NC DQ5V SSQ DQS NC V REF V SS DM*CK CK CKE NC A12A11A9V DD NC V DDQ NC DQ0V SSQ V DDQ NC DQ1V SSQ NC NC NC NC V DDQ NC NC V DD NU NC WE CAS RAS CS NC BA0BA1V SS NC V SSQ NC DQ3V DDQ V SSQ NC DQ2V DDQ NC NC NC NC V SSQ DQS NC V REF V SS DM*CK CK CKE NC A12A11A9A10/APA0A1A2A3V DDA10/APA0A1A2A3V DDA8A7A6A5A4V SSA8A7A6A5A4V SS*DM is internally loaded to match DQ and DQS identically .32Mb x 416Mb x 866-pin Plastic TSOP-II 400mil8Mb x 16V DD DQ0V DDQ DQ1DQ2V SSQ V DDQ DQ5DQ6V SSQ DQ7NC DQ3DQ4V DDQ LDQS NC V DD NU LDM*WE CAS RAS CS NC BA0BA1A10/APA0A1A2A3V DDV SS DQ15V SSQ DQ14DQ13V DDQ V SSQ DQ10DQ9V DDQ DQ8NC DQ12DQ11V SSQ UDQS NC V REF V SS UDM*CK CK CKE NC A12A11A9A8A7A6A5A4V SSInput/Output Functional DescriptionSymbol Type FunctionCK, CK Input Clock:CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-enced to the crossings of CK and CK (both directions of crossing).CKE, CKE0, CKE1Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control of stacked devices.CS, CS0, CS1Input Chip Select: All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in addition to CS0, to allow upper or lower deck selection on stacked devices.RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.DM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-ing a Read, DM can be driven high, low, or floated.BA0, BA1Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.A0 - A12Input Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command.DQ Input/Output Data Input/Output: Data bus.DQS, LDQS, UDQS Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15NC No Connect: No internal electrical connection is present.NU Electrical connection is present. Should not be connected at second level of assembly. V DDQ Supply DQ Power Supply: 2.5V ± 0.2V.V SSQ Supply DQ GroundV DD Supply Power Supply: 2.5V ± 0.2V.V SS Supply GroundV REF Supply SSTL_2 reference voltage: (V DDQ / 2) ± 1%.Ordering InformationOrg.Part Number PackageSpeedComments Clock (MHz)CL-t RCD-t RP Clock (MHz)CL-t RCD-t RP8M x 16N2DS12H16CT-566 pin TSOP-II200 2.5-3-31662-3-3DDR400AN2DS12H16CT-5T2003-3-3166 2.5-3-3DDR400BN2DS12H16CT-6K1663-3-3133 2.5-3-3DDR333/DDR266A N2DS12H16CT-75B1333-3-3100 2.5-3-3DDR266BNote:1. Lead-free and Halogen-free product2. At the present time, there are no plans to support DDR SDRAMs with the QFC function. All reference to QFC are for information onlyBlock Diagram (8Mb x 16)R e c e i v e r s1DQS CK, CK DLLRASCAS CK CS WE CK C o n t r o l L o g i cColumn-Address Counter/LatchMode 9C o m m a n dD e c o d eA0-A12,BA0, BA1CKE 1515I/O Gating DM Mask LogicBank0Memory Array(8192 x 256 x 32)Sense AmplifiersBank1Bank2Bank3138122R e f r e s h C o u n t e r 161616Input Register111113232232clk out DataMask Data CK,COL0COL0COL0clkin M U XDQS Generator161616161632DQ0-DQ15,LDM, UDM LDQS,UDQS1R e a d L a t c hWrite FIFO &DriversNote: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation.Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-rectional DQ and DQS signals.Column Decoder256(x32)R o w -A d d r e s s M U XRegisters138192B a n k 0R o w -A d d r e s s L a t c h & D e c o d e r8192A d d r e s s R e g i s t e rD r i v e r sB a n kC o n t r o l L o g i c13CKFunctional DescriptionThe 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. The 128Mb DDR SDRAM is internally configured as a quad-bank DRAM.The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architec-ture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a pro-grammed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access.Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.InitializationOnly one of the following two conditions must be met.• No power sequencing is specified during power up or power down given the following criteria:V DD and V DDQ are driven from a single power converter outputV TT meets the specificationA minimum resistance of 42 ohms limits the input current from the VTT supply into any pin andV REF tracks V DDQ /2or• The following relationships must be followed:V DDQ is driven after or with V DD such that V DDQ < V DD + 0.3VV TT is driven after or with V DDQ such that V TT < V DDQ + 0.3VV REF is driven after or with V DDQ such that V REF < V DDQ + 0.3VThe DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command.Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH. Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” stateOnce in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or extended mode register can be modified at any valid time during device operation without affecting the state of the internal address refresh counters used for device refresh.Register DefinitionMode RegisterThe Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation.Burst LengthRead and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.Reserved states should not be used, as unknown operation or incompatibility with future versions may result.When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts.Mode Register OperationA8A7A6A5A4CAS Latency A3A2A1A0Burst LengthBTAddress Bus CAS LatencyA6A5A4Latency 000Reserved 001Reserved0102011 3 (Option)100Reserved 101 1.5 (Option)110 2.5111ReservedBurst LengthA2A1A0Burst Length 000Reserved001201040118100Reserved 101Reserved 110Reserved 111ReservedBA1BA0A11A10A90*0*Mode RegisterOperating Mode* BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register).A12 - A9A8A7A6 - A0Operating Mode 000Valid Normal operation Do not reset DLL 010Valid Normal operation in DLL Reset 01VS **Vendor-Specific Test Mode −−−ReservedA3Burst Type 0Sequential 1InterleaveVS ** Vendor SpecificA12Notes:1.For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.2.For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.3.For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.4.Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.Burst TypeAccesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-ing column address, as shown in Burst Definition on page 9.Read LatencyThe Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m.Reserved states should not be used as unknown operation or incompatibility with future versions may result.Burst DefinitionBurst LengthStarting Column Address Order of Accesses Within a BurstA2A1A0Type = SequentialType = Interleaved20 0-10-111-01-04000-1-2-30-1-2-3011-2-3-01-0-3-2102-3-0-12-3-0-1113-0-1-23-2-1-080000-1-2-3-4-5-6-70-1-2-3-4-5-6-70011-2-3-4-5-6-7-01-0-3-2-5-4-7-60102-3-4-5-6-7-0-12-3-0-1-6-7-4-50113-4-5-6-7-0-1-23-2-1-0-7-6-5-41004-5-6-7-0-1-2-34-5-6-7-0-1-2-31015-6-7-0-1-2-3-45-4-7-6-1-0-3-21106-7-0-1-2-3-4-56-7-4-5-2-3-0-11117-0-1-2-3-4-5-67-6-5-4-3-2-1-0Operating ModeThe normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode.All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result.CAS LatenciesExtended Mode RegisterThe Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2. These func-tions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended Mode Register is pro-grammed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation.DLL Enable/DisableThe DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-mal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command can be issued. This is the reason for introducing timing parameter t XSRD for DDR SDRAM’s (Exit Self Refresh to Read Com-mand). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (t MRD) or 10 clocks after the DLL is enabled via self refresh exit command (t XSNR, Exit Self Refresh to Non-Read Command).Output Drive StrengthThe normal drive strength for all outputs is specified to be SSTL_2, Class II.QFC Enable/DisableThe QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature for “elixie” and is not included on all DDR SDRAM devices.Extended Mode Register DefinitionA 8A 7A 6A 5A 4A 3A 2A 1A 0Address Bus Drive StrengthA 1Drive Strength0Normal 1ReservedBA1BA0Operating ModeA 11A 10A 90*1** BA0 and BA1 must be 1, 0 to select the Extended Mode Register Mode RegisterExtendedDSDLLA 0DLL 0Enable 1DisableA12 - A3A2 - A0Operating Mode 0ValidNormal Operation −−All other states Reserved(vs. the base Mode Register)QFCA 2QFC 0Disable 1Enable (Optional)A 12CommandsTruth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each commands follows.Truth Table 1a: CommandsName (Function)CS RAS CAS WE Address MNE Notes Deselect (Nop)H X X X X NOP1, 9 No Operation (Nop)L H H H X NOP1, 9 Active (Select Bank And Activate Row)L L H H Bank/Row ACT1, 3 Read (Select Bank And Column, And Start Read Burst)L H L H Bank/Col Read1, 4 Write (Select Bank And Column, And Start Write Burst)L H L L Bank/Col Write1, 4 Burst Terminate L H H L X BST1, 8 Precharge (Deactivate Row In Bank Or Banks)L L H L Code PRE1, 5 Auto Refresh Or Self Refresh (Enter Self Refresh Mode)L L L H X AR / SR1, 6, 7 Mode Register Set L L L L Op-Code MRS1, 21.CKE is high for all commands shown except Self Refresh.2.BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selectsExtended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.)3.BA0-BA1 provide bank address and A0-A12 provide row address.4.BA0, BA1 provide bank address; A0-A i provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre-charge feature (non-persistent), A10 low disables the Auto Precharge feature.5.A10 LOW: BA0, BA1 determine which bank is precharged.A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”6.This command is auto refresh if CKE is high; Self Refresh if CKE is low.7.Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.8.Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with AutoPrecharge enabled or for write bursts9.Deselect and NOP are functionally interchangeable.Truth Table 1b: DM OperationName (Function)DM DQs NotesWrite Enable L Valid1Write Inhibit H X1ed to mask write data; provided coincident with the corresponding data.DeselectThe Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected.No Operation (NOP)The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.Mode Register SetThe mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode reg-ister descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until t MRD is met.ActiveThe Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank.ReadThe Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses.WriteThe Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location.PrechargeThe Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (t RP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.Auto PrechargeAuto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is non-persistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is determined as if an explicit Precharge command was issued at the earliest possible time without violating t RAS (min). The user must not issue another command to the same bank until the precharge (t RP ) is completed.The DDR SDRAM devices supports the optional t RAS lockout feature. This feature allows a Read command with Auto Pre-charge to be issued to a bank that has been activated (opened) but has not yet satisfied the t RAS (min) specification. The t RAS lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst length of data has been successfully prefetched from the memory array; and two, t RAS (min) has been satisfied.As a means to specify whether a DDR SDRAM device supports the t RAS lockout feature, a new parameter has been defined, t RAP (RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Pre-charge). For devices that support the t RAS lockout feature, t RAP = t RCD (min). This allows any Read Command (with or without Auto Precharge) to be issued to an open bank once t RCD (min) is satisfied.Burst TerminateThe Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write burst cycles are not to be terminated with the Burst Terminate command.t RAP Definition。

标题:【原创】椭圆曲线加密分析：FLEXLM ECC问答[7月16日更新到第7部分]作者:readyu时间: 2012-06-25,19:00:18链接: /showthread.php?t=152615说明：我曾经写过ECCTool用于学习和研究椭圆曲线加密在软件上的应用。

椭圆曲线密码学工具 ECCTooL v1.04原帖年代久远不再更新。

v1.05版本我放在本帖3#。

FLexLM ECC是椭圆曲线签名的一个典型应用，不可不察。

我整理了一下FLEXLM ECC方面的研究心得，准备把它完全写出来。

后面会有算法描述的例子代码。

FLEXLM ECC问答 (1)readyu 2012.61. FLEXLM是个虾米东西？FLEXlm是应用广泛的License管理工具。

宣称数千家EDA工具采用它管理授权。

FLEXlm对厂商来说，它的优点是证书管理功能强大，支持平台众多。

对最终用户来说，它的缺点是不够友好，比如Windows下，经常由于某些原因，flexlm服务启动错误。

对于破解者来说，它有着为数众多的教本。

维基百科上的条目为：/wiki/FLEXlmFLEXLM本来属于GLOBEtrotter。

Macrovision曾经收购GLOBEtrotter。

2006年的时候，FLEXLM原来的开发组跑路，另起灶头，产品叫RLM。

/index.php2008年Macrovision把FLEXLM卖了。

现在叫FlexNet Publisher。

/products/flexnet-publisher.htm2. FLexLM 的ECC（椭圆曲线加密）怎么来的？早期的flexlm采用的常规加密，不安全，能被做出lic。

这样的教程是很多的。

flexlm的安全性完全得不到保障，所以，自 v8(大约2001-2002)版本引入了公钥加密算法：椭圆曲线加密。

从此，它一直是flexlm的金钟罩。

包括v9(2003-) , v10(2004-) , v11(2007-), 到最新的版本 v11.10 (2012) 。

Function pushbutton1_Callback(hObject, eventdata, handles)global x y Y Lmax Myh dirth dirtd dirtr dirtt chaerrorpersistent error if isempty(error)error=0;endx=1:30;T=100*rand(30,40);for i=1:15;x1=mean(x(i));endfor i=16:30;x2=mean(x(i));endrowave=cumsum(T,2)/10;for i=1:15;y1=mean(rowave(i)) ;endfor i=16:30;y2=mean(rowave(i)) ;endm=(y2-y1)/(x2-x1);b=y1-m*x1;y=m*x+b;axes(handles.axes1)plot(x,rowave(i),'rx',x,y);for i=1:30;l(i)=rowave(i)-y(i);endmaxx=sort(l,2,'descend');lmaxz=maxx(1);lmaxf=maxx(30);Lmax=1/2*(abs(lmaxz)+abs(lmaxf));e=0;f1=0;g=0;h=0;for i=1:30;ei=x(i)*y(i);e=e+ei;f1=f1+x(i);g=g+y(i);h=h+x(i)^2;endM=(30*e-f1*g)/29*f1;B=1/30*(g-M*f1);Y=M*x+B;Yfs=M*max(x)+B;axes(handles.axes2) plot(x,rowave(i),'*',x,Y);cla(handles.axes3);for i=1:15;for j=1:40;yui(i)=sqrt((1/59)*sumsqr(Y(i)-y1));endendfor i=16:30;for j=1:40;ydt(i-15)=sqrt((1/59)*sumsqr(Y(i)-y2));endendMyui=max(yui);Mydt=max(ydt);MM=max(Myui,Mydt);for i=1:15;yh(i)=1/2*(yui(i)-ydt(i));endMyh=max(yh);K=rand;C=abs(Lmax)+abs(Myh)+K*MM;A=C/abs(Yfs);u=fix(rand(1)*30);for i=1:30;dirtl=rowave(u)-Y(u);endif u>15u=u-15;elseend%t=abs(fix(randn*15));dirth=sqrt(1/15*sumsqr(yui(u)));dirtd=sqrt(1/15*sumsqr(ydt(u)));dirtr=sqrt(mean(dirth^2+dirtd^2));dirtt=sqrt(dirth^2+dirtd^2+dirtr^2);error=error+1;if error>1endset(handles.nonline_text,'string','0.00');set(handles.chizhi_text,'string','0.00');set(handles.chongfu_text,'string','0.00');set(handles.zonghe_text,'string','0.00');function pushbutton2_Callback(hObject, eventdata,handles)% hObject handle to pushbutton2 (see GCBO)global x y Y Lmax Myh dirth dirtd dirtr dirttchaerrorcla(handles.axes1);cla(handles.axes2);set(handles.axes3,'Visible','on');set(handles.text2,'Visible','off');set(handles.text7,'Visible','off');axes(handles.axes3) % Select the proper axes plot(x,y,x,Y,'r*');set(handles.axes3,'XMinorTick','on')grid onset(handles.nonline_text,'String',num2str(Lmax)); set(handles.chizhi_text,'string',num2str(Myh)); set(handles.chongfu_text,'string',num2str(dirtr)); set(handles.zonghe_text,'string',num2str(dirtt));xx=xlsread('a1','A2:A11');x=xx';x;T=xlsread('a1','B2:K11');xxf1=xlsread('a1','A2:A6');xf1=xxf1';x1=mean(xf1);xxf2=xlsread('a1','A7:A11');xf2=xxf2';x2=mean(xf2);。