毕业设计(论文)-基于fpga的函数信号发生器的设计与实现[管理资料]

基于FPGA的函数信号发生器的设计与实现

摘要

波形发生器己成为现代测试领域应用最为广泛的通用仪器之一，代表了信号源的发展方向。直接数字频率合成(DDS)是二十世纪七十年代初提出的一种全数字的频率合成技术，其查表合成波形的方法可以满足产生任意波形的要求。由于现场可编程门阵列(FPGA)具有高集成度、高速度、可实现大容量存储器功能的特性，能有效地实现DDS技术，极大的提高函数发生器的性能，降低生产成本。

本文首先介绍了函数波形发生器的研究背景和DDS的理论。然后详尽地叙述了用FPGA完成DDS模块的设计过程，接着分析了整个设计中应处理的问题，根据设计原理就功能上进行了划分，将整个仪器功能划分为控制模块、外围硬件、FPGA器件三个部分来实现。最后就这三个部分分别详细地进行了阐述。

本文利用Altera的设计工具QuartuSH并结合VeI’i1og一HDL语言，采用硬件编程的方法很好地解决了这一问题。论文最后给出了系统的测量结果，并对误差进行了一定分析，结果表明，，、三角波、锯齿波、方波，通过实验结果表明，本设计达到了预定的要求，并证明了采用软硬件结合，利用FPGA技术实现波形发生器的方法是可行的。

关键词:函数发生器，直接数字频率合成，现场可编程门阵列

The Design and Realize of DDS Based on FPGA

Abstract

Arbitrary Waveform Generator(AWG) is one of the most popular

instruments in modern testing domains，Which represents the developing

direction of signal sources· Direct Digital frequency Synthesis(DDS) advance

dearly in full digital technology for frequency synthesis，its LUT method for

synthes waveform .Adapts togenerate arbitrary Waveform· Field programable

GateArray(FPGA)has the feature sof Iargeseale integration,high working

frequency and ean realize lal’ge Memory,50FPGAeaneffeetivelyrealizeDDS.

The of Corporation Altera ehosen to do the main digitalProcessing

work，which based on its large sale and highs Peed. The 53C2440MCU

ehosenasa control ehip· Inthisdesign,how to design the fpga chip and theInter

faee between the FPGA and the control ehiP the the method of

Software and hardware Programming,the design used the software Quartus11

and languageverilog一 HDL solves ，the PrineiPle of DDS and Basis of

EDA technology introdueed Problem is the design are analyzed and the

whole fun into three Parts:masterehiP，FPGA deviee and PeriPheral three

Parts are described indetail disadvantage and thing sneed toadv anceareal

Of the dissertation,or asquare wave with in the frequency range

to20MHz .Planed and the way to use software and hardware Programming

method and DDS Technology to realize Functional Waveform

Generatoravailable.

Keywords:DDS;FPGA;Functional Waveform Generator

目 录 第一章 绪论 ................................................ IV

............................................................................................................... IV

................................................................................................................. V

......................................................................................................... V

....................................................................................................... VI

.............................................................................................................. VII

...................................................................................................... VII

DMA输出方式 .......................................................................... VII

...................................................................................................... VII

..................................................................................................... VIII

第二章 直接数字频率合成器的原理及性能 ................................................ I

.................................................................................................................. I

.......................................................................................................... I

......................................................................................................... II

DDS原理 ............................................................................................. III

第三章 基于FPGA的DDS模块的实现 .......................................................... I

(FPGA)简介 ............................................................................................. I

II软件并建立工程 ....................................................................... II

新建Block Diagram/Schematic File并添加模块电路。 .......... IV

建立VHDL编程模块 ................................................................ VI

生成Vector Waveform File ........................................................ VII

................................................................................................................. X

....................................................................................................... XI

..................................................................................................... XIII

..................................................................................................... XIII

第4章 模块生成及仿真 ................................................................................ I

相位累加器模块 .................................................................................... I