datasheet

PROCESS CONDITIONS
FILTER SEPERATOR 1
NATURAL GAS Min. 101,200 ~ Max. 786,000
P0 Rev
2006.11.30 Date
Issued for Approval Description
Q. Xi Reapaired by
B. He Checked by
RECONDENSER DATA SHEET
Owner: Project No.: Project Name: Location: SERVICE OF UNIT NO. OF UNITS PROCESS DESIGN DATA FLUID ALLOCATION INLET CONDITION FLUID NAME FLUID FLOW PER ONE UNIT WORKING TEMPERATURE DESIGN TEMPERATURE WORKING PRESSURE DESIGN PRESSURE DENSITY VISCOSITY MOLECULAR WEIGHT OUTLET CONDITION FLUID NAME FLUID FLOW PER ONE UNIT, WORKING TEMPERATURE DESIGN TEMPERATURE WORKING PRESSURE DESIGN PRESSURE DENSITY VISCOSITY MOLECULAR WEIGHT GAS COMPOSITION MOL% NITROGEN METHANE ETHANE PROPANE i-BUTANE n-BUTANE i-PENTANE n-PENTANE NOTES 0.00 85.12 8.63 4.14 1.10 0.90 0.10 0.01 kg/hr DegC DegC Mpa.g Mpa.g kg/m3 cP "-170/140 0.81 1.77 420.7 ~ 478 kg/hr DegC DegC Mpa.g Mpa.g kg/m3 cP NATURAL GAS Min. 100,000 ~ Max. 765,000 -157 -170 0.81 1.77 TYPICAL 478 0.167 19.32 GAS Page No. Item No. Service No.Required 1 of 4 D-406A/B Recondenser Two(2)

U E D P R O D U C T E F E R E N C E O N L Y .U250 f o r n e w d e s i g n Data Sheet 27621.40The A3150JLT and A3150JUA programmable switches provide tooth/valley recognition in large gear-tooth sensing applications. Each sensor consists of a single element, chopper-stabilized Hall-effect IC that can be programmed to the desired magnetic switch point, opti-mizing sensor airgap and timing accuracy performance after final packaging. The small package can be easily assembled and used in conjunction with a wide variety of gear/target shapes and sizes. The two devices differ only in package style.The sensing technology used for this sensor is Hall-effect based.The sensor incorporates a single-element Hall IC that switches inresponse to magnetic signals created by a ferrous target. The program-mability of the circuit eliminates magnet and system offsets such as those caused by tilt yet provides zero-speed detection capabilities without the associated running jitter inherent in classical digital solu-tions.A proprietary dynamic offset cancelation technique, with an internal high-frequency clock, reduces the residual offset voltage,which is normally caused by device overmolding, temperaturedependancies, and thermal stress. This technique produces devices that have an extremely stable quiescent output voltage, are immune to mechanical stress, and have precise recoverability after temperature cycling. Many problems normally associated with low-level analog signals are minimized by having the Hall element and amplifier in a single chip. Output precision is obtained by internal gain adjustments during the manufacturing process and operate-point programming in the user’s application.This sensor system is ideal for use in gathering speed, position, and timing information using gear-tooth-based configurations. TheA3150JLT/JUA are particularly suited to those applications that require accurate duty cycle control or accurate edge detection. The lower vibration sensitivity also makes these devices extremely useful for transmission speed sensing.3150Always order by complete part number: the prefix 'A' + the basic four-digit part number + a suffix to indicate operating temperature range +a suffix to indicate package style, e.g., A3150JLT .PROGRAMMABLE, CHOPPER-STABILIZED, HALL-EFFECT SWITCHContinued next page115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-********PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHCopyright © 2000, Allegro MicroSystems, Inc.Two package styles provide a magnetically opti-mized package for most applications. Suffix ‘–LT’ is a miniature SOT-89/TO-243AA transistor package for surface-mount applications; while suffix ‘–UA’ is a three-lead ultra-mini-SIP for through-hole mounting.FEATURES AND BENEFITSs Chopper Stabilized forExtremely Low Switch-Point Drift and Immunity to Mechanical Stresss Externally Programmed Switch Point s On-Chip Supply-Transient Protection s Output Short-Circuit Protections Single-Chip Sensing IC for High Reliability s Small Mechanical Size s <50µs Power-On Times Wide Operating Voltage Range s Defined Power-On State3150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHLimitsCharacteristic Symbol Test ConditionsMin.Typ.Max.Units Operate PointB OPProgrammable offset range 500670850G Initial (before programming)02040G Resolution8.01114G ∆B OPV CC = 14 V, after programming, B OP ≈ 500 G-358.0+35G HysteresisB hys5.02035GNOTE: Typical data is at V CC = 5 V and T A = +25°C and is for design information only.ELECTRICAL CHARACTERISTICS over operating voltage and temperature range (unless otherwise noted).LimitsCharacteristic Symbol Test Conditions Min.Typ.Max.Units Supply Voltage V CC Operating, T J < 165°C4.25–26V Power-On State POS After programming, V CC = 0 ¡ 5 V HIGH HIGH HIGH –Low Output Voltage V OUT(SAT)I OUT = 20 mA –175400mV Output Current Limit I OUTM V OUT = 12 V 658095mA Output Leakage Current I OFF V OUT = 24 V–0.210µA Supply CurrentI CCBefore programming, output OFF – 4.07.0mA Before programming, output ON– 5.08.0mA Reverse Supply Current I RCC V RCC = -30 V ––-5.0mA Power-On Delay t on V CC > 5 V–2050µs Output Rise Time t r R L = 820 Ω, C L = 20 pF –200–ns Output Fall Time t f R L = 820 Ω, C L = 20 pF–100–ns Clock Frequency f C –340–kHz Zener Voltage V Z I ZT = 100 µA, T A = 25°C 2732–V Zener Impedancez zI ZT = 10 mA, T A = 25°C –50100ΩNOTE: Typical data is at V CC = 5 V and T A = +25°C and is for design information only.MAGNETIC CHARACTERISTICS over operating supply voltage and temperature ranges.115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHTYPICAL ELECTRICAL CHARACTERISTICS255075100AMBIENT TEMPERATURE IN °C-50Dwg. GH-053-2125-25S U P P L Y C U R R E N T I N m A5.04.03.02.01.015010152025SUPPLY VOLTAGE IN VOLTSDwg. GH-041-25S U P P L Y C U R R E N T I N m A10300AMBIENT TEMPERATURE IN °C200Dwg. GH-040-4S A T U R A T I O N V O L T A G E I N m V3150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHFUNCTIONAL DESCRIPTIONChopper-Stabilized Technique. These devices use a proprietary dynamic offset cancellation technique, with an internal high-frequency clock to reduce the residual offset voltage of the Hall element that is normally caused by device overmolding, temperature dependencies, and thermal stress.This technique produces devices that have an extremely stable quiescent Hall output voltage, are immune to thermal stress, and have precise recoverability after temperature cycling. Thistechnique will also slightly degrade the device output repeatabil-ity.The Hall element can be considered as a resistor arraysimilar to a Wheatstone bridge. A large portion of the offset is a result of the mismatching of these resistors. The chopper-stabilizing technique cancels the mismatching of the resistors by changing the direction of the current flowing through the Hall plate and Hall voltage measurement taps, while maintaining the Hall-voltage signal that is induced by the external magnetic flux.The signal is, then, captured by a sample-and-hold circuit.Operation. The output of these devices switches low (turns ON) when a magnetic field (south pole) perpendicular to the Hall sensor exceeds the operate point threshold (B OP ). After turn-ON, the output is capable of sinking 25 mA and the output voltage is V OUT(SAT). When the magnetic field is reduced below the release point (B RP ), the device output goes high (turns OFF).The difference in the magnetic operate and release points is the hysteresis (B hys ) of the device. This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise.Applications. It is strongly recommended that an external bypass capacitor be connected (in close proximity to the Hall sensor) between the supply and ground of the device to reduce both external noise and noise generated by the chopper-stabiliza-tion technique.The simplest form of magnet that will operate these devices is a bar magnet with the south-seeking pole towards the branded surface of the device. Many other methods of operation are possible. Extensive applications information on magnets and Hall-effect sensors is also available in the Allegro Electronic Data Book AMS-702 or Application Note 27701, orO U T P U T V O L T A G EFLUX DENSITYDwg. GH-007-2115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHPROGRAMMING PROTOCOLThe A3150JLT and A3150JUA operate points are pro-grammed by serially addressing the device through the supply terminal (pin1). After the correct operate point is determined, the device programming bits are selected and then a “lock” set to prevent any further (accidental)programming.Program Enable. To program the device, a sequence of pulses is used to activate/enable the addressing mode as shown in figure 1. This sequence of a V PP pulse, at least seven V PH pulses, and a V PP pulse with no supply interrup-tions, is designed to prevent the device from being pro-grammed accidentally (for example, as a result of noise on the supply line).VV V Dwg. WH-013Figure 1 — Program enablePROGRAMMING PROTOCOL over operating temperature range.LimitsCharacteristic Symbol DescriptionMin.Typ.Max.Units Programming VoltageV PL Minimum voltage during programming4.55.0 5.5V V PH 9.01011V V PP202325V Programming Current I PP Max. supply current during programming –250–mA Pulse Widtht d(0)OFF time between bits20––µs t d(1)Enable, address, program, or lock bit ON time 20––µs t dPProgram pulse ON time 100300–µs Pulse Rise Time t r V PL to V PH or V PP 11––µs Pulse Fall Timet fV PH or V PP to V PL 5.0––µsNOTE: Typical data is at T A = +25°C and is for design information only.3150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCH* In application, the terms “gear” and “target” are often interchanged. However, “gear” is preferred when motion is transferred.Address Determination. The operate point is adjust-able in 64 increments. With the appropriate target or gear*in position, the 64 switch points are sequentially selected (figure 2) until the required operate point is reached. Note that the difference between the operate point and the release point (hysteresis) is a constant for all addresses.Set-Point Programming. After the desired set-point address is determined (0 through 63), each bit of theequivalent binary address is programmed individually. For example, as illustrated in figure 3, to program address code 5 (binary 000101), bits 1 and 3 need to be programmed.Each bit is programmed during the wide V PP pulse and is not reversible.Lock Programming. After the desired set point is programmed, the program lock is then activated (figure 4)to prevent further programming of the device.V PV 0Dwg. WH-014A D D R E S S 0A D D R E S S 1A D D R E S S 2A D D R E S S N (UP T O 63)A D D R E S S N -1A D D R E S S N -2Figure 2 — Address determinationFigure 4 — Lock programmingV V VDwg. WH-016Figure 3 — Set-point programmingV V V Dwg. WH-015A115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHAll Allegro sensors are subjected to stringent qualification requirements prior to being released to production.To become qualified, except for the destructive ESD tests, no failures are permitted.CRITERIA FOR DEVICE QUALIFICATIONQualification Test Test Method and Test Conditions Test Length SamplesComments Biased Humidity (HAST)T A = 130°C, RH = 85%50 hrs 77V CC = V OUT = 5 V High-Temperature JESD22-A108,408 hrs77V CC = 24 V,Operating Life (HTOL)T A = 150°C, T J = 165°C V OUT = 20 V Accelerated HTOLJESD22-A108,504 hrs 77V CC = 24 V,T A = 175°C, T J = 190°C V OUT = 20 VAutoclave, Unbiased JESD22-A102, Condition C,96 hrs 77T A = 121°C, 15 psig High-Temperature MIL-STD-883, Method 1008,1000 hrs 77(Bake) Storage Life T A = 170°CTemperature CycleMIL-STD-883, Method 1010,500 cycles 77-65°C to +150°C Latch-Up—Pre/Post 6Reading Electro-Thermally—Pre/Post 6Induced Gate Leakage Reading ESD,CDF-AEC-Q100-002Pre/Post x per Test to failure,Human Body Model Reading test All leads > TBDElectrical DistributionsPer Specification—303150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHSENSOR LOCATIONS(±0.005” [0.13 mm] die placement)Package Designators “UA” and "UA-TL"Although sensor location is accurate to three sigma for a particular design, product improvements may result in small changes to sensor location.Dwg. MH-008-80.030"0.76 mm NOMDwg. MH-011-9APackage Designator “LT”115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCH0.440.35PACKAGE DESIGNATOR 'LT'(SOT-89/TO-243AA)Dimensions in Inches (for reference only)Dimensions in Millimeters (controlling dimensions)Dwg. MA-012-3 mmPads 1, 2, 3, and B — Low-Stress VersionPads 1, 2, and 3 only — Lowest Stress, But Not Self AligningNOTE: Exact body and lead configuration at vendor’s option within limits shown.Dwg. MA-012-3 inads 1, 2, 3, and B — Low-Stress Versionads 1, 2, and 3 only — Lowest Stress, But Not Self Aligning3150 PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCH Surface-Mount Lead Form (Suffix '-TL')Dimensions in Inches (controlling dimensions)Dimensions in Millimeters (for reference only)PACKAGE DESIGNATOR 'UA'Dwg. MH-014E mm1.27BSC°Dwg. MH-014E inBSC°NOTES: 1.Tolerances on package height and width represent allowable mold offsets. Dimensions given are measured at the widest point (parting line).2.Exact body and lead configuration at vendor’s option within limits shown.3.Height does not include mold gate flash.4.Recommended minimum PWB hole diameter to clear transition area is 0.035” (0.89 mm).5.Where no tolerance is specified, dimension is nominal.115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHThe products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283;5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719;5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, ormanufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.Allegro products are not authorized for use as critical components in life-support appliances, devices, or systems without express written approval.The information included herein is believed to be accurate andreliable. However, Allegro MicroSystems, Inc. assumes no responsibil-ity for its use; nor for any infringements of patents or other rights of third parties that may result from its use.。

GENERAL DESCRIPTIONOB2279 is a highly integrated current mode PWM control IC optimized for high performance, low standby power and cost effective offline flyback converter applications. PWM switching frequency at normal operation is externally programmable and trimmed to tight range. At no load or light load condition, the IC operates in extended ‘burst mode’ to minimize switching loss. Lower standby power and higher conversion efficiency is thus achieved. VDD low startup current and low operating current contribute to a reliable power on startup design with OB2279. A large value resistor could thus be used in the startup circuit for reduced power loss. The internal slope compensation improves system large signal stability and reduces the possible sub-harmonic oscillation at high PWM duty cycle output. Leading-edge blanking on current sense input removes the signal glitch due to snubber circuit diode reverse recovery and greatly reduces the externalcomponent count and system cost in the design.OB2279 offers comprehensive protection coverageincluding Cycle-by-Cycle current limiting(OCP),VDD Under Voltage Lockout(UVLO), VDD OverVoltage Protection(OVP), VDD Clamp, Gate Clamp,Over Load protection(OLP) and Over Temperatureprotection (OTP), etc.Different latch shutdown options are offered onOB2279 in different device version. V version has OVP Latch shutdown. T version supports both OVP and OTP latch shutdown. L version provides all OVP, OTP and OLP latch shutdown control. Excellent EMI performance is achieved with On-Bright proprietary frequency shuffling technique together with soft switching control at the totem pole gate drive output. Tone energy at below 20KHZ is minimized in operation. Consequently, audio noise is eliminated during operation.OB2279 is offered in SOP-8 and DIP-8 packages.FEATURES■ On-Bright Proprietary Frequency Shuffling Technology for Improved EMI Performance ■ Power On Soft Start■ Extended Burst Mode Control For Improved Efficiency and Minimum Standby Power Design ■ Audio Noise Free Operation■ External Programmable PWM Switching Frequency ■ Internal Synchronized Slope Compensation■ Low VIN/VDD Startup Current(3uA) and Low Operating Current (2.3mA)■ Leading Edge Blanking on Current Sense Input ■ Complete Protection Coverage with selective protections for Latch Shutdown o VDD Over Voltage Protection(OVP) – LatchShutdown o Over Temperature Protection(OTP) – Auto recovery or Latch Shutdowno Over Load Protection. (OLP) – Auto recovery or Latch Shutdown o VDD Under Voltage Lockout with Hysteresis (UVLO) o Gate Output Voltage Clamp (16.5V) o Built-in OCP Compensation to Achieve Minimum OPP Variation over Universal AC Input Range. APPLICATIONSOffline AC/DC flyback converter for ■ Adaptor ■ Notebook Adaptor ■ LCD Monitor/TV/PC/Set-Top Box PowerSupplies■ Open-frame SMPS ■ Printer Power TYPICAL APPLICATIONOn -B ri g h tC o nf i de n ti al ToH ig hr ayGENERAL INFORMATIONPin ConfigurationThe pin map of OB2279 in DIP8 and SOP8 package is shown as below.Ordering Information Part Number Description OB2279AP-V DIP8, V version with OVPLatchOB2279AP-T DIP8, T version withOVP/OTP latchOB2279AP-L DIP8, L version withOVP/OTP/OLP latchOB2279CP-V SOP8, V version with OVPlatchOB2279CP-T SOP8, T version withOVP/OTP latchOB2279CP-LSOP8, L version with OVP/OTP/OLP latchNote: All Devices are offered in Pb-free Package if not otherwisenoted.Package Dissipation Rating PackageR θJA (°C/W)DIP8 90 SOP8 150Absolute Maximum RatingsParameter Value VDD Clamp Voltage 35 V VDD Clamp Continuous Current10 mA V FB Input Voltage -0.3 to 7V V SENSE Input Voltage to Sense Pin-0.3 to 7V V RT Input Voltage to RT Pin -0.3 to 7V V RI Input Voltage to RI Pin -0.3 to 7V Min/Max Operating Junction Temperature T J-20 to 150 o C Min/Max Storage Temperature T stg-55 to 150 o C Lead Temperature (Soldering, 10secs)260 o C Note: Stresses beyond those listed under “absolute maximumratings” may cause permanent damage to the device. These are stress ratings only, functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.On -B ri g h tC o nf i de n ti al ToH ig hr ayMarking InformationTERMINAL ASSIGNMENTSPin Num Pin Name I/O Description 1 GND P Ground 2 FB I Feedback input pin. PWM duty cycle is determined by voltage level into thispin and current-sense signal level at Pin 6.3 VIN I Connected through a large value resistor to rectified line input for Startupand line voltage sensing.4 RI I Internal Oscillator frequency setting pin. A resistor connected between RIand GND sets the PWM frequency.5 RT I Dual function pin. Either connected through a NTC resistor to GND for overtemperature shutdown control or used as latch shutdown control input.6 SENSE I Current sense input pin. Connected to MOSFET current sensing resistornode.7 VDD P DC power supply pin. 8 GATE O Totem-pole gate drive output for power MOSFET.On -B ri g h tCo nf i de n ti al ToH ig hr ayBLOCK DIAGRAMRECOMMENDED OPERATING CONDITIONSymbol Parameter Min Max UnitVDD VDD Supply Voltage 11.5 25 V RI RI Resistor Value 100 133 Kohm T A Operating Ambient Temperature-20 85o COn -B ri gh tC o nf i de n ti al ToH ig hr ayELECTRICAL CHARACTERISTICS(T A = 25O C if not otherwise noted)Symbol Parameter Test Conditions Min Typ Max Unit Supply Voltage (VDD) I_VDD_Startup VDD Start up Current VDD =15V, RI=100K Measure current into VDD3 20 uAI_VDD_Ops Operation Current VDD =16V, RI=100Kohm, V FB =3V2.3 mAUVLO(Enter) VDD Under Voltage Lockout Enter8.8 9.8 10.8 VUVLO(Exit) VDD Under Voltage Lockout Exit (Startup)15.5 16.5 17.5 VOVP(Latch)VDD Over Voltage Latch Trigger26.5 28 29.5 VOVP(De-Latch) VDD Latch Release Voltage Threshold7.5 VI(Vdd)_latch VDD bleeding current at latch shutdown when VDD = 9V45 uA T D _OVP VDD OVP Debounce timeRI = 100Kohm 80 uSecV DD _Clamp V DD Zener Clamp Voltage RI = 100 Kohm, I(V DD ) = 5 mA35 VT_Softstart Soft Start Time 3 mSec Feedback Input Section(FB Pin)A VCS PWM Input Gain ΔV FB /ΔV cs2.8 V/V V FB_Open V FB Open Voltage VDD = 16V 6.2VI FB _Short FB pin short circuit current Short FB pin to GND, measure current0.75 mAV TH _0D Zero Duty Cycle FB Threshold Voltage VDD = 16V, RI=100Kohm0.95 VV TH _BM Burst Mode FB Threshold Voltage1.6 VV TH _PL Power Limiting FB Threshold Voltage4.4 VT D _PL Power limiting Debounce Time VDD = 16V, RI=100Kohm80 mSecZ FB _IN Input Impedance 9.0 Kohm Current Sense Input(Sense Pin) T_blanking Sense Input Leading Edge Blanking TimeRI = 100Kohm 300 nSecZ SENSE _IN Sense Input Impedance30 KohmT D _OC Over Current Detection and Control DelayCL=1nf at GATE, RI=100Kohm 70 nSecV TH _OC_0 Current LimitingThreshold at NoCompensationVDD = 16V, I(VIN) = 0uA, RI=100Kohm 0.85 0.90 0.95 V On -B ri g h tC o nf i de n ti al ToH ig hr ayV TH _OC_1 Current Limiting Threshold at CompensationVDD = 16V, I(VIN) = 150uA, RI=100Kohm 0.80 VOscillator F OSC Normal Oscillation FrequencyRI = 100Kohm 60 65 70 KHZ∆f_TempCentral Frequency Temperature Stability VDD = 16V, RI=100Kohm, -20oC to100 o C3 % ∆f_VDDCentral Frequency Voltage Stability VDD = 12-28V, RI=100Kohm3 % RI_range Operating RI Range 50 100 250 Kohm V_RI_open RI open voltage VDD = 16V 2.0 V F_BM Burst Mode Base Frequency VDD = 16V, RI=100Kohm20 KHZGate Drive Output VOL Output Low Level VDD = 16V, Io = 20 mA 0.3 V VOH Output High Level VDD = 16V, Io = 20 mA 11 V VG_Clamp Output Clamp Voltage Level16.5 VT_r Output Rising Time VDD = 16V, CL = 1nf 120 nSec T_f Output Falling Time VDD = 16V, CL = 1nf 50 nSec Over Temperature Protection I_RT Output Current of RT pin VDD = 16V, RI=100Kohm70 uAV TH _OTP OTP Threshold Voltage VDD = 16V, RI=100Kohm1.015 1.065 1.115 VV TH _OTP_off (Version V Only) OTP Recovery Threshold Voltage VDD = 16V, RI=100Kohm 1.165 V V TH _RT_latch (Version V Only) RT Input Latch Threshold Voltage 0.6 V T D _OTP OTP De-bounce Time VDD = 16V, RI=100Kohm100 uSecV_RT_Open RT Pin Open Voltage VDD = 16V, RI=100Kohm3.7 VFrequency Shuffling∆f_OSCFrequency Modulation range /Base frequencyRI =100Kohm -3 3 % Freq_Shuffling Shuffling Frequency RI = 100Kohm 32 HZOn -B ri gh tC o nf i de n ti al ToH ig hr ayri g ToigOPERATION DESCRIPTIONOB2279 is a highly integrated PWM controller IC optimized for offline flyback converter applications with requirement in latch shutdown or auto recovery. The extended burst mode control greatly reduces the standby power consumption and helps the design easily meet the international power conservation requirements. z Startup Current and Start up ControlStartup current of OB2279 is designed to be very low so that VDD could be charged up above UVLO(exit) threshold level and device starts up quickly. A large value startup resistor can therefore be used to minimize the power loss yet reliable startup in application. For a typical AC/DC adaptor with universal input range design, a 2 M Ω, 1/8 Wstartup resistor could be used together with a VDDcapacitor to provide a fast startup and yet lowpower dissipation design solution.z Operating CurrentThe Operating current of OB2279 is low at 2.3mA.Good efficiency is achieved with OB2279 lowoperating current together with extended burstmode control schemes.z Frequency shuffling for EMI improvementThe frequency Shuffling/jittering (switchingfrequency modulation) is implemented in OB2279.The oscillation frequency is modulated with ainternally generated random source so that the toneenergy is evenly spread out. The spread spectrumminimizes the conduction band EMI and thereforeeases the system design in meeting stringent EMIrequirement.z Burst Mode OperationAt zero load or light load condition, most of thepower dissipation in a switching mode powersupply is from switching loss on the MOSFETtransistor, the core loss of the transformer and theloss on the snubber circuit. The magnitude ofpower loss is in proportion to the number ofswitching events within a fixed period of time.Reducing switching events leads to the reductionon the power loss and thus conserves the energy.OB2279 self adjusts the switching mode accordingto the loading condition. At from no load tolight/medium load condition, the FB input dropsbelow burst mode threshold level. Device entersBurst Mode control. The Gate drive output switchesonly when VDD voltage drops below a preset leveland FB input is active to output an on state.Otherwise the gate drive remains at off state tominimize the switching loss thus reduce the standby power consumption to the greatest extend. The nature of high frequency switching also reduces the audio noise at any loading conditions. z Oscillator Operation A resistor connected between RI and GND sets the constant current source to charge/discharge theinternal cap and thus the PWM oscillator frequency is determined. The relationship between RI and switching frequency follows the below equation within the specified RI in Kohm range at nominal loading operational condition. )()(6500Khz Kohm RI F OSC = z Current Sensing and Leading Edge Blanking (LEB) Cycle-by-Cycle current limiting is offered in OB2279 current mode PWM control. The switch current is detected by a sense resistor into the sense pin. An internal leading edge blanking circuit chops off the sense voltage spike at initial MOSFET on state due to snubber diode reverse recovery so that the external RC filtering on sense input is no longer needed. The current limit comparator is disabled and cannot turn off the external MOSFET during the blanking period. The PWM duty cycle is determined by the current sense input voltage and the FB input voltage. z Internal Synchronized Slope Compensation Built-in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM generation. This greatly improves the close loop stability at CCM and prevents the sub-harmonic oscillation and thus reduces the output ripple voltage. z Over Temperature Protection with Latch Shutdown(Only to T and L version) A NTC resistor in series with a regular resistor should connect between RT and GND for temperature sensing and protection. NTC resistor value becomes lower when the ambient temperature rises. With the fixed internal current I RT flowing through the resistors, the voltage at RT pin becomes lower at high temperature. The internal OTP circuit is triggered and shutdown the MOSFET when the sensed input voltage is lower than V TH _OTP. OTP is a latched shutdown. On -B ri g h tC o nf i de n ti al ToH ig hr ayz RT Pin Used as Latch Shutdown InputControlRT pin could also be used as a control input to implement system latch shutdown function.An example is to implement system OVP protection with a latch shutdown function through a photo coupler and affiliated circuits. When OVP detection signal connected to RT is lower than V TH _OTP for Version T/L device, (or V TH _OT_Latch for Version V), OB2279 controls system into latch shutdown. The recovery of the AC/DC system could only start by resetting internal latch when VDD voltage drops below VDD_De-latch value. This could be achieved by unplugging/re-plugging of AC source in AC start-up configuration.z Gate DriveOB2279 Gate is connected to the Gate of an external MOSFET for power switch control. Too weak the gate drive strength results in higher conduction and switch loss of MOSFET while too strong gate drive output compromises the EMI.Good tradeoff is achieved through the built-in totem pole gate drive design with right output strength and dead time control. The low idle loss and good EMI system design is easier to achieve with this dedicated control scheme. An internal 16.5V clamp is added for MOSFET gate protection at higher than expected VDD input.z Protection Controls Good system reliability is achieved with OB2279’s rich protection features including Cycle-by-Cycle current limiting (OCP), Over Load Protection (OLP) with auto-recovery(V and T version) or latch shutdown(L version), over temperature protection (OTP) with auto-recovery(V version) or latch shutdown(T and L version), on-chip VDD over voltage protection (OVP) with latch shutdown and under voltage lockout (UVLO).VDD OVP protection is a latched shutdown in OB2279.The OCP threshold value is self adjusted lower at higher current into VIN pin. This OCP threshold slope adjustment helps to compensate the increased output power limit at higher AC voltage caused by inherent Over-Current sensing and control delay. A constant output power limit is achieved with recommended OCP compensation scheme.At output overload condition, FB voltage is set higher. When FB input exceeds power limit threshold value for more than 80mS, control circuit reacts to turnoff the power MOSFET. This is so called OLP shutdown. It is either auto-recovery or latched shutdown depending on version of OB2279. Similarly, control circuit shutdowns the power MOSFET when an Over Temperature condition is detected. This shutdown is either auto-recovery or latched depending on version of OB2279 been used. VDD is supplied with transformer auxiliary winding output. It is clamped when VDD is higher than 35V. MOSFET is shut down when VDD drops below UVLO(enter) limit and device enters power on start-up sequence thereafter.On -B ri g h tC o nf i de n ti al ToH ig hr ayPACKAGE MECHANICAL DATA8-Pin Plastic DIPOn -B ri g h tC o nf i de n ti al ToH ig hr ay8-Pin Plastic SOPO n -B r i g h t C o nf i d e n t i a l ToH ig hr ayIMPORTANT NOTICERIGHT TO MAKE CHANGESOn-Bright Electronics Corp. reserves the right to make corrections, modifications, enhancements, improvements and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.WARRANTY INFORMATIONOn-Bright Electronics Corp. warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with its standard warranty. Testing and other quality control techniques are used to the extent it deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.On-Bright Electronics Corp. assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using On-Bright’s components, data sheet and application notes. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.LIFE SUPPORTOn-Bright Electronics Corp.’s products are not designed to be used as components in devices intended to support or sustain human life. On-bright Electronics Corp. will not be held liable for any damages or claims resulting from the use of its products in medical applications.MILITARYOn-Bright Electronics Corp.’s products are not designed for use in military applications. On-Bright Electronics Corp. will not be held liable for any damages or claims resulting from the use of its products in military applications.On -B ri g h tC o nf i de n ti al ToH ig hr ay。

Low Cost Low Power Instrumentation AmplifierAD620Rev. GInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 FEATURESEasy to useGain set with one external resistor (Gain range 1 to 10,000)Wide power supply range (±2.3 V to ±18 V) Higher performance than 3 op amp IA designs Available in 8-lead DIP and SOIC packaging Low power, 1.3 mA max supply current Excellent dc performance (B grade) 50 µV max, input offset voltage 0.6 µV/°C max, input offset drift 1.0 nA max, input bias current100 dB min common-mode rejection ratio (G = 10) Low noise9 nV/√Hz @ 1 kHz, input voltage noise 0.28 µV p-p noise (0.1 Hz to 10 Hz) Excellent ac specifications120 kHz bandwidth (G = 100) 15 µs settling time to 0.01%APPLICATIONSWeigh scalesECG and medical instrumentation Transducer interface Data acquisition systems Industrial process controlsBattery-powered and portable equipmentCONNECTION DIAGRAM–IN R G –V S+IN R G+V S OUTPUTREFTOP VIEW00775-0-001Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) PackagesPRODUCT DESCRIPTIONThe AD620 is a low cost, high accuracy instrumentationamplifier that requires only one external resistor to set gains of 1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and DIP packaging that is smaller than discrete designs and offers lower power (only 1.3 mA max supply current), making it a good fit for battery-powered, portable (or remote) applications. The AD620, with its high accuracy of 40 ppm maximumnonlinearity, low offset voltage of 50 µV max, and offset drift of 0.6 µV/°C max, is ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces.Furthermore, the low noise, low input bias current, and low power of the AD620 make it well suited for medical applications, such as ECG and noninvasive blood pressure monitors.The low input bias current of 1.0 nA max is made possible with the use of Superϐeta processing in the input stage. The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV/√Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band, and 0.1 pA/√Hz input current noise. Also, the AD620 is well suited for multiplexed applications with its settling time of 15 µs to 0.01%, and its cost is low enough to enable designs with one in-amp per channel.30,0005,00010,00015,00020,00025,000T O T A L E R R O R , P P M O F F U L L S C A L ESUPPLY CURRENT (mA)00000Figure 2. Three Op Amp IA Designs vs. AD620SOURCE RESISTANCE (Ω)R T I V O L T A G E N O I S E (0.1– 10H z ) (µV p -p )00000Figure 3. Total Voltage Noise vs. Source ResistanceAD620TABLE OF CONTENTSSpecifications (3)Absolute Maximum Ratings (5)ESD Caution (5)Typical Performance Characteristics (7)Theory of Operation (13)Gain Selection (16)Input and Output Offset Voltage (16)Reference Terminal (16)Input Protection (16)RF Interference (16)Common-Mode Rejection (17)Grounding (17)Ground Returns for Input Bias Currents (18)Outline Dimensions (19)Ordering Guide (20)REVISION HISTORY12/04—Rev. F to Rev. GUpdated Format..................................................................Universal Change to Features. (1)Change to Product Description (1)Changes to Specifications (3)Added Metallization Photograph (4)Replaced Figure 4-Figure 6 (6)Replaced Figure 15 (7)Replaced Figure 33 (10)Replaced Figure 34 and Figure 35 (10)Replaced Figure 37 (10)Changes to Table 3 (13)Changes to Figure 41 and Figure 42 (14)Changes to Figure 43 (15)Change to Figure 44 (17)Changes to Input Protection section (15)Deleted Figure 9 (15)Changes to RF Interference section (15)Edit to Ground Returns for Input Bias Currents section (17)Added AD620CHIPS to Ordering Guide....................................19 7/03—Data Sheet changed from REV. E to REV. FEdit to FEATURES (1)Changes to SPECIFICATIONS (2)Removed AD620CHIPS from ORDERING GUIDE (4)Removed METALLIZATION PHOTOGRAPH (4)Replaced TPCs 1–3 (5)Replaced TPC 12 (6)Replaced TPC 30 (9)Replaced TPCs 31 and 32 (10)Replaced Figure 4 (10)Changes to Table I (11)Changes to Figures 6 and 7 (12)Changes to Figure 8 (13)Edited INPUT PROTECTION section (13)Added new Figure 9 (13)Changes to RF INTERFACE section (14)Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS section (15)Updated OUTLINE DIMENSIONS (16)AD620 SPECIFICATIONSTypical @ 25°C, V S = ±15 V, and R L = 2 kΩ, unless otherwise noted.Table 1.AD620A AD620B AD620S1Parameter ConditionsMin Typ Max Min Typ Max Min Typ Max Unit GAIN G = 1 + (49.4 kΩ/R G)Gain Range 1 10,000 1 10,000 1 10,000Gain Error2V OUT = ±10 VG = 1 0.03 0.10 0.01 0.02 0.03 0.10 %G = 10 0.15 0.30 0.10 0.15 0.15 0.30 %G = 100 0.15 0.30 0.10 0.15 0.15 0.30 %G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 % Nonlinearity V OUT = −10 V to +10 VG = 1–1000 R L = 10 kΩ 10 40 10 40 10 40 ppmG = 1–100 R L = 2 kΩ 10 95 10 95 10 95 ppm Gain vs. TemperatureG = 1 10 10 10 ppm/°C>12−50 −50 −50 ppm/°C GainVOLTAGE OFFSET (Total RTI Error = V OSI + V OSO/G)30 125 15 50 30 125 µV Input Offset, V OSI V S = ±5 Vto ± 15 VOvertemperature V S = ±5 V185 85 225 µV to ± 15 V0.3 1.0 0.1 0.6 0.3 1.0 µV/°CAverage TC V S = ±5 Vto ± 15 VOutput Offset, V OSO V S = ±15 V 400 1000 200 500 400 1000 µV V S = ± 5 V 1500 750 1500 µV Overtemperature V S = ±5 V2000 1000 2000 µV to ± 15 V5.0 15 2.5 7.0 5.0 15 µV/°CAverage TC V S = ±5 Vto ± 15 VOffset Referred to theInput vs. Supply (PSR) V S = ±2.3 Vto ±18 VG = 1 80 100 80 100 80 100 dBG = 10 95 120 100 120 95 120 dBG = 100 110 140 120 140 110 140 dBG = 1000 110 140 120 140 110 140 dB INPUT CURRENTInput Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA Overtemperature 2.5 1.5 4 nA Average TC 3.0 3.0 8.0 pA/°C Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA Overtemperature 1.5 0.75 2.0 nA Average TC 1.5 1.5 8.0 pA/°C INPUTInput ImpedanceDifferential 10||2 10||2 10||2 GΩ_pF Common-Mode 10||2 10||2 10||2 GΩ_pF−V S + 1.9 +V S − 1.2 −V S + 1.9 +V S − 1.2 −V S + 1.9 +V S − 1.2 V Input Voltage Range3V S = ±2.3 Vto ±5 VOvertemperature −V S + 2.1 +V S − 1.3 −V S + 2.1 +V S − 1.3 −V S + 2.1 +V S − 1.3 V V S = ± 5 V−V S + 1.9 +V S − 1.4 −V S + 1.9 +V S − 1.4 −V S + 1.9 +V S − 1.4 V to ±18 VOvertemperature −V S + 2.1 +V S − 1.4 −V S + 2.1 +V S + 2.1 −V S + 2.3 +V S − 1.4 VAD620AD620A AD620B AD620S1Parameter ConditionsMin Typ Max Min Typ Max Min Typ Max Unit1 See Analog Devices military data sheet for 883B tested specifications.2 Does not include effects of external resistor R G.3 One input grounded. G = 1.4 This is defined as the same supply range that is used to specify PSR.AD620ABSOLUTE MAXIMUM RATINGSTable 2.Parameter RatingSupply Voltage ±18 VInternal Power Dissipation 1 650 mWInput Voltage (Common-Mode) ±V SDifferential Input Voltage 25 VOutput Short-Circuit Duration IndefiniteStorage Temperature Range (Q) −65°C to +150°CStorage Temperature Range (N, R) −65°C to +125°COperating Temperature Range AD620 (A, B) −40°C to +85°C AD620 (S) −55°C to +125°C Lead Temperature Range (Soldering 10 seconds) 300°C1Specification is for device in free air: 8-Lead Plastic Package: θJA = 95°C 8-Lead CERDIP Package: θJA = 110°C 8-Lead SOIC Package: θJA = 155°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performancedegradation or loss of functionality.AD62000775-0-004Figure 4. Metallization Photograph. Dimensions shown in inches and (mm). Contact sales for latest dimensions.AD620TYPICAL PERFORMANCE CHARACTERISTICS(@ 25°C, V S = ±15 V , R L = 2 kΩ, unless otherwise noted.)INPUT OFFSET VOLTAGE (µV)20304050P E R C E N T A G E O F U N I T S1000775-0-005Figure 5. Typical Distribution of Input Offset VoltageINPUT BIAS CURRENT (pA)1020304050–600600P E R C E N T A G E O F U N I T S–1200120000775-0-006Figure 6. Typical Distribution of Input Bias Current1020304050INPUT OFFSET CURRENT (pA)P E R C E N T A G E O F U N I T S00775-0-Figure 7. Typical Distribution of Input Offset Current TEMPERATURE (°C)I N P U T B I A S C U R R E N T (n A )+I B–I B2.0–2.0175–1.0–1.5–75–0.500.51.01.51257525–2500775-0-008Figure 8. Input Bias Current vs. TemperatureC H A N G E I N O F F S E T V O L T A G E (µV )1.50.5WARM-UP TIME (Minutes)2.0011.0432500775-0-009Figure 9. Change in Input Offset Voltage vs. Warm-Up TimeFREQUENCY (Hz)V O L T A G E N O I S E (n V / H z )00775-0-010Figure 10. Voltage Noise Spectral Density vs. Frequency (G = 1−1000)AD620FREQUENCY (Hz)1000100101101000100C U R R E N T N O I S E (f A / H z )00775-0-011Figure 11. Current Noise Spectral Density vs. FrequencyR T IN O I S E (2.0µV /D I V )TIME (1 SEC/DIV)00775-0-012Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) R T I N O I S E (0.1µV /D I V )TIME (1 SEC/DIV)00775-0-013Figure 13. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) 00775-0-014Figure 14. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div1001000AD620AFET INPUT IN-AMPSOURCE RESISTANCE (Ω)T O T A L D R I F T F R O M 25°C T O 85°C , R T I (µV )100,000101k10M10,00010k1M100k 00775-0-015Figure 15. Total Drift vs. Source ResistanceFREQUENCY (Hz)C M R (d B )16001M80401600.1140100120100k 10k 1k 100102000775-0-016Figure 16. Typical CMR vs. Frequency, RTI, Zero to 1 kΩ Source ImbalanceAD620FREQUENCY (Hz)P S R (d B )1601M80401600.1140100120100k 10k 1k 100102018000775-0-017Figure 17. Positive PSR vs. Frequency, RTI (G = 1−1000)FREQUENCY (Hz)P S R (d B )1601M80401600.1140100120100k10k1k 100102018000775-0-018Figure 18. Negative PSR vs. Frequency, RTI (G = 1−1000)100010010M10011k10100k 1M 10k FREQUENCY (Hz)GA I N (V /V )0.100775-0-019Figure 19. Gain vs. Frequency O U T P U T V O L T A G E (V p -p )FREQUENCY (Hz)351551030202500775-0-020Figure 20. Large Signal Frequency ResponseI N P U T V O L T A G E L I M I T (V )(R E F E R R E D T OS U P P L Y V O L T A G E S )SUPPLY VOLTAGE ± Volts+V S –V S 00775-Figure 21. Input Voltage Range vs. Supply Voltage, G = 120501510SUPPLY VOLTAGE ± VoltsO U T P U T V O L T A G E S W I N G (V )(R E F E R R E D T O S U P P L Y V O L T A G E S )+V S –V S 00775-0Figure 22. Output Voltage Swing vs. Supply Voltage, G = 10AD620O U T P U T V O L T A G E S W I N G (V p -p )LOAD RESISTANCE (Ω)300010k20101001k00775-0-023Figure 23. Output Voltage Swing vs. Load Resistance00775-0-024Figure 24. Large Signal Pulse Response and Settling TimeG = 1 (0.5 mV = 0.01%)00775-0-025Figure 25. Small Signal Response, G = 1, R L = 2 kΩ, C L= 100 pF00775-0-026Figure 26. Large Signal Response and Settling Time, G = 10 (0.5 mV = 0.01%)00775-0-027Figure 27. Small Signal Response, G = 10, R L = 2 kΩ, C L = 100 pF00775-0-030Figure 28. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%)00775-0-029Figure 29. Small Signal Pulse Response, G = 100, R L = 2 kΩ, C L = 100 pF00775-0-030Figure 30. Large Signal Response and Settling Time,G = 1000 (0.5 mV = 0.01% )00775-0-031Figure 31. Small Signal Pulse Response, G = 1000, R L = 2 kΩ, C L = 100 pF OUTPUT STEP SIZE (V)S E T T L I N G T I M E (µs )TO 0.01%TO 0.1%2002155510101500775-0-032Figure 32. Settling Time vs. Step Size (G = 1)GAINS E T T L I N G T I M E (µs )1000111000100101010000775-0-033Figure 33. Settling Time to 0.01% vs. Gain, for a 10 V Step00775-0-034Figure 34. Gain Nonlinearity, G = 1, R L = 10 kΩ (10 µV = 1 ppm)00775-0-035Figure 35. Gain Nonlinearity, G = 100, R L = 10 kΩ(100 µV = 10 ppm)00775-0-036Figure 36. Gain Nonlinearity, G = 1000, R L = 10 kΩ(1 mV = 100 ppm)1k Ω10k Ω*ALL RESISTORS 1% TOLERANCE00Figure 37. Settling Time Test CircuitTHEORY OF OPERATIONS REF775--38Figure 38. Simplified Schematic of AD620The AD620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately(to 0.15% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit. The input transistors Q1 and Q2 provide a single differential-pair bipolar input for high precision (Figure 38), yet offer 10× lower input bias current thanks to Superϐeta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1 and Q2, thereby impressing the input voltage across the external gain setting resistor R G. This creates a differential gain from the inputs to the A1/A2 outputs given by G = (R1 + R2)/R G + 1. The unity-gain subtractor, A3, removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. The value of R G also determines the transconductance of the preamp stage. As R G is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gain related errors. (b) The gain-bandwidth product (determined by C1 and C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of9 nV/√Hz, determined mainly by the collector current and base resistance of the input devices.The internal gain resistors, R1 and R2, are trimmed to an absolute value of 24.7 kΩ, allowing the gain to be programmed accurately with a single external resistor.The gain equation is then14.49+Ω=GRkG14.49−Ω=GkRGMake vs. Buy: a Typical Bridge Application Error Budget The AD620 offers improved performance over “homebrew” three op amp IA designs, along with smaller size, fewer components, and 10× lower supply current. In the typical application, shown in Figure 39, a gain of 100 is required to amplify a bridge output of 20 mV full-scale over the industrial temperature range of −40°C to +85°C. Table 3 shows how to calculate the effect various error sources have on circuit accuracy.Regardless of the system in which it is being used, the AD620 provides greater accuracy at low power and price. In simple systems, absolute accuracy and drift errors are by far the most significant contributors to error. In more complex systems with an intelligent processor, an autogain/autozero cycle will remove all absolute accuracy and drift errors, leaving only the resolution errors of gain, nonlinearity, and noise, thus allowing full 14-bit accuracy.Note that for the homebrew circuit, the OP07 specifications for input voltage offset and noise have been multiplied by √2. This is because a three op amp type in-amp has two op amps at its inputs, both contributing to the overall input error.PRECISION BRIDGE TRANSDUCER00775-0-039AD620A MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 100SUPPLY CURRENT = 1.3mA MAX00775-0-040Figure 39. Make vs. Buy"HOMEBREW" IN-AMP, G = 100*0.02% RESISTOR MATCH, 3ppm/°C TRACKING **DISCRETE 1% RESISTOR, 100ppm/°C TRACKING SUPPLY CURRENT = 15mA MAX0000Table 3. Make vs. Buy Error BudgetError, ppm of Full Scale Error SourceAD620 Circuit Calculation “Homebrew” Circuit Calculation AD620 Homebrew ABSOLUTE ACCURACY at T A = 25°CInput Offset Voltage, µV 125 µV/20 mV(150 µV × √2)/20 mV 6,250 10,607 Output Offset Voltage, µV 1000 µV/100 mV/20 mV ((150 µV × 2)/100)/20 mV 500 150 Input Offset Current, nA 2 nA ×350 Ω/20 mV(6 nA ×350 Ω)/20 mV18 53 CMR, dB 110 dB(3.16 ppm) ×5 V/20 mV (0.02% Match × 5 V)/20 mV/100 791 500Total Absolute Error 7,559 11,310DRIFT TO 85°CGain Drift, ppm/°C(50 ppm + 10 ppm) ×60°C 100 ppm/°C Track × 60°C 3,600 6,000 Input Offset Voltage Drift, µV/°C 1 µV/°C × 60°C/20 mV(2.5 µV/°C × √2 × 60°C)/20 mV3,000 10,607 Output Offset Voltage Drift, µV/°C 15 µV/°C × 60°C/100 mV/20 mV (2.5 µV/°C × 2 × 60°C)/100 mV/20 mV 450 150Total Drift Error 7,050 16,757RESOLUTIONGain Nonlinearity, ppm of Full Scale40 ppm40 ppm40 40 Typ 0.1 Hz to 10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × √2)/20 mV 14 27 Total Resolution Error 54 67Grand Total Error 14,663 28,134G = 100, V S = ±15 V .(All errors are min/max and referred to input.)Figure 40. A Pressure Monitor Circuit that Operates on a 5 V Single SupplyPressure MeasurementAlthough useful in many bridge applications, such as weigh scales, the AD620 is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant.Figure 40 shows a 3 kΩ pressure transducer bridge powered from 5 V . In such a circuit, the bridge consumes only 1.7 mA. Adding the AD620 and a buffered voltage divider allows the signal to be conditioned for only 3.8 mA of total supply current. Small size and low cost make the AD620 especially attractive for voltage output pressure transducers. Since it delivers low noise and drift, it will also serve applications such as diagnostic noninvasive blood pressure measurement.Medical ECGThe low current noise of the AD620 allows its use in ECGmonitors (Figure 41) where high source resistances of 1 MΩ or higher are not uncommon. The AD620’s low power, low supply voltage requirements, and space-saving 8-lead mini-DIP and SOIC package offerings make it an excellent choice for battery-powered data recorders.Furthermore, the low bias currents and low current noise, coupled with the low voltage noise of the AD620, improve the dynamic range for better performance.The value of capacitor C1 is chosen to maintain stability of the right leg drive loop. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm.Figure 41. A Medical ECG Monitor CircuitPrecision V-I ConverterThe AD620, along with another op amp and two resistors, makes a precision current source (Figure 42). The op amp buffers the reference terminal to maintain good CMR. The output voltage, V X , of the AD620 appears across R1, which converts it to a current. This current, less only the input bias current of the op amp, then flows out to the load.V IN+V 00775-0-044Figure 42. Precision Voltage-to-Current Converter (Operates on 1.8 mA, ±3 V)GAIN SELECTIONThe AD620’s gain is resistor-programmed by R G , or moreprecisely, by whatever impedance appears between Pins 1 and 8. The AD620 is designed to offer accurate gains using 0.1% to 1% resistors. Table 4 shows required values of R G for various gains. Note that for G = 1, the R G pins are unconnected (R G = ∞). For any arbitrary gain, R G can be calculated by using the formula:14.49−Ω=G k R GTo minimize gain error, avoid high parasitic resistance in series with R G ; to minimize gain drift, R G should have a low TC—less than 10 ppm/°C—for the best performance.Table 4. Required Values of Gain Resistors1% Std Table Value of R G (Ω) Calculated Gain 0.1% Std Table Value of R G (Ω ) Calculated Gain 49.9 k 1.990 49.3 k 2.002 12.4 k 4.984 12.4 k 4.984 5.49 k 9.998 5.49 k 9.998 2.61 k 19.93 2.61 k 19.93 1.00 k 50.40 1.01 k 49.91 499 100.0 499 100.0 249 199.4 249 199.4 100 495.0 98.8 501.0 49.9991.049.31,003.0INPUT AND OUTPUT OFFSET VOLTAGEThe low errors of the AD620 are attributed to two sources,input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains, and the output errors dominate at low gains. The total V OS for a given gain is calculated asTotal Error RTI = input error + (output error/G) Total Error RTO = (input error × G) + output errorREFERENCE TERMINALThe reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output, with an allowable range of 2 V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR.INPUT PROTECTIONThe AD620 features 400 Ω of series thin film resistance at itsinputs and will safely withstand input overloads of up to ±15 V or ±60 mA for several hours. This is true for all gains and power on and off, which is particularly important since the signal source and amplifier may be powered separately. For longer time periods, the current should not exceed 6 mA(I IN ≤ V IN /400 Ω). For input overloads beyond the supplies, clamping the inputs to the supplies (using a low leakage diode such as an FD333) will reduce the required resistance, yielding lower noise.RF INTERFERENCEAll instrumentation amplifiers rectify small out of band signals. The disturbance may appear as a small dc voltage offset. High frequency signals can be filtered with a low pass R-C network placed at the input of the instrumentation amplifier. Figure 43 demonstrates such a configuration. The filter limits the input signal according to the following relationship:)2(21C D DIFF C C R FilterFreq +π=CCM RC FilterFreq π=21where C D ≥10C C.C D affects the difference signal. C C affects the common-mode signal. Any mismatch in R × C C will degrade the AD620’s CMRR. To avoid inadvertently reducing CMRR-bandwidth performance, make sure that C C is at least one magnitudesmaller than C D . The effect of mismatched C C s is reduced with a larger C D :C C ratio.Figure 43. Circuit to Attenuate RF Interference COMMON-MODE REJECTIONInstrumentation amplifiers, such as the AD620, offer high CMR, which is a measure of the change in output voltage when both inputs are changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance.For optimal CMR, the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 44 and Figure 45 show active data guards that are configured to improve ac common-mode rejections by “bootstrapping” the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs.V OUT775--46Figure 44. Differential Shield DriverOUT775--47Figure 45. Common-Mode Shield Driver GROUNDINGSince the AD620 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the REF pin to the appropriate “local ground.”To isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (Figure 46). It would be convenient to use a single ground line; however, current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be tied together at some point, usually best at the ADC package shown in Figure 46.DIGITALDATAOUTPUT775--48Figure 46. Basic Grounding PracticeGROUND RETURNS FOR INPUT BIAS CURRENTSInput bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents. Therefore, when amplifying “floating” input sources, such as transformers or ac-coupled sources, there must be a dc path from each input to ground, as shown in Figure 47, Figure 48, and Figure 49. Refer to A Designer’s Guide to Instrumentation Amplifiers (free from Analog Devices) for more information regarding in-amp applications.Figure 47. Ground Returns for Bias Currents with Transformer-Coupled InputsTO POWER SUPPLY GROUND+V 00775-0-050Figure 48. Ground Returns for Bias Currents with Thermocouple InputsFigure 49. Ground Returns for Bias Currents with AC-Coupled InputsOUTLINE DIMENSIONSCOMPLIANT TO JEDEC STANDARDS MS-001-BA0.070 (1.78)0.060 (1.52)0.045 (1.14)MAXCONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8).Dimensions shown in inches and (millimeters)CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN0.005 (0.13)0.055 (1.40)Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8)Dimensions shown in inches and (millimeters)CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGNCOMPLIANT TO JEDEC STANDARDS MS-012AAFigure 52. 8-Lead Standard Small Outline Package [SOIC]Narrow Body (R-8)Dimensions shown in millimeters and (inches)。