国立台湾大学High-Speed_CMOS_Circuit_Techniques_for_Broadband_Communications
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1 Overdrive to switch current (~250 mV) 1 Overdrive for current source (~250 mV)
Supply reduction will stop at 0.7~0.8V if we have nothing better than CML.
1 ω1 = L1C ω 2 = 2 ω1 24 6 ω3 = R1C ω 3dB 3.9 = R1C
π-Peaking Network [Jin, ’08]
Application of Inductive Peaking
High-Speed Selector [Lee, ’05]
Pushing internal bandwidth to speed up switching. Applicable to other CML switching circuits.
Difficulties of Distributed Amplifier
Transmission Line Loss
Top metal thickness < 1μm in nano-scale CMOS tech.
For Q = 7, wave amplitude halves after λ/2 propagation
Fundamental Oscillation Theory
Atot = 40 dB
Atot = 50 dB
For a given technology, gain × bandwidth constant
BWtot = GBW 1/n 2 1 1/n Atot
Atot = 60 dB
nopt = 2 lnAtot (but usually we have n≦5 )
The Past and The Future
1950
2000
Year
CMOS Device in 5-10 Years Gate oxide > 1nm (otherwise tunneling) Channel length > 10x gate oxide (otherwise no gate control)
Triple-Resonance Architecture [Galal, ’04]
1 ω1 = L1C ω 2 = 2 ω1 ω 3 = 4 6 ω1
Resp R1C
Alternative Dual-Resonance Peaking
Reversed TRA [Liao, ’08] Double Series [Kim, ’05]
Switching energy = 1.25 eV. 12 electrons in one node!
Supply Limitations on High-Speed Circuits
BER=10
－12
SNR=14 250 mV
Pe,tot = ∫
∞
V0 σ n
VPP 1 x2 dx = Q ( exp ) 2 2σ n 2π
Powerful technique. No extra power dissipation. Area consuming.
Dual-Resonance Peaking
Triple-Resonance Architecture [Galal, ’04]
1 ω1 = L1C ω 2 = 2 ω1 ω 3 = 4 6 ω1
Uncertain output swing and dc level Finite current goes through RF unless ISS1RD1 = ISS2RD2
Other Broadband Techniques
Multi-Stage
fT Doubler
Vout = gm (Vin1 Vin2 )RD
Insufficient Gain / Complex Routing
Most DAs provide gain < 15dB
Not efficient in area using
Loss-Compensation
Stage-Reuse Architecture
[Moez,’07] [Arbabian, ’08]
Applications at Ultra High Frequencies
60 GHz Indoor Comm. 77 GHz 94 GHz Automotive Cloud Radars
O2
140 GHz P-to-P Comm.
O2
20 Gb/s 40 Gb/s 100 Gb/s
H2O
Backplane Optical Links Ethernet
Evolution of PLL Circuits
Extending the Bandwidth by Cascading
Cascading identical gain stages
BWtot = ω 0 21/n 1
Gain increases faster than bandwidth decreases.
[Shigematsu, ’02]
Cascaded Segments
Av = gm Z 0L l n ≈ πf T 2 v
Voltage gain proportional to length l (i.e., number of stages) Ideally infinite gain and infinite bandwidth
CMOS Boundaries
Voltage Limitation V V In sub-threshold, ID = I S e nkT / q (1 e kT / q )(1 + λVDS ) For inverter with reasonable gain, VDD,min = 100 mV.
High-Speed CMOS Circuit Techniques for Broadband Communications
Jri Lee Electrical Engineering Department National Taiwan University
Outline
Introduction Broadband Amplifiers Design Considerations High-Speed Techniques VCOs Cross-Coupled Colpitts mm-Wave Associated Frequency Dividers Static Regenerative Injection-Locked Conclusion
ω 3dB
2 3 = R1C
Dual-Resonance Peaking
Triple-Resonance Architecture [Galal, ’04]
1 ω1 = L1C ω 2 = 2 ω1 ω 3 = 4 6 ω1
Response Analysis:
ω 3dB
2 3 = R1C
Dual-Resonance Peaking
Response Analysis:
ω 3dB
2 3 = R1C
Dual-Resonance Peaking
Triple-Resonance Architecture [Galal, ’04]
1 ω1 = L1C ω 2 = 2 ω1 ω 3 = 4 6 ω1
Response Analysis:
Minimum device length ~ 10 nm!
Forecast the future “640k ought to be enough for anybody”- Bill Gates, 1981 “No exponential is forever... but we can delay 「forever」” - Gordon Moore, 2003
Challenges of CMOS Cherry-Hooper Amplifiers
High supply
Incompetent current source/source follower (also need CMFB) Resistive load becomes the only possibility Gain degrades. (still IR drop)
Capacitive Degeneration
Three poles, two zeros. The second zero extends the gain boosting by canceling the first pole.
Distributed Amplifier
Cascode with peaking
Scrambler or encoder removes the near-dc power
Offset cancellation introduces one zero and one pole. Lower corner defined by standards.
Inductive Peaking
Offset-Cancellation Technique
[Vos,in Vos,outGmFR1 ]A = Vos,out
Vos,out = ≈ A Vos,in 1 + AGmFR1 Vos,in GmFR1
(Offset reduced by A)
Vout AGmR1(1 + sCFRF ) = Vin 1 + AGmFR1 + sCFRF
Active Feedback
Miller Cap. Cancellation M7-M8
