high-speed burst-mode optical interconnects for photonic packet communication

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3:30pm - 4:OOpm (Invited)

WBBl High-speed Burst-Mode Optical Interconnects for

Photonic Packet Communications Keishi Habara and Yoshiaki Yamada NTT Network Innovation Laboratories

1-1 , Hikarino-oka, Yokosuka-shi, Kanagawa 239-0847, JAPAN

TEL+81-468-59-8305 FAX:+81-468-55-1282 E-mail: habara@exa.onlab.ntt.co.jp

Introduction A packet switch with capacity of more than 1 Tbit/s will be required in the near future to meet the exponential growth of the Internet and intranet traffic. In such packet switching networks, burst-mode optical interconnects running at 10 Gbit/s are necessary because high-speed optical packets arrive in bursts at the receiver side. [l]

The signal power fluctuates rapidly with each packet in a switching time of a few nano-seconds. Conventional receiver cannot follow the threshold to the optimum in such a short time, and therefore suffers a large penalty from the rapid power-fluctuations. To solve this problem, DC-coupled optical-packet receivers employing an automatic threshold tracking circuit (ATC) have been demonstrated. [2] However, a DC-coupled receiver is inferior in sensitivity to an AC-coupled one. The rapid timing-fluctuation is the other crucial problem in photonic-packet communications. The PLL clock

recovery circuit, which is commonly used for 3R-function in a conventional receiver cannot be used in packet communication because the long synchronization time compared with a packet length deteriorates the utilization efficiency of the transmission line. This paper describes a differential receiver which is capable of handling fast power fluctuations and also describes a digital-ring oscillator for handling rapid timing-fluctuations. [3,4] Differential receiver for level fluctuation Figure 1 shows the configuration of the differential receiver, which features synchronous decoding. The receiver consists of a differential-O/E part and a synchronous decoding part. We evaluated a tolerance to the rapid power fluctuation of the differential receiver. A test-pattern-generator created lO-Gbit/s Manchester-encoded optical data packets, each of which had 480 bits of 15th-stage pseudo- random data payload and an overhead of 32-bit zeros. And an electro-absorption modulator integrated with a DFB

laser-diode created a power difference between consecutive optical packets. Figure 2 shows a transition from a high-level packet to a low-level packet. The eye diagram of the incoming

signal is shown in Fig. 2 (a). Obviously, the high-level and low-level packets have different optimum thresholds.

The differential signal shown in Fig. 2 (b), however, has a common threshold for signal regeneration. Figure 2 (c) shows a signal regenerated by the synchronous decoder. Figure 3 shows bit-error rate performances of the experimental receiver with and without power fluctuation. The optical power was measured at the input of an erbium-doped fiber amplifier (EDFA). The bit-error-rate performance was measured to the data payloads of smaller-power packets. The receiver sensitivity (without fluctuation) was -34.4 dBm. With a power-fluctuation of up to 10 dB, the power-penalty of the smaller packet

was less than 1 dB. However, the power-penalty of 2.2 dB was observed with 13-dB fluctuation. Digital-ring oscillator for timing fluctuation We have proposed a digital-ring oscillator (DR-OSC), which is capable of ultra-fast clock synchronization. [4] We assumed that each burst consists of a short preamble for synchronization and a data payload. The clock recovery circuit instantaneously synchronizes the preamble, and the synchronized clock regenerates the data payload. We developed a 1-chip DR-OSC IC for STM64 (f = 9.95328GHz) using silicon bipolar HSST.[5] As shown in Fig. 4, the IC comprises input data buffers, two AND/NAND gates, a 50-ps internal-delay buffer, and a differential output driver. By changing the length of the external delay line, the resonate frequency can be coarsely selected. The frequency can be precisely tuned by the supply voltage. In the test set for an experimental receiver including the DR-OSC module, a test-pattern-generator generates 64-byte frames, each of which comprises a 56-byte data payload and an 8-byte overhead. The data payload contains an index of the frame number and a Manchester-encoded 15th-stage pseudo-random data stream, and the overhead is filled with zeros. An encoder converts the input stream into a Manchester-encoded stream. Then, the overhead of the Manchester-encoded zeros can be used as a decoding clock of a subsequent data payload.