Ap Note Discrete Circuit for Magneto-Inductive Sensors

计算机常见英文缩写Virtue carries wealth. On the morning of November 2, 2022计算机常用英文缩写3DPA—3D Positional Audio—3D定位音频3DS—Three Dimension Studio—三维摄影室AAT—Average Access Time—平均存取时间ABS—Auto Balance System—自动平衡系统AC—Alternating Current—交流电ACOPS—Automatic CPU Overheat Prevention System—自动CPU过热预防系统ACPI—Advanced Configuration And Power Interface—高级配置与电源接口ADC—Analog To Digital Convent—模数转换器ADIMM—Advanced Dual In-line Memory Modules—高级双重内嵌式内存模块ADO—ActiveX Data Object—ActiveX数据对象ADSL—Asymmetric Digital Subscriber Line—非对称数字用户路线AE—Atmospheric Effect—雾化效果AGP—Accelerated Graphics Port—加速图形接口AGU—Address Generation Unit—地址产生单元AHA—Accelerated Hub Architecture—加速中心架构AH—Authentication Header—鉴定头文件AI—Artificial Intelligence—人工智能AL—Artificial Life—人工生命ALU—Arithmetic Logic Unit—算术逻辑单元ANSI—American National Standard Institute—美国国家标准协会AOL—American Online—美国在线APIC—Advanced Programmable Interrupt Controller—高级程序中断控制器APM—Advanced Power Management—高级电源管理APP—Accelerated Parallel Processing—AMD加速并行处理技术APPE—Advanced Packet Parsing Engine—高级数据包解析引擎ARP—Address Resolution Protocol—地址解析协议ASC—Anti Static Coating—防静电涂层ASCII—American Standard Code For Information Interchange—美国信息交换标准代码ASIC—Application Specific Integrated Circuit—特殊应用集成电路AST—Average Seek Time—平均寻道时间ATAPI—Advanced Technology Attachment Packet Interface—高级技术附加数据包接口ATL—ActiveX Template Library—ActiveX模版库ATM—Asynchronous Transfer Mode—异步传输模式AV—Analog Video—模拟视频AVI—Audio Video Interleave—音频视频插入B2C—Business To Custom—商家对客户BASIC—Beginner—All-Purpose Symbolic Instruction Code—初学者通用符号指令代码BBS—Bulletin Board System—公告牌系统BCF—Boot Catalog File—启动目录文件BGA—Ball Grid Array—球栅阵列BIF—Boot Image File—启动映像文件BIOS—Basic Input Output System—基本输入输出系统BIS—Boot Integrity Service—启动整体服务BMS—Black Matrix Screen—超黑矩阵屏幕BOPS—Billion Operation Per Second—十亿次计算每秒BPT—Branch Prediction Table—分支预测表BTB—Branch Target Buffer—分支目标缓冲CAD—Computer Aided Design—计算机辅助设计CAE—Computer Aided Engineering—计算机辅助工程CAI—Computer Aided Instruction—计算机辅助教学CAM—Common Access Mode—公共存取模型CAM—Computer Aided Manufacturing—计算机辅助制造CBIC—Cell based Integrated Circuit—基于单元的集成电路CC—Companion Chip—同伴芯片CCD—Charge Coupled Dvice—电流连接设备CCM—Call Control Management—拨号控制管理CC-NUMA—Cache Coherent Non Uniform Memory Access—连贯缓冲非统一内存寻址CCT—Clock Cycle Time—时钟周期CDMA—Code Division Multiple Access—码分多址CDR—Compact Disc Recordable—可刻录光盘CD-ROM—Compact Disc Read Only Memory—光驱CD-RW—Compact Disc Rewriter—刻录机CDSL—Consumer Digital Subscriber Line—消费者数字订阅线路CE—Consumer Electronic—消费电子CEM—Cube Environment Mapping—立方环境映射CEO—Chief Executive Officer—首席执行官CG—Computer Graphic—计算机生成图像CGI—Common Gateway Interface—通用网关界面CHRP—Common Hardware Reference Platform—公用硬件平台CIEA—Commercial Internet Exchange Association—商业英特网交易协会CIR—Committed Information Rate—约定信息速率CISC—Complex Instruction Set Computing—复杂指令集计算机CLV—Constant Linear Velocity—恒定线速度CMOS—Complementary Metal Oxide Semiconductor—互补金属氧化物半导体存储器COB—Cache On Board—板上集成缓存COD—Chip On Board—芯片内集成缓存COM—Component Object Model—组件对象模型COO—Chief Organization Officer—首席管理官CPGA—Ceramic Pin Grid Array—陶瓷针形栅格阵列CPLD—Complex Programmable Logic Device—复杂可编程逻辑器件CPS—Characters Per Second—每秒字符数CPU—Central Processing Unit—中央处理器CRC—Cyclical Redundancy Check—循环冗余检查CRM—Custom Relationship Management—客户关系管理CRT—cathode Ray Tube—阴极射线管CSE—Configuration Space Enable—可分配空间CSS—Cascading Style Sheets—层叠样式表CTO—Chief Technology Officer—首席技术官CTS—Carpal Tunnel Syndrome—腕管综合症CUDA—Computer Unified Device Architecture—计算机统一装置结构CVS—Computer Visual Syndrome—计算机视觉综合症DAC—Dual Address Cycle—双重地址周期DAE—Digital Audio Extraction—数字音频抓取DB—Deep Buffer—深度缓冲DCD—Dynamic Content Delivery—动态内容推送DC—Domain Controller—域控制器DCE—Data Communication Equipment—数据通信设备DCOM—Distributed Component Object Model—分布式组件对象模型DCT—Display Compression Technology—显示压缩技术DDC—Display Data Chanel—显示数据通道DDN—Digital Data Network—数字数据网DDR—Double Data Rate—双倍速率DDSS—Double Dynamic Suspension System—双层动力悬吊系统DEC—Direct Etching coating—表面蚀刻涂层DES—Data Encryption Standard—数据加密标准DFP—Dynamic Feedback Protocol—动态反馈协议DHCP—Dynamic Host Configuration Protocol—动态主机配置协议DIB—Dual Independent Bus—双独立总线DIC—Digital Image Controller—数字图像控制DIMM—Dual Inline Memory Module—双列直插内存模块DIP—Double In-line Package—双列直插式封装DIR—Direct Infrastructure rendering—基层直接渲染DLL—Dynamic Link Library—动态数据链接库DLP—Digital Light Process—数字光处理DME—Direct Memory Execute—直接内存执行DMI—Desktop Management Interface—桌面管理界面DMI—Dynamic Method Invocation—动态方法调用DNS—Digital Nervous System—数字神经系统DNS—Domain Name System—域名系统DOS—Disk Operating System—磁盘操作系统DP—Dual Processor—双处理器DPI—Dots Per Inch—每英寸点数DPMS—Display Power Management Signal—显示能源管理信号DQL—Dynamic Quadrapole Lens—动态四极镜DRC—Design Rule Check—设计规则检查DSD—Direct Stream Digital—直接比特流数字DSL—Digital Subscriber Line—数字用户专线DSP—Digital Signal Processing—数字信号处理DST—Drive Self Test—驱动自检程序DTD—Document Type Definition—文件类型定义DTE—Digital Terminal Equipment—数据终端设备DVD—Digital Versatile Disc—数字多功能光DVD—Digital Video Disc—数字视频光盘DVD-RAM—Digital Versatile Disc Random Access Memory—DVD随机存储器DVI—Digital Video Interface—数字视频接口E3—Electronic Entertainment Expo—美国E3大展EAX—Environment Audio Extension—环境音效扩展EB—Expansion Bus—扩展总线EBR—Excess Burst Rate—超频突发速率ECC—Elliptical Curve Crypto—椭圆曲线加密EC—Embedded Controller—嵌入式控制ECP—Extended Capabilities Port—扩展并行口ECTS—European Computer Trade Show—欧洲计算机商贸展示会EDIF—Electronic Design Interchange Format—电子设计交换格式EEPROM—Electrically Erasable Programmable Read Only Memory—电擦可编程只读存储器EFEAL—Extension Field Elliptically Aperture Lens—可扩展扫描椭圆孔镜头EIDE—Enhanced Integrated Driver Electronic—增强电子集成驱动器EISA—Enhanced Industry Standard Architecture—增强工业标准架构EMI—Electromagnetic Interference—电磁干扰EMP—Emergency Management Port—紧急事情管理端口EPP—Enhanced Parallel Port—增强并行口EPU—Energy Processing Unit—能耗调控单元ERC—Electronic Rule Check—电气规则检查ERP—Enterprise Resource Planning—企业资源计划ERP—Estimated Retail Place—估计零售价ESCD—Extended System Configuration Data—扩展系统配置数据FADD—Floating Addition—浮点加FAT—File Allocation Table—文件分配表FBC—Frame Buffer Cache—帧缓冲缓存FCPGA—Flip Chip Pin Grid Array—反转芯片针脚栅格阵列FDBM—Fluid Dynamic Bearing Motor—液态轴承马达FDC—Floppy Disk Controller—软盘控制装置FDD—Floppy Disk Drive—软盘FDIV—Floating Divided—浮点除FDM—Frequency Division Multiplexing—频分多路复用FIR—Finite Impulse Response—有限推进响应FMUL—Floating Multiplication—浮点乘FMV—Full Motion Video—全动态影像FPGA—Filed Programmable Grate Array—现场可编程门阵列FPS—First Person Shooting—第一人称射击FPU—Floating Processing Unit—浮点运算单元—Frames Per Second—每秒传输帧数FRICC—Federal Research Internet Coordinating Committee—联邦调查因特网协调委员会FSAA—Full Scene Anti—aliasing—全景抗锯齿FSE—Frequency Shifter Effect—频率转换效果FSM—Finite Status Machine—有限状态机FSUB—Floating Subtraction—浮点减FTP—File Transfer Protocol—文件传输协议FWH—Firmware Hub—固件中心GDI—Graphic Device Interface—图形设备接口GIF—Generalized Timing Formula—一般程序时间GMCH—Graphic Memory Control Hub—图形内存控制中心GMR—Giant Magneto Resistive—巨型磁阻GPF—Generation Protection Fault—一般保护性错误GPS—Global Positioning System—全球定位系统GPU—Graphic Processing Unit—图形处理器GSM—Global System For Mobile Communication—全球移动通讯系统GUI—Graphical User Interface—图形用户界面GVPP—Generic Visual Perception Processor—常规视觉处理器HAL—Hardware Abstraction Layer—硬件抽象化层HCI—Host Control Interface—主机控制接口HCT—Hardware Compatibility Test—硬件兼容性测试HDA—Head Disk Assembly—磁头集合HDCP—High-Bandwidth Digital Content Protection—高带宽数字内容保护HDD—Hard Disk Drive—硬盘HDL—Hardware Description Language—硬件描述语言HDMI—High Definition Multimedia Interface—高清晰度多媒体接口HDSL—High-Speed Digital Subscriber Line—高速率数字用户路线HDTV—High Definition TV—高清电视HEL—Hardware Emulation Layer—硬件模拟层HiFDA—High_Capacity Floppy Disk—高容量软盘HMOS—High Performance Metal Oxide Semiconductor—高性能金属氧化物半导体HPA—High Power Amplifier—高功率放大器HPS—High Performance Server—高性能服务器HPW—High Performance Workstation —高性能工作站HRIF—Head Related Transfer Function—头部关联传输功能HTML—Hyper Text Markup Language—超文本标志语言HTPC—Home Theater Personal Computer—家庭影院电脑HTTP—Hyper Text Transmission Protocol—超文本传输协议HUD—Head Up Display—平视显示器IA—Intel Architecture—英特尔架构ICD—Installable Client Drive—可安装客户端驱动程序ICMP—Intel Control Message Protocol—英特尔控制报文协议ICU—Instruction Control Unit—指令控制单元IDCT—Inverse Discrete Cosine Transfer—非连续反余弦变换IDF—Intel Developer Forum—因特尔开发者论坛IEEE—The Institute Electrical And Electronic Engineerings—美国电气和电子工程师协会IETF—Intel Engineer Task Force—因特网工程任务组IEU—Integer Excute Unit—整数执行单元IID—Interaural Intensity Difference—两侧声音强度差别IIR—Infinite Impulse Response—无限推进响应IIS—Internet Information Service—互联网信息服务IKE—Intel Key Exchange—因特网密钥交换协议IMM—Intel Mobil Module—因特尔移动模块IP—Internet Protocol—互联网协议IPPR—Image Processing And Pattern Recognition—图像处理和模式识别IPS—In Plane Switching—平面转换IRC—Internet Relay Chat—互联网接力聊天IRQ—Interrupt Request—中断请求IRST—Intel Rapid Storage Technology—英特尔快速存储技术ISA—Industry Standard Architecture—工业标准结构ISA—Instruction Set Architecture—指令集架构ISDN—Integrated Service Digital Network—综合服务数字网络IS—Internal Stake—内置堆栈ISO—International Standard Organization—国际标准化组织ISP—Intel Service Provider—因特网服务供应商JIT—Just In Time—准时制生产JVM—Java Virtual Machine—Java虚拟机KBC—Keyboard Controller—键盘控制器LBA—Logical Block Addressing—逻辑块寻址LCD—Liquid Crystal Display—液晶显示屏LCM—LCD Module—LCD显示模组LCOS—Liquid Crystal On Silicon—硅上液晶LDAP—Lightweight Directory Access Protocol—轻权目录访问协议LDT—Lighting Data Transport—闪电数据传输LED—Light Emitting Diode—发光二极管LF—Linear Filtering—线性过滤LMDS—Local Multipoint Distributed System—局域多点分布式系统LPM—Library Parameterized Module—参数化模块库LTE—Long Term Evolution—长期演进LVDS—Low Voltage Differential Single—低压差分信号LVS—Layout Versus Schematic—版图原理图对比MAC—Media Access Controller—介质访问控制MALS—Multi Astigmatism Lens System—多重散光聚焦系统MB—Motherboard—主机板MDC—Mobile Daughter Card—移动式子卡MFC—Microsoft Foundation Classes—微软基础库MFD—Multi Function Device—多功能设备MIDI—Musical Instrument Digital Interface—乐器数字接口MIME—Multipurpose Internet Mail Extension—多用途因特网邮件扩展协议MIOC—Memory And I/O Bridge Controller—内存和I/O桥控制器MiPad—Multimodal Interactive Notepad—多语态互动式记事本MIS—Management Information System—管理信息系统MMVF—Multi-Media Video File—多媒体视频文件MPEG—Moving Picture Expert Group—运动图像专家组MPP—Massive Parallel Processing—巨量平行处理MPS—Multi Processor Specification—多重处理器规范MRP—Manufacturing Resource Planning—制造资源计划MRW—Midrange Workstation—中型工作站MSI—Microsoft Installer—微软安装程序MS—Magnetic Sensor—磁场感应器MSN—Microsoft Network—微软网络MSP—Media Stream Processor—媒体流处理器MTBF—Mean Time Before Failure—平均故障时间MTH—Memory Transfer Hub—内存转换中心MUD—Multiple User Dungeon—多用户地牢NAOC—No-Account Overclock—无效超频NAS—Network Attached Storage—网络连接式存储NAT—Network Area Translation—网络地址转换NBC—North Bridge Chip—北桥芯片NDIS—Network Driver Interface specification—网络驱动接口规范NDS—Novell Directory Service—网威目录服务NE—Netlist Extract—网表提取NIC—Network Interface Card—网络接口卡NNTP—Network News Transport Protocol—网络新闻传输协议NPC—Non Player Character—非玩着人物NT—New Technology—新技术OCR—Optical Character Recognition—光学字符识别OEM—Original Equipment Manufacturer—原始设备制造商OLGA—Organic Land Grid Array—基板栅格阵列OOP—Object Oriented Programming—面向对象的程序设计OPT—Optimized Production Technology—优化生产技术OS—Operating System—操作系统PCAV—Part Constant Angular Velocity—部分恒定角速度PCB—Printed Circuit Board—印刷电路板PCI—Peripheral Component Interconnect—外围装置连接端口PC—Personal Computer—个人计算机PC—Perspective Correction—透视纠正PDA—Personal Digital Assistant—个人数字助理PDS—Public Directory Support—公众目录支持PE—Parameter Extract—参数提取PGC—Parallel Graphic Configuration—并行图像设置PIB—Processor In a Box—盒装处理器PIC—Programmable Interrupt Controller—可编程中断控制器PICS—Platform For Internet Content Selection—英特网内容选择平台PIM—Personal Information Management—个人信息管理系统PLCC—Plastic Leadless Chip Carrier—塑料无引脚芯片载体PLD—Programmable Logic Device—可编程逻辑器件PLL—Phase Locked Loop—锁相环PNP—Plug And Play—即插即用POF—Polymer Optical Fiber—聚合体光纤POST—Power On Self Test—开机自检PPM—Pages Per Minute—每分钟打印页数PPTP—Point To Point Tunneling Protocol—点对点通道协议PQFP—Plastic Quad Flat Package—塑料方型扁平式封装PRML—Partial Response Maximum Likelihood—最大可能部分反应PSK—Pre-Shared Key—预共享密钥PSN—Processor Serial Numbers—处理器序列号PSU—Power Supply Unit—计算机电源PSW—Program Status Word—程序状态字PXE—Per-boot Execution Environment—预启动运行环境QBM—Quad Band Memory—四倍边带内存QOS—Quality Of Service—服务质量QPA—Quad Port Acceleration—四倍接口加速RADSL—Rate Adaptive Digital Subscriber Line—速率自适应数字用户路线RAM—Random Access Memory—内存随机存储器RARP—Reverse Address Resolution Protocol—反相地址解析协议RDF—Resource Description Framework—资源描述框架RISC—Reduced Instruction Ser Computing—精简指令集计算机RMA—Real Media Architecture—实媒体架构RNG—Random Number Generator—随即数字发生器ROB—Reorder Buffer—重新排列缓存区RPG—Role Playing Game—角色扮演游戏RPM—Revolution Per Minute—每分钟转数RRVP—Resource Reser Vation Protocol—资源保留协议RSD—Removable Storage Device—移动式存储设备RSDS—Reduced Swing Differential Single—小幅度摆动差动信号RTC—Real Time Clock—实时时钟RTL—Register Transmit Level—寄存器传输级RTSP—Real Time Streaming Protocol—实时流协议RTS—Real Time Strategy—即时战略RTS—Request To Send—需求发送SAM—Sales Available Market—可发售市场SAP—Sideband Address Port—边带寻址端口SATA—Serial Advanced Technology Attachment—串行高级技术附件SBC—South Bridge Chip—南桥芯片SBFS—Sample Boot Flag Specification—简单引导标记规范SCSI—Small Computer System Interface—小型计算机系统接口SC—Static Core—静态内核SCT—Software Compatibility Test—软件兼容性测试SDK—Software Development Kit—软件开发工具包SDRAM—Synchronous Dynamic Random Access Memory—同步动态随机存储器SDTV—Standard Definition Television—标准清晰度电视SEC—Single Edge Connector—单边连接器SEM—Spherical Environment Mapping—球形环境映射SET—Secure Electronic Transaction—安全电子交易SGML—Standard Generalized Markup Language—标准通用标记语言SIMD—SIngle Instruction Multi Data—单指令多数据SIV—System Information Viewer—系统信息观察SLI—Scanline Interleave—扫描线间插SMART—Self-Monitoring Analysis And Reporting Technology—自动检测、分析和报告技术SMB—System Management Bus—系统管理总线SMD—Surface Mount Device—表面安装设备SMIL—Synchronous Multimedia Integrated Language—同步多媒体集成语言SMIP—Simple Mail Transfer Protocol—简单邮件传输协议SMI—System Management Interrupt—系统管理中断SMM—System Management Mode—系统管理模式SMP—Symmetric Multi-Processing—对称式多重处理器架构SNMP—Simple Network Management Protocol—简单网络管理协议SNR—Single To Noise Rate—信噪比SOAC—System ON A Chip—系统集成多功能芯片SOC—System On Chip—片上系统SOI—Silicon On Insulator—绝缘体硅片SOS—Server Operating Systems—服务器操作系统SPD—Serial Presense Detect—串行存在检查SPEC—System Performance Evaluation Check—系统性能评估测试SPS—Shock Protection System—震动保护系统SP—Stack Pointing—堆栈指针SQRC—Square Root Calculation—平方根计算SRA—Symmetric Rendering Architecture—对称渲染架构SRR—Segment Register Rewrite—区段寄存器重写SRS—Sound Retrieval System—声音修复系统SSB—Super South Bridge—超级南桥芯片SSD—Solid State Disk—固态硬盘SSE—Streaming SIMD Extensions—单一指令多数据流扩展SSI—Small Scall Integration—小规模集成STB—Set Top Boxes—电视顶置盒STD—Suspend To Disk—磁盘唤醒STR—Suspend To RAM—内存唤醒STS—Switched Internet working Service—交换式网络互联服务SUA—Single User Account—单用户账号SVR—Switching Voltage Regulator—交换式电压调节TCA—Twin Cache Architecture—双缓冲结构TCO—Total Cost Of Ownership—拥有总成本TCP—Transmission Control Protocol—传输控制协议TCP—Transmission Control Protocol—传输控制协议TDP—Thermal Design Power—散热设计功耗TFT—Thin Film Transistor—薄膜晶体管TLB—Translate Look Side Buffers—翻译旁视缓冲器TOP—The Olympic Partner—奥林匹克全球合作伙伴TPS—Transactions Per Second—每秒处理事项数TQM—Total Quality Management—全面质量管理UART—Universal Asynchronous Receive/Transmitter—通用异步收发器UCC—Ultra Clear Coating—超清晰涂层UDMA—Ultra Direct Memory Access—高级直接内存访问UDP—User Datagram protocol—用户数据报协议UDP—User Datagram Protocol—用户数据报协议ULS—User Location Service—用户定位服务UPA—Ultra Port Architecture—超级端口结构UPS—Uninterrupted Power Supply—不间断电源USB—Universal Serial Bus—通用串行总线USDM—Unified System Diagnostic Manager—统一系统检测管理USWC—Uncacheabled Speculative Write Combination—无缓冲随即联合写操作VALU—Vector Arithmetic Logic Unit—向量算术逻辑单元VBI—Vertical Blanking Interval—垂直空白间隙VCMA—Virtual Channel Memory Architecture—虚拟通道内存结构VDM—Windows Driver Model—视窗驱动程序模块VDSL—Very-high-bit-rate Digital Subscriber Loop—甚高速数字用户环路VDT—Video Display Terminal—视频显示终端VESA—Video Electronic Standard Association—视频电子标准协会VFAT—Virtual File Allocation Table—虚拟文件分配表VFM—Wired For Management—有线管理VGA—Video Graphics Array—视频图形阵列VID—Voltage Identification Definition—电压识别认证VIP—Video Interface Port—视频接口VLIW—Very Long Instruction Word—超长指令集VLSI—Very Large Scale Integrated—超大规模集成电路VOD—Video On Demand—视频点播VPN—Virtual Private Network—虚拟局域网VPU—Vector Permutate Unit—向量排列单元VQTC—Vector-Quantization Texture Compression—向量纹理单元VRE—Voltage Reduction Enhance—增强型电压调节VRML—Virtual Reality Makeup Language—虚拟现实结构化语言VRM—Voltage Regulator Module—电压调整模块VSA—Virtual System Architecture—虚拟系统架构VSIS—Video Single Standard—视频信号标准VXML—Voice Extensible Markup Language—语音扩展标记语言WAIS—Wide Area Information Service—广义信息服务器WAN—Web Area Network—广域网WG—Wave Guide—波导合成Wi—Fi—Wireless Fidelity—无线保真WLAN—Wireless Local Area Network—无线局域网络WMI—Wired For Management Initiative—主动式管理线路WOL—Wake On Lan—局域网唤醒WPAN—Wireless Personal Area Network—无线个域网WSH—Windows Scripting Host—视窗脚本程序—World Wide Web—万维网XSL—Extensible Style Sheet Language—可扩展设计语言ZAM—Zero Administration For Windows—零管理视窗系统ECL—Emitter Couple Logic—射极耦合逻辑CAM—Content Addressable Memory—内容寻址存储器MIPS—Million Instruction Per Second—每秒处理百万级指令。

电路原理专业词汇表Glossary of “Principles of Electric Circuits” Chapter 1 Elements and Laws of ElectricalCircuits电路electrical circuit电流current电荷electric charge电压voltage电位potential电位差potential difference电动势electromotive force功率power能量energy电阻resistor / resistance电导conductor / conductance电感inductor / inductance电容capacitor / capacitance欧姆定律Ohm’s Law广义欧姆定律generalized Ohm’s Law 参考方向reference direction电压极性voltage polarity正极positive polarity负极negative polarity理想独立电压源ideal independent voltage source理想独立电流源ideal independent current source理想受控源ideal dependent / controlled source压控电压源voltage controlled voltage source(VCVS) 压控电流源voltage controlled current source(VCCS) 流控电压源current controlled voltage source(CCVS) 流控电流源current controlled current source(CCCS) 节点node支路branch回路loop基尔霍夫电流定律Kirchhoff’s Current Law(KCL)基尔霍夫电压定律Kirchhoff’s V oltage Law(KVL)闭合面closed boundary 集总参数lumped parameter集总参数电路lumped circuit集总参数元件lumped element分布参数distributed parameter分布参数电路distributed circuit直流direct current(DC)交流alternating current(AC)有源器件active element无源器件passive element无损电路lossless circuitChapter 2 Analysis methods to simple resistorcircuits串联series connection分压voltage division并联parallel connection分流current division等效电阻equivalent resistanceY-Δ变换 Wye-Delta transformation入端电阻input resistanceChapter 3 Methods of Analysis支路电流法method of branch current节点法Nodal Analysis回路电流法loop current method网孔电流法mesh current method外网孔outer mesh自导纳self-admittance互导纳mutual-admittance矩阵matrix行row列column参考节点reference node平面电路planar circuit方程equation消去法elimination technique克莱姆法则 Cramer’s rule代入法substitution method运算放大器operational amplifier(op amp)同向输入端 noninverting input反向输入端 inverting input输出端output等效电路模型equivalent circuit model 开环放大倍数open-loop gain闭环放大倍数closed-loop gain入端电阻input resistance输出电阻output resistance线性工作区 linear region正向饱和区 positive saturation反向饱和区 negative saturation同向放大noninverting amplifier反向放大inverting amplifier加法器summing amplifier积分器integrator微分器differentiator自激振荡self-sustained oscillationChapter 4 Circuit Theorems叠加原理superposition principle输入/激励input / excitation输出/响应output / response线性电路linear circuit代数和algebraic sum替代定理substitution principle戴维南定理 Thevenin’s Theorem诺顿定理Norton’s Theorem二端网络two-terminal circuit开路电压open-circuit voltage短路电流short-circuit current特勒根定理 Tellegen Theorem功率平衡定理Power-balancing Theorem 互易定理reciprocal theorem对偶原理principle of duality对偶元件dual element对偶图dual graphChapter 5 Nonlinear Circuit非线性电路 nonlinear circuit非线性元件 nonlinear element压控电阻voltage-controlled resistor流控电阻current-controlled resistor静态电阻static resistance动态电阻dynamic resistance小信号分析 small-signal analysis小信号模型 small-signal modal分段线性化法piece-wise linear mthod 数值解法numerical analysis Chapter 6 First-order Circuit一阶电路first-order circuit一阶微分方程first-order differential equation 过渡过程transient process线性时不变电路linear time-invariable circuit单位阶跃函数unit step function单位脉冲函数unit pulse function单位斜坡函数unit ramp function起始条件initial condition起始值initial value零输入响应 zero-input response零状态响应 zero-state response稳态响应steady-state response暂态响应transient response时间常数time constant指数函数exponential function阶跃响应step response冲激响应impulse response自由响应natural response强迫响应forced response全响应complete response稳态值final value卷积积分convolution integration时域延迟time delay换路switching跳变现象jump phenomenon脉冲持续时间pulse duration脉冲重复周期repeating period of pulseChapter 7 Second-order Circuit二阶电路second-order circuit齐次微分方程homogeneous differential equation常系数微分方程constant coefficients equation特征方程characteristic equation特征根characteristic root特征值eigenvalue特征向量eigenvector特解particular solution通解general solution自然频率natural frequency衰减系数damping factor谐振角频率resonant frequency / undampednatural frequency过阻尼情况 overdamped case欠阻尼情况 underdamped case临界情况critically damped case固有振荡角频率damping frequency / dampednatural frequency衰减振荡damped oscillation无损lossless正弦响应sinusoidal response波形waveform实数real复数complex衰减attenuationChapter 8 Sinusoidal Steady-State Analysis幅值amplitude / magnitude相位phase相位差phase difference角频率angular frequency周期period频率cyclic frequency正弦sinusoidal余弦cosine初相角initial phase angle瞬时值instantaneous value最大值maximum有效值 effectivevalueroot-mean-square valueu 领先 i φu leads i by φu 落后 i φu lags i by φ同相in phase反相opposite in phase实部real part虚部imaginary part直角坐标形式rectangular form极坐标形式 polar form指数形式exponential form相量phasor参考相量reference phasor电压三角形 voltage triangle瞬时功率instantaneous power平均功率average power阻抗impedance导纳admittance电抗reactance电纳susceptance感性inductive容性capacitive 正弦稳态响应sinusoidal steady-state response时域time-domain相量域phasor-domain视在功率apparent power功率因数power factor (pf)复功率complex power功率三角形 power triangle复共轭complex conjugate有功功率active power无功功率reactive power最大功率传输定理Maximum Power Transfer Theorem功率守恒定理Theorem of conservation of power阻抗匹配impedance matching共轭匹配conjugate matchingChapter 9 Magnetically Coupled Circuits耦合couple互感mutual inductance自感self-inductance磁通magnetic flux互感电压mutual / induced voltage线圈coil铁心线圈coil with iron core匝数turn耦合系数coupling coefficient变压器transformer空心变压器 air-core transformer原边primary coils / windings副边secondary coils / windings引入阻抗reflected impendence理想变压器 ideal transformer全耦合变压器unity-coupled transformer变比turns ratio / transformation ratio自耦合变压器auto-transformer多绕组变压器multiple-winding transformer 右螺旋定则right-handed screw rule同名端dotted terminalterminals of same magnetic polarity 漏感leakage inductanceChapter 10 Resonance串联谐振series resonance并联谐振parallel resonance谐振频率resonant frequency特性阻抗characteristic impedance品质因数quality factor频率响应frequency response选择性selectivity选频特性frequency-selection characteristicChapter 11 Frequency Response复频率complex frequency网络函数network function转移函数transfer function多项式polynomial极点pole零点zero波特图Bode plot分贝decibel增益gain对数logarithm半对数semilog转折频率corner / break frequency截止频率cut-off frequency带宽bandwidth无源滤波器 passive filter有源滤波器 active filter低通滤波器 low-pass filter高通滤波器 high-pass filter带通滤波器 band-pass filter带阻滤波器band-stop / band-reject / notch filterChapter 12 Three-phase Circuits对称三相电源balanced three-phase sources 对称三相电路symmetrical three-phase circuit中线neutral line中性点neutral point三相四线制three-phase four-wire system相电压phase voltage线电压line voltage相序phase sequence正序positive / abc sequence负序negative / acb sequence相电流phase current线电流line current Chapter 13 Steady-State Response of PeriodicExcitation周期性非正弦激励nonsinusoidal periodic excitation三角形式的付里叶级数trigonometric Fourier series指数形式的付里叶级数exponential Fourier series付里叶系数 Fourier coefficient基波fundamental harmonic基波频率fundamental frequency谐波harmonic wave高次谐波higher harmonic频谱frequency spectrum谱线spectrum line线状频谱line spectrum奇次odd偶次even奇对称odd symmetry偶对称even symmetry半波对称half-wave symmetry帕斯瓦尔定理Parseval’s theoremChapter 14 Fourier Transformation andLaplace Transformation付里叶变换 Fourier transformation拉普拉斯变换Laplace transformation原函数original function象函数transform function积分变换integral transformation频域frequency domain幅度谱amplitude spectrum相位谱phase spectrum矩形脉冲rectangular pulse线性性质linearity时域微分time differentiation时域积分time integration时域平移time shift频域平移frequency shift拉普拉斯反变换inverse Laplace transformation 拉普拉斯变换对 Laplace pairsChapter 15 Two-port Networks端口port二端口网络 two-port network四端网络four-terminal network / quadripole Z参数impedance parametersY参数admittance parametersH参数Hybrid parametersT参数Transmission parameters策动点driving point(二端口)级联cascade connection传播常数transmission constantChapter 16 Basis of Network Graph Theory 图graph拓扑图topological graph子图subgraph连通图connected graph有向图oriented graph树tree树支tree branch连支link割集cut set降阶关联矩阵reduced incidence matrix增广矩阵augmented matrix秩rank基本回路矩阵fundamental loop matrix基本割集矩阵fundamental cut set matrix单位阵unit matrix转置阵transposed matrix正定矩阵positive definite matrix非奇异矩阵 nonsingular matrix逆矩阵inverse matrix方阵square matrix零矩阵zero matrix行列式determinantChapter 17 State Variables Approach状态变量state variable状态方程state equation状态空间state space列向量column vector特征值characteristic value特征向量characteristic vector特征方程characteristic equation 相似矩阵similar matrixChapter 18 Nonlinear Dynamic Circuits非线性时变电路nonlinear time-varying circuit自治电路非自治电路前向欧拉法forward Eular’s method后向欧拉法backward Eular’s method相平面状态平面state planar相轨线中心点焦点节点鞍点平衡点稳定性stability渐近稳定asymptotic stabilityChapter 19 Distributed Circuits分布参数电路distributed circuit传输线transmission line均匀传输线uniform transmission line 反射 reflection透射 transmission波长 wavelength波速 wavespeed行波traveling wave驻波standing wave正向行波direct wave反向行波returning wave波阻抗wave impedance波前wave front传播常数propagation constantAppendix Magnetic Circuit磁路magnetic circuit铁磁物质ferromagnetic substance磁导率magnetic permeability磁感应强度 magnetic induction磁通magnetic flux磁链magnetic linkage磁通势magnetomotive force磁通密度magnetic flux density磁通连续性定理principle of continuity of magnetic flux 磁场强度magnetic flux intensity磁阻reluctance磁导permeance安培环路定理principle of Ampere loop circuit磁化曲线magnetization curve磁滞回线hysteresis loop磁滞hysteresis涡流eddy current涡流损失eddy current loss集肤效应skin effect漏磁通leakage flux磁饱和magnetic saturation电磁感应定律law of electromagnetic induction励磁电流exciting current。

123sn1232 1232fasSYMBOL PARAMETER CONDITIONSMINTYP MAX UNITSV CC Supply Voltage● 4.555.5V V IH ST and PB RST Input High Level ●2V CC +0.3V V ILST and PB RST Input Low Level●–0.30.8VDC ELECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MINTYP MAX UNITS I IL Input Leakage (Note 3)●–11µA I OH Output Current at 2.4V (Note 5)●–1–13mA I OL Output Current at 0.4V (Note 5)●26mAI CC Supply Current (Note 4)●0.52mA V CCTP V CC Trip Point TOL = GND ● 4.5 4.62 4.74 V V CCTP V CC Trip PointTOL = V CC●4.254.37 4.49 V V HYS V CC Trip Point Hysteresis 40mV V RSTRST Output Voltage at V CC = 1VI SINK = 10µA4200mVThe ● denotes the specifications which applyover the full operating temperature. V CC = full operating range.The ● denotes the specifications which apply over the full operatingtemperature. V CC = full operating range.SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITS t PB PB RST = V IL ●40ms t RST RESET Active Time ●2506101000ms t ST ST Pulse Width●20ns t RPD V CC Detect to RST and RST ●100ns t f V CC Slew Rate 4.75V–4.25V ●300µs t RPU V CC Detect to RST and RSTt R = 5µs●2506101000ms (Reset Active Time)t R V CC Slew Rate 4.25V–4.75V ●0nst TDST Pin Detect to RST and RST TD = GND ●60150250ms (Watchdog Time-Out Period)TD = Floating ●2506101000ms TD = V CC●50012002000ms C IN Input Capacitance 5pF C OUTOutput Capacitance5pFNote 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.Note 2: All voltage values are with respect to GND.Note 3: The PB RST pin is internally pulled up to V CC with an internal impedance of 10k typical. The TD pin has internal bias current.Note 4: Measured with outputs open.Note 5: The RST pin is an open drain output.The ● denotes the specifications which apply over the full operating temperature.V CC = full operating range.AC CHARACTERISTICSRECO E D ED OPERATI G CO DITIO SU U U U WW456Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.7Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LW/TP 1002 1K REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORA TION 19928。

Supertex inc.AN-H56Application NoteIntroductionThe MD1812 and the MD1813 are two unique composite return-to-zero (RTZ) pulser drivers for ultrasound applications. The ICs have built-in level shifters that provide negative P-MOS gate DC bias and fast AC coupled gate drivesignals. They enable the fast damping functions necessary to generate return-to-zero bipolar pulses, and are also able to keep the zero-state to as long as needed, even to infinity. These kinds of fast return-to zero and DC coupled features are very useful for medical ultrasound imaging equipment, piezoelectric transducer drivers, material flaw detection, ultrasonic NDT detection, and sonar ranger applications, especially for those that need to launch ultrasound in pseudo-random codes. Designing a Pulser with the MD1812/13This a pplication n ote d escribes h ow t o u se M D1812 o r M D1813 to design the basic channel of an ultrasound transmitter with the RTZ feature. The circuit is a single channel ultrasound transmitter using the MD1812 or MD1813 to drive TC6320 & TC2320 MOSFETs. It can generate fast return to zero waveforms. The output of high voltage to transducer has ±2A source and sink current capability. A CPLD programmable logic circuit and on-board 40MHz crystal oscillator generate a fast logic signal to control the pulse circuit. The CPLD hasa six-pin JTAG connection for Xilinx’s USB or a convenient parallel-port programming link cable. The circuit consists of one MD1812K6 or MD1813K6 in a 16-lead 4x4x0.9mm QFN package, driving TC6320FGs and TC2320FGs, two complementary high-voltage P and N- channel MOSFETs in one single SO-8 package. The input stage of the MD1812/13 is a high-speed level translator that is able to operate with logic input signals of 1.2V to 5.0V amplitude. In this circuit, the CPLD output logic is typically 3.3V. An adaptive threshold circuit is used with the OE pininside of the MD1812 to set the level translator threshold to the middle of the input logic 0 and logic 1 levels. The OE pin serves a dual purpose. First, its logic 1 level is used to compute the threshold voltage level for the channel input level translators. Second, when OE is low, the outputs are disabled, with the A and C outputs high and the B and Doutputs low (for MD1812 only). This assists in properly pre-charging the coupling capacitors that may be used in series in the gate drive circuit of external PMOS and NMOS FETs. The MD1812/13 level translator uses a proprietary composite drive circuit, which provides DC coupling, together with high-speed operation. The output pin, OUT C , is designed to drive the return-to-zero PMOS FET through a capacitor as fast as an AC coupling gate driver, and OUT G provides delayed DC coupling negative biased gate control to the same PMOS FET. The OUT C swings between V H and V L voltages, while OUT G is within V SS or V NEG levels. Note that the OUT C and OUT G pins of one chip are designed to drive together forone PMOS FET, and that the PMOS FET source is typicallyconnected to the same potential of the MD1812/13 V SS voltage. Each of the output stages of OUT A , OUT B , OUT C & OUT D of MD1812/13 are capable of peak currents of up to ±2.0A, depending on the supply voltages used and load capacitance. But a 2kΩ resistor, R36, must be between OUT G and the gate of the PMOS FET, which is driven by the OUT C through a capacitor. This configuration provides the optimal series resistance value of the gate DC bias driver circuit.The output stage of the MD1812/13 has separate power connections enabling the output signal high and low levels to be chosen independently from the driver supply voltages. As an example, the input logic levels may be 0V and 1.8V, the control logic may be powered by +5V and –5V, and the output high and low levels may be varied anywhere over the range of +5V to -5V. In this design example, MD1812/13’s V DD and V H are both powered by +10V, V SS and V L are grounded, and V NEG is –10V. The source pin of the RTZ PMOS FET driven by the OUT C and OUT G pins is connected to ground.PCB Layout TechniquesIt is very important that the slab at the bottom of the IC package, which is the IC substrate “pin”, be externally connected to the V NEG pin to make sure it always has the lowest potential in any condition.Designing An Ultrasound Pulser with MD1812/MD1813 Composite DriversBy Ching Chu, Sr. Application EngineerUse high-speed PCB trace design practices that are compatible with the circuit’s operating speed. The internal circuitry of the MD1812/13 can operate at up to 100MHz, with the primary speed limitation being due to load capacitance. Because of this high speed and the high transient currents that result when driving capacitive loads, the supply voltage bypass capacitors should be as close to the supply pins as possible. The V SS and V L pins should have low inductance feed-through connections that are connected directly to a solid ground plane. If these voltages are not zero, they will require bypass capacitors similar to the positive power supplies. The V DD and V H supplies determine the output logic levels. These two pins can draw fast transient currents of up to 2.0A, so they should be provided with a low-impedance bypass capacitor at the chip’s pins. A ceramic capacitor of up to 1.0µF may be appropriate. Minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. A common voltage source and local decoupling capacitor may be used for the V DD and V H pins, which should always have the same DC level applied to them. For applications that are sensitive to jitter and noise, insert another ferrite bead between V DD and V H and decouple each pin separately.Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surfacemount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small value resistor in series with the output to obtain better waveform integrity at the load terminals. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load. Pay particular attention to the parasitic coupling from the driver’s output to the input signal terminals. This feedback may causeoscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V, even small coupling voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry.Testing the Ultrasound Pulser The MD1812 RTZ pulser design example is tested with the following power supply voltage and current limiting: V PP 0 to +100V 5mA, V NN 0 to -100V 5mA, V DD = +10V 50mA, V NEG -10V 5mA, V CC +3.3V, 90mA.The HV OUT signal appears at the SMA connector J6. There is a 5:1 attenuation of the signal, due to the value of resistor R11. When driving a real transducer load, the value of this resistor should be reduced in value to match the load impedance.The HV OUT signal passes through jumper J5, which can be used to terminate the HV OUT signal in a dummy load, comprising a 220pF capacitor in parallel with a 1kΩ resistor. When an external load is connected, the dummy load is not required, and J5 can be configured to pass the signals straight through to the output connector J6.All the on-board test points are designed to work with an active oscilloscope probe, such as the Tektronix P6243 1MΩ active probe. Because TP7 is connected to the HV OUT , where potentially damaging voltages could be present, make sure that V PP /V NN does not exceed the probe limit. If using another type of high impedance oscilloscope probe for the test points, ensure that the ground lead connections to the circuit board ground plane are as short as possible.There are multiple frequency and waveform combinations that can be selected as bipolar pulses, PW or CW waveforms. An external clock input can be used if the on-board 40MHz-oscillator is disabled. The external trigger input can be used to synchronize the output waveforms. There are five push buttons for selecting demo waveform, frequency, phase, and MD1812 chip enable functions. Color LEDs indicate the demo selection states. The CH1 output allows the monitoring of one of the 5 inputs (IN A , IN B , IN C , IN D or O E ) of the MD1812/13 via the select button. The MD1812 and the MD1813 are very similar in function. The only differences between them are the control of the OE (MD1812) vs VLL (MD1813) pin and their logic functions. Please read their data sheets for the details. In this design example, the CPLD program is using an on-board solder jumper, R34, to sense the difference and works accordingly. The example MD1812/13 pulser circuit schematic, detailsignals definitions, and some measured waveforms areshown below.Waveform C, 20MHz, 8 cycles Load: 220pF//1kPulser Circuit SchematicWaveform AWaveform CWaveform BWaveform DOE INA INB INC INDHV OUTV PPV NNOE INA INB INC INDHV OUTV PPV NNOE INAINBINC INDHV OUTV PPV NNOEINAINBINC IND HV OUTV PPV NNNote: The duty cycle of the PW burst is set about 0.2% for limitedpower dissipationNote: The duty cycle of the PW burst is set about 25% at ≤5.0MHz forlimited power dissipation.AN-H56MD1812/13 Reference DesignJ 6X D C RJ E X = L oFig. 1 Waveform of 2.5MHz Fig. 2 Waveform of 5MHzFig. 3 Waveform of 10MHz Fig. 4 Waveform of 10MHz InvertingFig. 5 Waveform of 20MHz 8 Cycles Fig. 6 Waveform of 5mHz & Delay ReadingsFig. 7 Waveform of 10MHz(at IN C , OUT C , OUT G , and P- Gate, V DD = 12V, V NEG = -10V)Fig. 8 Waveform of 5MHz(at IN C , OUT C , OUT G , and P- Gate, V DD = 5V, V NEG = -10V)Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//)©2013 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.Supertex inc.。