联发科八核MT6592 新四核MT6588细节曝光

联发科发布八核处理器，能否掀起新核战？ 201308俗话说得好，“文无第一，武无第二”。

对于艺术来说，因为每个人的审美观念都不同，自然就没有绝对的胜出者。

科技则不然，除去外观、制作工艺、材料这些肉眼能看到的不说，处理器的核心数量、制程、跑分、速度等都是实打实的，完全做不来假。

因此，处理器单单从参数上就能看出来优劣、高低。

近日，联发科正式发布了全球首款“真八核”移动处理器处理器MT6592，引来业界一片哗然。

首先这是赤裸裸地打三星的脸——就在今年年初，三星曾发布了两颗四核处理器叠加而成的八核处理器Exynos5Octa。

其次，此次联发科发布八核处理器将引来移动处理器的新一轮洗牌，一直没有推出八核处理器的高通就开始炮轰。

最后，八核处理器真的有意义吗？这也是业界和用户关注的话题。

究竟联发科发布八核处理器意味着什么，又会带来怎样的连锁反应？八核处理器，迟来的升级在移动端，除去苹果一直按部就班的升级自家产品上的处理器，到现在还在使用双核处理器以外，Android设备上的“核战争”早已经进行了好几年。

从当初的低频率单核到高频率单核，再到双核，直到去年四核全面普及。

可以说，过去的几年，移动处理器就是一场血淋漓的战争，升级速度之快让人瞠目结舌。

但自从发展到四核以后，这场“核战争”似乎变得越来越雷声大，雨点小，似乎已经不再是移动终端宣传的重点。

越来越多的移动终端设备宣扬自己的人性化功能、个性化外观等。

仅仅只有三星在今年年初发布了一款八核处理器产品，其他厂商都没有像以往那样迅速跟进——直到半年后的现在。

对于已经习惯了看到厂商大打“核战争”的用户来说，都和小伙伴们惊呆了。

之所以会如此，有着多方面的原因。

首先，目前移动终端设备性能已经完全过剩。

很多应用程序在双核上都已经非常流畅，体验几乎和四核没什么区别。

硬件发展的速度远远超过系统、软件的发展速度，已经严重过剩。

在这样的情况下，八核处理器自然几乎没有用武之地。

其次，也许很多处理器厂商已经有了开发八核处理器的计划，甚至已经有了可普及的产品。

MTK平台发展及各芯片功能介绍：MT6205、MT6217、MT6218、MT6219、MT6226、MT 6227、MT6228均为基带芯片，所以芯片均采用ARM7的核。

MT6305、MT6305B为电源管理芯片。

MT6129为RF芯片RF3146（7×7mm）、RF3146D（双频）、RF3166（6×6mm）为RFMD的PA。

MT6205为最早的方案，只有GSM的基本功能，不支持MP3等功能。

支持wap/mms的只是用csd的方式传送(2003年MP）MT6218为在MT6205基础上增加GPRS、WAP、MP3功能。

MT6217为MT6218的cost down 方案，6217的班子可以贴6218，反之不可以，这说明不是pin-to-pin，软件也不同，另外MT6 217支持16bit数据。

（2004年MP)MT6219为MT6218上增加内置AIT的1.3M camera处理IC，增加MP4功能。

8bit数据。

（2 005年MP）MT6226为MT6219 cost down产品，内置0.3M camera处理IC，支持GPRS、WAP、MP3、M P4等，内部配置比MT6219优化及改善，比如配蓝牙是可用很便宜的芯片CSR的BC03模块U SD3即可支持数据传输（如听立体声MP3等）功能。

MT6226M为MT6226高配置设计，内置的是1.3M camera处理IC。

（2006年MP）MT6227与MT6226功能基本一样，PIN TO PIN，只是内置的是2.0M camera处理IC。

（200 6年MP）MT6228比MT6227增加TV OUT功能，内置3.0M camera处理IC，支持支持GPRS、WAP、MP3、MP4。

（2006年MP）从MT6226后软件均可支持网络摄像头功能，也就是说你的机子可以用于QQ视频。

MT6229……暂不是很了解。

MT6229:EDGE GPRS +All Mutinedia features of MT62286219不是增加ait的，这个mtk的人可以自己写出来的6226的性能主要体现在由gif的硬件解码，主频升到了91mhz,原来的17/18/19都是78mhz 6228的性能主要体现在104mhz上，它的处理速度很快，另外他的mp4编解码已经达到了专业水平cif/vgaMT6225采用ARM7EJ-S核，主频为104M，支持nand boot，30w的camera；相对于MT6226在硬件上少了2D Engine、image DMA、image post proc、gif decode、jpeg code、mpeg—4 video codec等，通过软件来实现。

TECHNOLOGYFEATURESGENERAL DESCRIPTIONBLOCK DIAGRAM•IEEE802.3 Clause 9 and IEEE802.3u Cluse 27 compliant.•Provide 8 RMII (Reduced Media Independent Interface) ports.•Provide 2 inter_repeater stacking bus for 10M and 100M port expansion each.•Support stacking to 4 units without any external arbitration logic ( if use external arbitration logic, theoretically can stack to 6 units and up) .•Build_in 2 port switch controller, support up to 2048 MAC addresses filtering database.•Optional back_pressure flow control•Optional up_link_switch port function (in slave hub), support 100FX 2km distance extension in 100FD mode.•Meet Class_2 repeater specification for 100M_hub.•Use simple and low cost asynchronous SRAM (high speed ASRAM 128k*8 : one pcs only) •128 pin PQFP package, 5V operation voltage.8 Port 10M/100M Hub With 2 port SwitchThe MTD658 is a highly integrated, 10M/100M dual speed hub with build_in 2 port switch.Support 8 RMII ports for 10M/100M operation,and really meet 100M_hub class_2 spec when connect with external QPHYceivers.The MTD658 provides two Inter-repeater stacking bus for 10M and 100M expansion each,easily stack to 4 units without any external arbi-tration logic. If using external arbitration logic and proper bus driver, can stack to 6 units and up.The build_in 2 port switch, support 2k MAC addresses filtering, and use low cost asynchro-nous high speed SRAM (128k*8) one pcs only for packet buffering. This 2 port switch can also be configured to be up_link switch when hub is under slave mode.The MTD658 also support an simple and effective LED display function, provide 10M_col,100M_col, memory_test_fail, and per port’s parti-tion status.ASRAM InterfaceRMII7RMII6RMII5RMII4RMII3RMII2RMII1RMII010M Hub100M HubTwo PortSwitchUplink Switch Enable(10/100,FD/HD)10M_HD100M_HDPort Switch Logic10MInter Hub Bus100MInter Hub BusTECHNOLOGY SYSTEM DIAGRAMMTD658MTD658QUAD PHYsceiverQUAD PHYsceiverASRAM (128kx8)10MInter Hub Bus100MInter Hub Bus10MInter Hub Bus100MInter Hub Bus MTD658MTD65810MInter Hub Bus100MInter Hub Bus10MInter Hub Bus100MInter Hub BusRMII0-3RMII4-7DB25 ConnectorQUAD TransformerQUAD TransformerRJ45RJ45TECHNOLOGY1.0 PIN CONNECTION1021011009998979695949392919089888786858483828180797877767574737271706968676665103104105106107108109110111112113114115116117118119120121122123124125126127128A 11A 5A 9A 6A 8A 7A 13A 12W EB A 14G N D A 15A 16I R E Q 10_O U T I R E Q 10_I N 0I R E Q 10_I N 1I R E Q 10_I N 2IC O L B 10I A C K B 10I C L K 10G ND I D A T 10I RE Q 100_O U T I R E Q 100_I N 0I R E Q 100_I N 1I R E Q 100_I N 2I C O L B 100I A C K B 100G N D I C L K 100V C C I D A T 100_0I D A T 100_1I D A T 100_2I D A T 100_3I M A S T E RF D 7U P S W E NVCC A4GND OEB A3A10A2A1D7A0D6D0D5D1GND D4D2D3VCC SYSCLK GND LEDDAT LEDCLK MDC MDIO RSTB0102030405060708091011121314151617181920212223242526272829303132333435363738C R SD V 0T X D 0_1V C C T X D 0_0T XE N 0R X D 0_0R X D 0_1C R S D V 1T X D 1_1T X D 1_0T X E N 1R X D 1_0R X D 1_1G N D C R S D V 2T X D 2_1T X D 2_0T X E N 2R X D 2_0R X D 2_1C R S D V 3T X D 3_1T X D 3_0T X E N 3R X D 3_0R X D 3_1S P D 3S P D 2S P D 1S P D 0V C C G N D C R S D V 4T X D 4_1T X D 4_0T X E N 4R X D 4_0R X D 4_1MTD6586463626160595857565554535251504948474645444342414039SPD4SPD5SPD6SPD7GND VCC RXD7_1RXD7_0TXEN7TXD7_0TXD7_1CRSDV7RXD6_1RXD6_0TXEN6TXD6_0TXD6_1CRSDV6GND VCC RXD5_1RXD5_0TXEN5TXD5_0TXD5_1CRSDV5TECHNOLOGY2.0 PIN DESCRIPTIONSRMII Port Interface PinsName Pin Number I/O DescriptionsCRSDV01I Port0 RMII receive interface signal, CRSDV0 is asserted high whenport0 media is non_idle.RXD0_0 RXD0_167IIPort0 RMII receive data bit_0.Port0 RMII receive data bit_1.TXEN05O Port0 RMII transmit enable signal.TXD0_0 TXD0_142OOPort0 RMII transmit data bit_0.Port0 RMII transmit data bit_1.CRSDV18I Port1 RMII receive interface signal, CRSDV1 is asserted high whenport1 media is non_idle.RXD1_0 RXD1_11213IIPort1 RMII receive data bit_0.Port1 RMII receive data bit_1.TXEN111O Port1 RMII transmit enable signal.TXD1_0 TXD1_1109OOPort1 RMII transmit data bit_0.Port1 RMII transmit data bit_1.CRSDV215I Port2 RMII receive interface signal, CRSDV2 is asserted high whenport2 media is non_idle.RXD2_0 RXD2_11920IIPort2 RMII receive data bit_0.Port2 RMII receive data bit_1.TXEN218O Port2 RMII transmit enable signal.TXD2_0 TXD2_11716OOPort2 RMII transmit data bit_0.Port2 RMII transmit data bit_1.CRSDV321I Port3 RMII receive interface signal, CRSDV3 is asserted high whenport3 media is non_idle.RXD3_0 RXD3_12526IIPort3 RMII receive data bit_0.Port3 RMII receive data bit_1.TXEN324O Port3 RMII transmit enable signal.TXD3_0 TXD3_12322OOPort3 RMII transmit data bit_0.Port3 RMII transmit data bit_1.CRSDV433I Port4 MII receive interface signal, CRSDV4 is asserted high whenport4 media is non_idle.RXD4_0 RXD4_13738IIPort4 RMII receive data bit_0.Port4 RMII receive data bit_1.TXEN436O Port4 RMII transmit enable signal.TXD4_0 TXD4_13534OOPort4 RMII transmit data bit_0.Port4 RMII transmit data bit_1.CRSDV539I Port5 RMII receive interface signal, CRSDV5 is asserted high whenport5 media is non_idle.RXD5_0 RXD5_14344IIPort5 RMII receive data bit_0.Port5 RMII receive data bit_1.TXEN542O Port5 RMII transmit enable signal. TXD5_0O Port5 RMII transmit data bit_0.TECHNOLOGYNote: Asynchronous SRAM acess time: 10/12 ns (max)CRSDV647I Port6 RMII receive interface signal, CRSDV6 is asserted high whenport6 media is non_idle.RXD6_0RXD6_15152I I Port6 RMII receive data bit_0.Port6 RMII receive data bit_1.TXEN650O Port6 RMII transmit enable signal.TXD6_0TXD6_14948O O Port6 RMII transmit data bit_0.Port6 RMII transmit data bit_1.CRSDV753I Port7 RMII receive interface signal, CRSDV7 is asserted high when port7 media is non_idle.RXD7_0RXD7_15758I I Port7 RMII receive data bit_0.Port7 RMII receive data bit_1.TXEN756O Port7 RMII transmit enable signal.TXD7_0TXD7_15554O OPort7 RMII transmit data bit_0.Port7 RMII transmit data bit_1.High Speed Asynchronous SRAM Interface PinsName Pin NumberI/O Descriptions WEB 94O ASRAM control pin for write (low active).OEB 106O ASRAM control pin for read (low active).D[7:0]111,113,115,118,120,119,116,114I/O ASRAM data busA[16:0]90,91,93,96,95,102,108,100,98,97,99,101,104,107,109,110,112O ASRAM address busRMII Port Interface PinsName Pin NumberI/O DescriptionsTECHNOLOGY10M Inter-Bus Interface pinsName Pin Number I/O DescriptionsIMASTER67I Master hub selection:when high: means hub internal inter_bus arbiter is enabled and hub internal two_port switch is well conneted to 10M_hub core and100M_hub core .when low: means hub internal inter_bus arbiter is disabled and hub internal two_port switch is not connected to 10M_hub core and100M_hub core.IACKB1084I/O10M Inter-Bus port access acknowledge signal (low active). For master hub, this pin is output; for slave hub is input, or while EXT_ARBjumper was set to “1”, this pin is input from an external arbitrationdevice.ICOLB1085I/O10M Inter-Bus collision signal (low active). For master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while EXT_ARB jumper was set to “1”, this pin is input from an external arbitration device.IREQ10_IN088I10M Inter-Bus port access request input. IREQ10_IN187I10M Inter-Bus port access request input. IREQ10_IN286I10M Inter-Bus port access request input. IREQ10_OUT89O10M Inter-Bus port access request output. ICLK1083I/O10M Inter-Bus port clock.IDAT1081I/O10M Inter-Bus port data bit100M Inter-Bus Interface pins Name Pin Number I/O DescriptionsIACKB10075I/O100M Inter-Bus port access acknowledge signal (low active). For master hub, this pin is output; for slave hub is input, or while EXT_ARBjumper was set to “1”, this pin is input from an external arbitrationdevice.ICOLB10076I/O100M Inter-Bus collision signal (low active). For master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while EXT_ARB jumper was set to “1”, this pin is input from an external arbitration device.IREQ100_IN079I100M Inter-Bus port access request input. IREQ100_IN178I100M Inter-Bus port access request input. IREQ100_IN277I100M Inter-Bus port access request input. IREQ100_OUT80O100M Inter-Bus port access request output. ICLK10073I/O100M Inter-Bus port clock.IDAT100_071I/O100M Inter-Bus port data bit 0.IDAT100_170I/O100M Inter-Bus port data bit 1.IDAT100_269I/O100M Inter-Bus port data bit 2.IDAT100_368I/O100M Inter-Bus port data bit 3.TECHNOLOGYLED Interface PinsName Pin Number I/O DescriptionsLEDDAT124I/O LED display serial data out; mapping for LEDCLK signal’s burst clock , its serial out data sequence is : ( first bit be shifted out is from b00, and end of burst bit is b23)b00: port0 partition b08: 10hub_col b16: port0 rx_activityb01: port1 partition b09: 100hub_col b17: port1 rx_activityb02: port2 partition b10: asram_test_fail b18: port2 rx_activityb03: port3 partition b11: port3 partition b19: port3 rx_activityb04: port4 partition b12: port4 partition b20: port4 rx_activityb05: port5 partition b13: port5 partition b21: port5 rx_activityb06: port6 partition b14: port6 partition b22: port6 rx_activityb07: port7 partition b15: port7 partition b23: port7 rx_activityLEDCLK125I/O LED display clock signal, the signal is a discontinued clock for LED data serial shift out. Every clock burst have 24 cycles ( period : 160 ns), and the clock burst will be repeated with every 42ms.Miscellaneous PinsName Pin Number I/O Descriptions RSTB128I System reset input, low active.SYSCLK122I50MHz system clock inputMDC126I/O MII management clock inoutMDIO127I/O MII management data inoutUPSWEN65I Up_link switch port enabling : one of internal two_port switch port willconnect to 100M_hub domain, and another port will redirect to RMII port7.FD766I When up_link switch port enabling, this pin is port7’s full_deplex indi-cator, input from PHY. When hign , indicate port7 in running onfull_duplex mode. When low, indicate on half_duplex mode.SPD030I Port0 speed indicator, input from PHY.SPD0 input low: 100M , input high: 10M.SPD129I Port1 speed indicator, input from PHY.SPD1 input low: 100M , input high: 10M.SPD228I Port2 speed indicator, input from PHY.SPD2 input low: 100M , input high: 10M.SPD327I Port3 speed indicator, input from PHY.SPD3 input low: 100M , input high: 10M.SPD464I Port4 speed indicator, input from PHY.SPD4 input low: 100M , input high: 10M.SPD563I Port5 speed indicator, input from PHY.SPD5 input low: 100M , input high: 10M.TECHNOLOGYSPD662I Port6 speed indicator, input from PHY.SPD6 input low: 100M , input high: 10M.SPD761I Port7 speed indicator, input from PHY.SPD7 input low: 100M , input high: 10M.VCC3,31,45,59,72,103,121PWR Power pinsGND14,32,46,60,74,82,92,105,117,123GND Ground pinsPower On Configuration Set Up Table Name Pin Number I/O DescriptionsTXEN218I/O Back_pressure disable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode (back_pressure enbale) - external pull_high: back_pressure disableTXEN542I/O Auto MII_setting bypass : ( power on external jumper configuration ) - external pull_low (default ) : normal mode ( auto MII_setting); after power_on, MTD658 will auto setup PHY devices be forced in half_ duplex mode for repeater apllication.- external pull_high: auto MII_setting bypassMDC126I/O 1522 bytes packet accept enable : ( power on external jumper configura-tion )- external pull_low (default ) : normal mode ( <=1518 bytes packetaccept)- external pull_high: <= 1522 bytes packet acceptLEDCLK125I/O Hub dealy enhance : ( power on external jumper configuration ) - external pull_low (default ) : nomal hub propagation delay mode.- external pull_high: enhanced hub propagational delay mode, for cov-ering long latency PHY devices).LEDDAT124I/O External arbiter enable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode (inter_repeater bus use internal arbiter)- external pull_high: inter_repeater bus use external arbiter .Miscellaneous PinsName Pin Number I/O DescriptionsTECHNOLOGY3.0 FUNCTIONAL DESCRIPTIONSThe MTD658 is conformed to IEEE802.3 chapter 9 and IEEE802.3u clause 27 specifications. The MTD658 provides 8 Redused MII interfaces and an embedded two port switch to construct a 10M/ 100M dual speed Hub application. Two Inter-Bus are also provided for stackable 10M/100M dual speed Hub application. The MTD658 functions are described as follows:3.1 Repeat and data handling8 independent RMII ports integrated with IEEE802.3 chapter 9 and IEEE802.3u clause 27 repeater functions simultaneously. MTD658 embedded two Hub cores (10M and 100M) ,and each dedicated RMII interface port can get per port’s speed information from per port speed input pin, and thenMTD658 will switch individual port to their appropriated Hub core functions (10M or 100M).The MTD658 receive packets from each RMII ports, and redirect port’s input packet to 10M or 100M Hub core according each port’s speed. The internal IEEE802.3 chapter 9 or IEEE802.3u clause 27 repeater main state machine will starts to repeat the input packet to all ports except the input port. If larger than or equal to two ports have input packet simultaneously, this will be treated as a collision, and MTD658 will assert an arbitrary JAM pattern to all ports’ output until collision event disappear and net-work is idle.3.2 PartitionThe MTD658 provides 10M/100M auto partition/reconnection functions to guarantee the network seg-ment performance by means of dectecting a consecutive collisions. Each dedicated RMII port has implement a individual 10M/100M auto partition/reconnection state machine. If port’s consecutive colli-sion number over or equal to CClimit (10M CClimit default is 32, 100M CClimit default is 64), this port will be partitioned. Reconnection will occurs after a larger than 512 bit time packet was received or transmitted from this partitioned port without any collision.When port is under partition state, MTD658 will not accept any input messages from this port (just mon-itor input message), but will continue output repeated messages to this partition port.Some new partition criterions are also implement, such as long_collision_partition event,jabber_partition event. In 10M/100M partition state machine, longer than 1024 bit time continueous col-lision will force port enter partition state. In 100M partition state machine, if port enter jabber_on state, this port will be partitioned. In 10M, jabber_partition function is not implemented.3.3 JabberThe jabber protect function is used to prevent an illegally long packet reception. After the MTD658 received a longer than 65536 +/- 6.25% bit times packet, this receive port‘s receive/transmit path will be inhibited until carrier is no longer detected.3.4 MII SettingDue to HUB is an half duplex device, the MTD658 need to force all connected phsical devices to work in half duplex environment. The MTD658 will setting all PHY’s SMI register 4’s half/full duplex bit during power on, and than restart auto-negotiation procedure to work in half duplex mode, and the PHY’s device ID should be set by PCB maker from 5’h04 - 5’h0b(port0-7).3.5 Inter-Bus InterfaceTwo Inter-Bus Interface are provided by the MTD658, One is 10M Inter-Bus Interface, the other is 100M Inter-Bus Interface. The Inter-Bus interface is designed for stackable hub application. For each domain, up to 4 MTD658s can be stacked through this Inter-Bus without any external arbitration logic. The Inter-Bus Interface includes IMASTER, IDATA (100M: use IDAT<3:0>, 10M: use only IDAT), REQOUT, REQIN0-2, ICLK, IACKB, ICOLB pins. IMASTER decide which MTD658 can arbitrate the Inter-Bus, and only one MTD658’s IMASTER can be tie high in a stackable Hub. IDATA are synchronous with ICLK. The MTD658 output REQOUT to inform Inter-Bus Interface that it need the Inter-Bus right. WhenTECHNOLOGYREQOUT , but IACKB is asserted, means this MTD658 can get data from IDATA bus. When only one MTD658 output REQOUT to Inter-Bus Interface, IACKB will be asserted by Inter-Bus master device, If larger than two MTD658’s REQOUT were asserted, Inter-Bus master will not assert IACKB , but will assert ICOLB to inform all the connected MTD658s.The Inter-Bus interface can also be programmed to EXT_ARB mode, using LEDDAT pin’s jumper set-ting. In this mode, Inter-Bus interface need an external arbitration logic to arbitrate Inter-Bus operation. And in this mode, the stackable capability is not limitted by the MTD658’s REQIN pins number.3.6 10M/100M packet SwitchThe MTD658 inplements a 10/100M two port switch for 10M/100M packet switching. Total 2K address entrys are provided for packets’ SA learning and DA routing; and alsoprovide automatic aging function ( aging time = 300secs). The input packet from 10MHub ( or 100M Hub) will be stored to external memory first, while packet is good for forward ( CRC chech ok, 64Bytes < length > 1518Bytes, and not local packets ) , than forward this packet to 100M Hub (or 10M Hub).3.7 Uplink Switch PortThe MTD658 can config one switch port as an uplink switch port. When UPSWEN pin is high, and IMASTER pin is low, one of the intenal switch port is connect to 100M HUB, the other is connected to RMII port 7. In uplink switch mode, port 7 can work in 10M/100M(from SPEED7 pin), half/fullduplex(from P7FULL pin) mode.3.8 Memory InterfaceThe MTD658 use asynchronous SRAM as two port switchs’ packet buffers, total has 128K byte exter-nal memory for packet buffering.3.9 MII managementThe MTD658 can be managed through MDC, MDIO pins. The MTD658 implements 3 MII registers for function control and status report (see Section4.0 on page).The management frame format is compliant to IEEE802.3u clause 22, and the device ID is fixed to 5’h1f internally.3.10 LED displayThe MTD658 implements three display modes, port RX activity, 10/100M domain collision, port parti-tion. The LED data pin LEDDAT is high actived.One strobe pin LEDCLK(24 burst clock/per 42ms) is used to latch serial LEDDAT information, and user can shift the latched data into byte aligned shift register to drive LEDs.4.0 RegistersThe MTD658 implements 3 MII registers, define as following tables:TABLE 1. MII registersREGBits Name R/W Descriptions Default NO0CtlReg0R/W CONTROL REGISTER 00Reserved.1’b01DisPar10Set this bit will disable 10M hub core partition function.1’b02DisPar100Set this bit will disable 100M hub core partition function.1’b03DisJab10Set this bit will disable 10M hub core Jabber function.1’b04DisJab100Set this bit will disable 100M hub core Jabber function.1’b05-8Reserved4’b000TECHNOLOGY"R/W" means read/writable.10CClimit10Set "1" will program 10M partition cclimit to 64.1’b0(32)11-15Reserved 2’b001CtlReg1R/W CONTROL REGISTER 116’h00000-7DisPortSet bits "1" disable port 0-7 RMII ports.8’h0008-15Reserved.2Reserved 3Reserved4AgeRegR/W AGE REGISTERTABLE 1. MII registers REG NOBits Name R/WDescriptionsDefaultTECHNOLOGY5.0 Electrical Characteristics5.1 Absolute Maximum Ratings5.2 Recommended Operating Conditions5.3 DC Electrical Characteristics(Under recommended operating conditions and Vcc = 4.75 ~ 5.25V, Tj = 0 to +115 o C)Symbol Parameter RATINGUnit V CC Power Supply Voltage -0.3 to 6.0V V IN Input Voltage -0.3 to Vcc+0.3V V OUT Output Voltage -0.3 to Vcc+0.3VT STGStorage Temperature-55 to 150οCSymbol ParameterMin.Typ.Max.Unit V CC Commercial Power Supply Voltage 4.755 5.25V Industrial Power Supply Voltage 4.55 5.5V V IN Input Voltage0-Vcc VT OPRCommercial Junction Operating Temperature 025115οC Industrial Junction Operating Temperature-4025125οCSymbol Parameter Conditions Min.Typ.Max.Unit I IL Input Leakage Current no pull-up or down-11uA I OZ Tri-state Leakage Current -1010uA C IN Input Capacitance 3pF C OUT Output Capacitance3pF C BID3Bi-direction buffer Capacitance 3pF V IL Input Low Voltage CMOS0.3*Vcc V V IH Input High Voltage CMOS 0.7*VccV V OH Output High Voltage I OL =2,4,8,12,16,24mA 0.4V V OL Output Low VoltageI OH =2,4,8,12,16,24mA 3.5V R IInput Pull-up/down resistanceV IL =0V or V IH =V CC50KOhmTECHNOLOGY5.4 Electrical CharacteristicsSymbol ParameterMin.Typ.Max.Unit NoteT1RMII input setup time 1nS T2RMII input hold time 1nS T3RMII output setup time 3nS T4RMII output hold time 5nSSymbol ParameterMin.Typ.Max.Unit NoteT5WEB pulse width 11.516nS T6OEB pulse width20nS T7Write Address setup time 1018.5nS T8Write Address hold time 1.57nS T9Write Data setup time 1012nS T10Write Data hold time14nS T11Read Address setup time 19.5nS T12Read Address hold timenSFIGURE 1. RMII timingREFCLK CRSDV TXEN TXD[1:0]RXD[1:0]T1T2T3T4Valid ValidFIGURE 2. Memory Interface TimingWEB A[16:0]T9T5T7T8ValidOEB T6ValidD[7:0]ValidValidT10T11T12TECHNOLOGYNote 1 : In 10M/100M Inter-Bus interface, T15-T18 have the same value.Symbol Parameter Min.Typ.Max.Unit NoteT13Inter-Bus output setup time(100M)1520nS Inter-Bus output setup time(10M)50nS T14Inter-Bus output hold time(100M)2025nS Inter-Bus output hold time(10M)50nSSymbol ParameterMin.Typ.Max.Unit Note T15Inter-Bus master REQOUT asserted to IACKB asserted propogation delay 720nS 1T16Inter-Bus master REQOUT deas-serted to IACKB deasserted propo-gation delay15nS1T17Inter-Bus master REQIN asserted to IACKB deasserted(ICOLB asserted) propogation delay(SOJ)517nS 1T18Inter-Bus master REQOUT deas-serted to IACKB asserted(ICOLBde-asserted) propogation delay(EOJ)015nS 1FIGURE 3. Inter-Bus Interface timing IICLK100,T13T14IDATA100,ValidIDAT10ICLK10FIGURE 4. Inter-Bus Interface timing IIIMASTER REQOUT100,REQIN100,IACKB100,ICOLB100,T15T17T16T18REQOUT10REQIN10IACKB10ICOLB10TECHNOLOGYNote 2 : In 10M/100M Inter-Bus interface, T19-T22 have the same value.Symbol ParameterMin.Typ.Max.Unit Note T19Inter-Bus slave REQOUT asserted to IACKB asserted propogation delay 520nS 2T20Inter-Bus slave REQOUT deasserted to IACKB deasserted propogation delay520nS2T21Inter-Bus slave REQIN asserted to IACKB deasserted(ICOLB asserted) propogation delay(SOJ)520nS 2T22Inter-Bus slave REQOUT deasserted to IACKB asserted(ICOLBdeas-serted) propogation delay(EOJ)520nS 2Symbol Parameter Min.Typ.Max.Unit NoteT23MDC clock cycle 400nS T23MDIO input setup time10nSFIGURE 5. Inter-Bus Interface timing IIIIMASTER REQOUT100,REQIN100,IACKB100,ICOLB100,T19T21T20T22REQOUT10REQIN10IACKB10ICOLB10FIGURE 6. MII Management timing MDC T24T25MDIOValidMDC T26T27MDIOValidT23Input TimingOutput TimingTECHNOLOGYT25MDIO input hold time 10nS T26MDIO output setup time 182194nS T27MDIO output hold time206218nSSymbol ParameterMin.Typ.Max.Unit NoteT2824 LED burst clocks duration 3.84uS T29LED burst clock cycle time 42mS T30LED burst clock cycle160nS T31LEDDAT to LEDCLK setup time 80nS T32LEDDAT to LEDCLK setup time80nSSymbol Parameter Min.Typ.Max.Unit NoteFIGURE 7. LED output timingLEDCLKLEDDAT........LEDCLKT28T29T30T31T32TECHNOLOGY6.0 128 pin PQFP Package Data103128138396465102eBD 1DE 1Eper side.. Total in excess of the B dimemsion at maximum material Symbol Dimension in inch Dimension in mm Min Norm Max Min Norm Max A --0.134-- 3.40A10.010--0.25--A20.1070.1120.1172.73 2.85 2.97B 0.0070.0090.0110.170.220.27C 0.004-0.0080.09-0.20D 0.9060.9130.92123.0023.2023.40 D 10.7830.7870.79119.9020.0020.10E0.6690.6770.68517.0017.2017.40 E 10.5470.5510.55513.9014.0014.10e 0.020 BSC 0.50 BSC L0.0290.0350.0410.730.88 1.03L10.063 BSC 1.60 BSCy --0.004--0.10z0o-7o0o -7o。

2016年联发科MTK处理器排行榜联发科MTK是现在的主流芯片之一，绝大多数的入门级手机以及部分中高端手机都使用的是联发科的处理器方案。

联发科目前的主流芯片，高端：helio x10、Helio X25、Helio X20，中端：Helio P10、MT6753，低端：MT6750、MT6738、MT6737等。

下面小编整理了联发科MTK处理器排行供大家参考，如有错误欢迎大家指正！1、联发科MTK Helio X30(暂无上市)使用台积电10nm FinFET新工艺制造，拥有两个2.8GHzA7x(下代架构)、四个2.2GHz A53、四个2GHz A35 CPU核心，以及定制的四核心PowerVR 7XT GPU，同时支持2600万像素摄像头、双主摄像头、VR虚拟现实，并整合全网通基带，最高支持LTE Cat.13。

支持四通道的LPDDR4，最大容量8GB。

2、联发科MTK MT6797T/Helio X25 (2016年)Helio X25 MT6797T Helio X20的高频加强版，采用了三集群设计，集成两个2.5GHz A72、四个2.0GHz A53、四个1.4GHz A53 CPU核心与Mali-T880 MP4 GPU核心，同时支持LPDDR3内存、eMMC 5.1存储、LTE Cat.6全网通基带。

3、联发科MTKMT6797/Helio X20(2016年)Helio X20是一颗64位十核的三簇SOC，两个最高性能的Cortex A72核心，最高主频达2.3GHz(增强版X25主频可以达到2.5GHZ)，64位Mali-T880 MP4 780MHz GPU，支持七模全频网络、支持2500万像素摄像头、2K显示屏、4K视频拍摄、快充3.0(20分钟充满75%)、Vulkan API、移动支付平台等。

4、联发科MTKMT6795/Helio X10（2015年04月01日）是联发科MTK在2015年推出的一款旗舰处理器，专门为高端智能手机打造的SoC。