pcm1609a 数字解码芯片特性

BurrĆBrown Productsfrom Texas InstrumentsFEATURES APPLICATIONSDESCRIPTIONPCM1609ASLES145B–AUGUST2005–REVISED MARCH2008 24-BIT192-kHz SAMPLING8-CHANNEL ENHANCED MULTILEVELDELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER•Integrated A/V Receivers•24-Bit Resolution•DVD Movie and Audio Players•Analog Performance•HDTV Receivers–Dynamic Range:105dB Typical•Car Audio Systems–SNR:105dB Typical•DVD Add-On Cards for High-End PCs –THD+N:0.002%Typical•Digital Audio Workstations –Full-Scale Output:3.1Vp-p,Typical•Other Multichannel Audio Systems•4×/8×Oversampling Interpolation Filter–Stop-Band Attenuation:–55dB–Pass-Band Ripple:±0.03dB The PCM1609A is a CMOS,monolithic integrated •Sampling Frequency:5kHz to200kHz circuit that features eight24-bit audio digital-to-analogconverters(DACs)and support circuitry in a small •Accepts16-,18-,20-,and24-Bit Audio DataLQFP-48package.The DACs use Texas Instruments •Data Formats:Standard,I2S,and Left-Justified(TI)enhanced multilevel delta-sigma architecture that •System Clock:128f S,192f S,256f S,384f S,employs fourth-order noise shaping and8-level 512f S,or768f S amplitude quantization to achieve excellentsignal-to-noise performance and a high tolerance to •User-Programmable Functionsclock jitter.–Digital Attenuation:0dB to–63dB,The PCM1609A accepts industry-standard audio data0.5dB/Stepformats with16-to24-bit audio data.Sampling rates –Soft Muteup to200kHz are supported.A full set of –Zero Flags Can Be Used as user-programmable functions is accessible through a General-Purpose Logic Output4-wire serial control port that supports register writeand read functions.–Digital De-Emphasis–Digital Filter Rolloff:Sharp or Slow•Dual-Supply Operation–5-V Analog– 3.3-V Digital•5-V Tolerant Digital Logic Inputs•Package:LQFP-48Please be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.FilterPro is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Copyright©2005–2008,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters. ABSOLUTE MAXIMUM RATINGS(1)RECOMMENDED OPERATING CONDITIONSPCM1609ASLES145B–AUGUST2005–REVISED MARCH2008This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.over operating free-air temperature range(unless otherwise noted)V DD–0.3V to4V Power-supply voltage rangeV CC–0.3V to6.5VV CC,V DD Supply voltage difference V CC–V DD<3V Ground voltage differences±0.1VDigital input voltage range–0.3V to6.5VInput current(except power supply pins)±10mAOperating temperature range under bias–40°C to125°CStorage temperature range–55°C to150°CJunction temperature150°CLead temperature(soldering)260°C,5sPackage temperature(reflow,peak)260°C(1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.MIN NOM MAX UNIT Digital supply voltage,V DD3 3.3 3.6V Analog supply voltage,V CC 4.55 5.5V Digital input logic family TTLSystem clock8.19236.864MHz Digital input clock frequencySampling clock32192kHz Analog output load resistance5kΩAnalog output load capacitance50pF Digital output load capacitance20pF Operating free-air temperature,T A–2585°C2Submit Documentation Feedback Copyright©2005–2008,Texas Instruments IncorporatedProduct Folder Link(s):PCM1609AELECTRICAL CHARACTERISTICSPCM1609A SLES145B–AUGUST2005–REVISED MARCH2008All specifications at T A=25°C,V CC=5V,V DD=3.3V,system clock=384f S(f S=44.1kHz),and24-bit data(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION24Bits DATA FORMATAudio data interface formats Standard,I2S,left-justifiedAudio data bit length16/18/20/24bit,selectableAudio data format MSB first,binary2s complementf S Sampling frequency5200kHz128f S,192f S,256f S, System clock frequency384f S,512f S,768f SDIGITAL INPUT/OUTPUTLogic family TTL compatibleV IH2Input logic level VdcV IL0.8I IH(1)V IN=V DD10I IL(1)V IN=0V–10Input logic currentµAI IH(2)V IN=V DD65100I IL(2)V IN=0V–10V OH I OH=–4mA 2.4Output logic level VdcV OL I OL=4mA1DYNAMIC PERFORMANCE(3)(4)V OUT=0dB,f S=44.1kHz0.002%0.008%V OUT=0dB,f S=96kHz0.004%V OUT=0dB,f S=192kHz0.005%THD+N Total harmonic distortion+noiseV OUT=–60dB,f S=44.1kHz0.7%V OUT=–60dB,f S=96kHz0.9%V OUT=–60dB,f S=192kHz1%EIAJ,A-weighted,f S=44.1kHz98105Dynamic range A-weighted,f S=96kHz103dBA-weighted,f S=192kHz102EIAJ,A-weighted,f S=44.1kHz98105SNR Signal-to-noise ratio A-weighted,f S=96kHz103dBA-weighted,f S=192kHz102f S=44.1kHz94103Channel separation f S=96kHz101dBf S=192kHz100Level linearity error V OUT=–90dB±0.5dBDC ACCURACYGain error±1±6%of FSRGain mismatch,channel-to-channel±1±3%of FSRBipolar zero error V OUT=0.5V CC at bipolar zero±30±60mV(1)Pins31,38,40,41,45–47(DATA4,SCKI,BCK,LRCK,DATA1,DATA2,DATA3)(2)Pins34–37(MDI,MC,ML,RST)(3)Analog performance specifications are tested using a System Two™Cascade audio measurement system by Audio Precision™with400-Hz HPF on,30-kHz LPF on,average mode with20-kHz bandwidth limiting.The load connected to the analog output is5kΩor larger via capacitive loading.(4)Conditions in192-kHz operation are system clock=128f S and oversampling rate=64f S in register12.Copyright©2005–2008,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):PCM1609APCM1609ASLES145B–AUGUST 2005–REVISED MARCH 2008ELECTRICAL CHARACTERISTICS (continued)All specifications at T A =25°C,V CC =5V,V DD =3.3V,system clock =384f S (f S =44.1kHz),and 24-bit data (unless otherwise noted)PARAMETERTEST CONDITIONSMIN TYP MAX UNIT ANALOG OUTPUTOutput voltage Full scale (–0dB)0.62V CC Vp-p Center voltage 0.5V CCVdc Load impedanceAC load5k ΩDIGITAL FILTER PERFORMANCEGroup delay time 20/f S De-emphasis error±0.1dBFilter Characteristics 1,Sharp RolloffPass band ±0.03dB 0.454f S Pass band –3dB0.487f SStop band 0.546f SPass-band ripple ±0.03dB Stop-band attenuation Stop band =0.546f S –50dB Stop-band attenuationStop band =0.567f S –55dBFilter Characteristics 2,Slow RolloffPass band ±0.5dB 0.198f S Pass band –3dB0.39f SStop band 0.884f SPass-band ripple ±0.5dB Stop-band attenuationStop band =0.884f S –40dBANALOG FILTER PERFORMANCEf =20kHz –0.03Frequency responsedBf =44kHz–0.2POWER-SUPPLY REQUIREMENTS (5)V DD 3 3.3 3.6Voltage rangeVdcV CC 4.55 5.5f S =44.1kHz 1825I DD (6)f S =96kHz 40f S =192kHz 40Supply currentmAf S =44.1kHz 3346I CCf S =96kHz 36f S =192kHz 36f S =44.1kHz224313Power dissipationf S =96kHz 312mWf S =192kHz312TEMPERATURE RANGE T A Operating temperature –2585°C θJA Thermal resistance100°C/W(5)Conditions in 192-kHz operation are system clock =128f S and oversampling rate =64f S in register 12.(6)SCKO is disabled.4Submit Documentation FeedbackCopyright ©2005–2008,Texas Instruments IncorporatedProduct Folder Link(s):PCM1609AOUT 1OUT 2OUT 3COMOUT 4OUT 5OUT 6OUT 7OUT 8B0033-03Z E R O 1/G P O A G N D 1−V C C 1−V D D G N DS C K Z E R O 2/G P O Z E R O 3/G P O Z E R O 4/G P O Z E R O 5/G P O Z E R O 6/G P O Z E R O Z E R O TEST RST ML MC MDI MDOPCM1609ASLES145B–AUGUST 2005–REVISED MARCH 2008FUNCTIONAL BLOCK DIAGRAMCopyright ©2005–2008,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):PCM1609ACC 3CC 4OUT 8CC 5OUT 7COM OUT 1OUT 2PT PACKAGE (TOP VIEW)Z E R O 1/G P O Z E R O 2/G P O Z E R O 3/G P O Z E R O 4/G P O Z E R O 5/G P O Z E R O 6/G P O N N V O U T V O U T V O U T V O U T LCD ID OE R O 8A T A 4E R O 7CC C 1G N D 1C C 2G N D 2P0028-03PCM1609ASLES145B–AUGUST 2005–REVISED MARCH 2008TERMINAL FUNCTIONSTERMINAL I/O DESCRIPTIONNAME NO.AGND127–Analog ground AGND225–Analog ground AGND323–Analog ground AGND421–Analog ground AGND517–Analog ground AGND619–Analog groundBCK 40I Shift clock input for serial audio data.Clock must be one of 32f S ,48f S ,or 64f S .(1)DATA145I Serial audio data for V OUT 1and V OUT 2(1)DATA246I Serial audio data for V OUT 3and V OUT 4(1)DATA347I Serial audio data for V OUT 5and V OUT 6(1)DATA431I Serial audio data for V OUT 7and V OUT 8(1)DGND 44–Digital groundLRCK 41I Left and right clock.This clock is equal to the sampling rate,f S .(1)MC 35I Shift clock for serial control port(2)MDI 34I Serial data input for serial control port(2)MDO 33OSerial data output for serial control port(3)(1)Schmitt-trigger input,5-V tolerant(2)Schmitt-trigger input with internal pulldown,5-V tolerant (3)3-state output6Submit Documentation FeedbackCopyright ©2005–2008,Texas Instruments IncorporatedProduct Folder Link(s):PCM1609APCM1609ASLES145B–AUGUST2005–REVISED MARCH2008 TERMINAL FUNCTIONS(continued)TERMINALI/O DESCRIPTIONNAME NO.ML36I Latch enable for serial control port(2)NC7,8,29–No connectionRST37I System reset,active low(2)SCKI38I System clock input.Input frequency is one of128f S,192f S,256f S,384f S,512f S,or768f S.(1)Buffered clock output.Output frequency is one of128f S,192f S,256f S,384f S,512f S,or768f S,or SCKO39Oone-half of128f S,192f S,256f S,384f S,512f S,or768f S.TEST42–Test.This pin should be connected to DGND.(2)V CC128–Analog power supply,5VV CC226–Analog power supply,5VV CC324–Analog power supply,5VV CC422–Analog power supply,5VV CC518–Analog power supply,5VV COM15O Common voltage.This pin should be bypassed with a10-µF capacitor to AGND.V DD43–Digital power supply,3.3VV OUT114O Voltage output of audio signal corresponding to left channel on DATA1V OUT213O Voltage output of audio signal corresponding to right channel on DATA1V OUT312O Voltage output of audio signal corresponding to left channel on DATA2V OUT411O Voltage output of audio signal corresponding to right channel on DATA2V OUT510O Voltage output of audio signal corresponding to left channel on DATA3V OUT69O Voltage output of audio signal corresponding to right channel on DATA3V OUT716O Voltage output of audio signal corresponding to left channel on DATA4V OUT820O Voltage output of audio signal corresponding to right channel on DATA4ZERO1/GPO11O Zero-data flag for V OUT1.Can also be used as GPO pin.ZERO2/GPO22O Zero-data flag for V OUT2.Can also be used as GPO pin.ZERO3/GPO33O Zero-data flag for V OUT3.Can also be used as GPO pin.ZERO4/GPO44O Zero-data flag for V OUT4.Can also be used as GPO pin.ZERO5/GPO55O Zero-data flag for V OUT5.Can also be used as GPO pin.ZERO6/GPO66O Zero-data flag for V OUT6.Can also be used as GPO pin.ZERO730O Zero-data flag for V OUT7ZERO832O Zero-data flag for V OUT8ZEROA48O Zero-data flag.Logical AND of ZERO1through ZERO8.Copyright©2005–2008,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):PCM1609ATYPICAL PERFORMANCE CURVESDigital Filter (De-Emphasis Off)Frequency [× f S ]−140−120−100−80−60−40−20001234A m p l i t u d e − d BG001Frequency [× f S ]−0.05−0.04−0.03−0.02−0.010.000.010.020.030.040.050.00.10.20.30.40.5A m p l i t u d e − d BG002Frequency [× f S ]−140−120−100−80−60−40−20001234A m p l i t u d e − d BG003Frequency [× f S ]−5−4−3−2−10123450.00.10.20.30.40.5A m p l i t u d e − d BG004PCM1609ASLES145B–AUGUST 2005–REVISED MARCH 2008All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =44.1kHz,system clock =384f S ,and 24-bit input data (unlessotherwise noted)FREQUENCY RESPONSE (SHARP ROLLOFF)PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF)Figure 1.Figure 2.FREQUENCY RESPONSE (SLOW ROLLOFF)TRANSITION CHARACTERISTICS (SLOW ROLLOFF)Figure 3.Figure 4.8Submit Documentation FeedbackCopyright ©2005–2008,Texas Instruments IncorporatedProduct Folder Link(s):PCM1609ADigital Filter (De-Emphasis Curves)f − Frequency − kHz002468101214L e v e l − d BG005f − Frequency − kHz024********E r r o r − d BG006f − Frequency − kHz −10−9−8−7−6−5−4−3−2−1002468101214161820L e v e l − d BG007f − Frequency − kHz−0.5−0.4−0.3−0.2−0.10.00.10.20.30.40.502468101214161820E r r o r − d BG008f − Frequency − kHz −10−9−8−7−6−5−4−3−2−100246810121416182022L e v e l − d BG009f − Frequency − kHz−0.5−0.4−0.3−0.2−0.10.00.10.20.30.40.50246810121416182022E r r o r − d BG010PCM1609ASLES145B–AUGUST 2005–REVISED MARCH 2008TYPICAL PERFORMANCE CURVES (continued)All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =44.1kHz,system clock =384f S ,and 24-bit input data (unless otherwise noted)DE-EMPHASIS (f S =32kHz)DE-EMPHASIS ERROR (f S =32kHz)Figure 5.Figure 6.DE-EMPHASIS (f S =44.1kHz)DE-EMPHASIS ERROR (f S =44.1kHz)Figure 7.Figure 8.DE-EMPHASIS (f S =48kHz)DE-EMPHASIS ERROR (f S =48kHz)Figure 9.Figure 10.Copyright ©2005–2008,Texas Instruments IncorporatedSubmit Documentation Feedback9Product Folder Link(s):PCM1609ATYPICAL PERFORMANCE CURVES (continued)ANALOG DYNAMIC PERFORMANCESupply Voltage CharacteristicsV CC − Supply Voltage − V96981001021041061081104.04.55.05.56.0D y n a m i c R a n g e − d BG012V CC − Supply Voltage − V4.04.55.05.56.0T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %100.010.001G0110.11V CC− Supply Voltage − V96981001021041061081104.04.55.05.56.0S N R − S i g n a l -t o -N o i s e R a t i o − d BG013V CC − Supply Voltage − V96981001021041061081104.04.55.05.56.0C h a n n e l S e p a r a t i o n − d BG014PCM1609ASLES145B–AUGUST 2005–REVISED MARCH 2008All specifications at T A =25°C,V CC =5V,V DD =3.3V,and 24-bit input data (unless otherwise noted).Conditions in 192-kHz operation are system clock =128f S ,DAC3through DAC6disabled in register 8,and oversampling rate =64f S (set by OVER bit in register 12).TOTAL HARMONIC DISTORTION +NOISEDYNAMIC RANGEvsvsSUPPLY VOLTAGESUPPLY VOLTAGE(V DD =3.3V)(V DD =3.3V)Figure 11.Figure 12.SIGNAL-TO-NOISE RATIOCHANNEL SEPARATIONvsvsSUPPLY VOLTAGESUPPLY VOLTAGE(V DD =3.3V)(V DD =3.3V)Figure 13.Figure 14.10Submit Documentation FeedbackCopyright ©2005–2008,Texas Instruments IncorporatedProduct Folder Link(s):PCM1609ATYPICAL PERFORMANCE CURVES (continued)ANALOG DYNAMIC PERFORMANCE (continued)Temperature CharacteristicsT A − Free-Air Temperature − °C9698100102104106108110−50−250255075100D y n a m i c R a n g e − d BG016T A − Free-Air Temperature − °C−50−25255075100T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %10G0150.11T A − Free-Air Temperature − °C 9698100102104106108110−50−250255075100S N R − S i g n a l -t o -N o i s e R a t i o − d BG017T A − Free-Air Temperature − °C9698100102104106108110−50−250255075100C h a n n e l S e p a r a t i o n − d BG018All specifications at T A =25°C,V CC =5V,V DD =3.3V,and 24-bit input data (unless otherwise noted).Conditions in 192-kHz operation are system clock =128f S ,DAC3through DAC6disabled in register 8,and oversampling rate =64f S (set by OVER bit in register 12).TOTAL HARMONIC DISTORTION +NOISEDYNAMIC RANGEvsvsTEMPERATURETEMPERATUREFigure 15.Figure 16.SIGNAL-TO-NOISE RATIOCHANNEL SEPARATIONvsvsTEMPERATURETEMPERATUREFigure 17.Figure 18.SYSTEM CLOCK AND RESET FUNCTIONSSYSTEM CLOCK INPUTSystem ClockHLT0005A08SYSTEM CLOCK OUTPUTThe PCM1609A requires a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators.The system clock is applied at the SCKI input (pin 38).Table 1shows examples of system clock frequencies for common audio sampling rates.Figure 19shows the timing requirements for the system clock input.For optimal performance,it is important to use a clock source with low phase jitter and noise.The PLL170x multiclock generator from Ti is an excellent choice for providing the PCM1609A system clock.Table 1.System Clock Rates for Common Audio Sampling FrequenciesSYSTEM CLOCK FREQUENCY (f SCLK )SAMPLING FREQUENCY(MHz)(kHz)128f S192f S256f S 384f S 512f S 768f S 8(1)(1) 2.048 3.072 4.096 6.14416(1)(1) 4.096 6.1448.19212.28832(1)(1)8.19212.28816.38424.57644.1(1)(1)11.289616.934422.579233.868848(1)(1)12.28818.43224.57636.86496(1)(1)24.57636.86449.152(1)19224.57636.864(1)(1)(1)(1)(1)This system clock is not supported for the given sampling frequency.SYMBOL MIN MAX UNIT t w(SCKH)System clock pulse duration,HIGH 7ns t w(SCKL)System clock pulse duration,LOW 7ns(1)1/128f S ,56f S ,1/384f S ,1/512f S ,and 1/768f S .Figure 19.System Clock TimingA buffered version of the system clock input is available at the SCKO output (pin 39).SCKO can operate at either full (f SCKI )or half (f SCKI /2)rate.The SCKO output frequency can be programmed using the CLKD bit of register 9.The SCKO output pin can also be enabled or disabled using the CLKE bit of register 9.If the SCKO output is not required,it is recommended to disable it using the CLKE bit.The default is SCKO enabled.POWER-ON AND EXTERNAL RESET FUNCTIONSV DD2.4 V 2 V 1.6 V Internal ResetSystem ClockT0014-080 VRSTInternal ResetSystem ClockT0015-06The PCM1609A includes a power-on reset function (see Figure 20).With the system clock active,and V DD >2V (typical,1.6V to 2.4V),the power-on reset function is enabled.The initialization sequence requires 1024system clocks from the time V DD >2V.After the initialization period,the PCM1609A is set to its reset default state,as described in the Mode Control Registers section of this data sheet.The PCM1609A also includes an external reset capability using the RST input (pin 37).This allows an external controller or master reset circuit to force the PCM1609A to initialize to its reset default state.For normal operation,RST should be set to a logic 1.The external reset operation and timing is shown in Figure 21.The RST pin is set to logic-0for a minimum of 20ns.After the initialization sequence is completed,the PCM1609A is set to its reset default state,as described in the Mode Control Registers section of this data sheet.During the reset period (1024system clocks),the analog outputs are forced to the bipolar zero level (or V CC /2).After the reset period,the internal registers are initialized in the next 1/f S period and,if SCKI,BCK,and LRCK are provided continuously,the PCM1609A provides proper analog output with the group delay time given in the Electrical Characteristics section of this data sheet.The external reset is especially useful in applications where there is a delay between PCM1609A power up and system-clock activation.In this case,the RST pin should be held at a logic-0level until the system clock has been activated.Figure 20.Power-On Reset TimingFigure 21.External Reset TimingAUDIO SERIAL INTERFACEThe audio serial interface for the PCM1609A consists of a5-wire synchronous serial port.It includes LRCK (pin41),BCK(pin40),DATA1(pin45),DATA2(pin46),DATA3(pin47),and DATA4(pin31).BCK is the serial audio bit clock,and is used to clock the serial data present on DATA1,DATA2,DATA3,and DATA4into the audio interface serial shift register.Serial data is clocked into the PCM1609A on the rising edge of BCK.LRCK is the serial audio left/right word clock.It is used to latch serial data into the serial audio interface internal registers. Both LRCK and BCK must be synchronous to the system clock.Ideally,it is recommended that LRCK and BCK be derived from the system clock input,SCKI.LRCK is operated at the sampling frequency(f S).BCK can be operated at32,48,or64times the sampling frequency(I2S format does not support BCK=32f S).Internal operation of the PCM1609A is synchronized with LRCK.Accordingly,internal operation of the device is suspended when the sampling rate clock(LRCK)is changed,or when SCKI and/or BCK is interrupted at least for a3-bit clock cycle.If SCKI,BCK,and LRCK are provided continuously after this suspended state,the internal operation is resynchronized automatically within a period of less than3/f S.During this resynchronization period and for a3/f S time thereafter,the analog outputs are forced to the bipolar zero level,V CC/2.External resetting is not required.AUDIO DATA FORMATS AND TIMINGThe PCM1609A supports industry-standard audio data formats,including standard,I2S,and left-justified(see Figure22).Data formats are selected using the format bits,FMT[2:0],in register9.The default data format is 24-bit standard.All formats require binary2s complement,MSB-first audio data.See Figure23for a detailed timing diagram of the serial audio interface.DATA1,DATA2,DATA3,and DATA4each carry two audio channels,designated as the left and right channels. The left-channel data always precedes the right-channel data in the serial data stream for all data formats. Table2shows the mapping of the digital input data to the analog output pins.(2) I 2S Data Format; L-Channel = LOW, R-Channel = HIGH(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW(= 48 f S,LRCK BCK DATA LRCKBCK DATA T0009-05(= 48 f S,Figure 22.Audio Data Input FormatsDATA1, DATA2,DATA3, DATA41.4 VBCKLRCK T0010-071.4 V1.4 V(1)f S is the sampling frequency (e.g.,44.1kHz,48kHz,96kHz,etc.)Figure 23.Audio Interface TimingTable 2.Audio Input Data to Analog Output MappingDATA INPUT CHANNELANALOG OUTPUTDATA1Left V OUT 1DATA1Right V OUT 2DATA2Left V OUT 3DATA2Right V OUT 4DATA3Left V OUT 5DATA3Right V OUT 6DATA4Left V OUT 7DATA4RightV OUT 8SERIAL CONTROL INTERFACEREGISTER WRITE OPERATIONR0001-021 = Read Operation (Register Index is Ignored)MLMCMDI T0048-02SINGLE REGISTER READ OPERATIONThe serial control interface is a 4-wire synchronous serial port that operates asynchronously to the serial audio interface.The serial control interface is used to program and read the on-chip mode registers.The control interface includes MDO (pin 33),MDI (pin 34),MC (pin 35),and ML (pin 36).MDO is the serial data output used to read back the values of the mode registers.MDI is the serial data input used to program the mode registers.MC is the serial bit clock used to shift data in and out of the control port.ML is the control port latch clock.All write operations for the serial control port use 16-bit data words.Figure 24shows the control data word format.The most significant bit (MSB)is the read/write (R/W)bit.When set to 0,this bit indicates a write operation.Seven bits,labeled IDX[6:0],set the register index (or address)for the write operation.The least significant eight bits,D[7:0],contain the data to be written to the register specified by IDX[6:0].Figure 25shows the functional timing diagram for writing to the serial control port.ML is held at a logic-1state until a register is to be written.To start the register write cycle,ML is set to logic 0.Sixteen clocks are then provided on MC,corresponding to the 16bits of the control data word on MDI.After the sixteenth clock cycle has completed,ML is set to logic 1to latch the data into the indexed mode control register.Figure 24.Control Data Word Format for MDIFigure 25.Write Operation TimingRead operations use the 16-bit control word format shown in Figure 24.For read operations,the R/W bit is set to 1.Read operations ignore the index bits,IDX[6:0],of the control data word.Instead,the REG[6:0]bits in control register 11are used to set the index of the register that is to be read during the read operation.Bits IDX[6:0]should be set to 00h for read operations.The details of the read operation are shown in Figure 26.First,control register 11must be written with the index of the register to be read back.Additionally,the INC bit must be set to logic 0in order to disable the auto-increment read function.The read cycle is then initiated by setting ML to logic 0and setting the R/W bit of the control data word to logic 1,indicating a read operation.MDO remains in a high-impedance state until the last eight bits of the 16-bit read cycle,which correspond to the eight data bits of the register indexed by the REG[6:0]bits of control register 11.The read cycle is completed when ML is set to 1,immediately after the MC clock cycle for the least significant bit (LSB)of the indexed control register has completed.INC = 1 (Auto-Increment Read)INDEX “N”ML10000000X XX X X X X XD0D1D2D3D4D5D6D7High Impedance MCMDI MDO INDEX “Y”MLX X X X X X X X X X X X XX X XD0D1D2D3D4D5D6D7High ImpedanceMCMDI MDO INDEX “N + 1”D0D1D2D3D4D5D6D7INC = 0 (Single-Register Read)INDEX “N”ML10000000XX X X X X X XD0D1D2D3D4D5D6D7High Impedance MCMDI MDO T0075-01AUTO-INCREMENT READ OPERATIONNOTES:X =Don’t careY =Last register to be readIn single-register read (INC =0),the index that indicates the register to be read in read operation can be set by REG[6:0]in register 11.For example,setting REG[6:0]=0001001b means reading from register 9.In auto-increment read (INC =1),the index REG[6:0]indicates the first register to be read.For example,setting REG[6:0]=0001001b means reading registers from 9to Y.Y is determined by the low-to-high transition of ML in serial mode control.Figure 26.Read Operation TimingThe auto-increment read function allows for multiple registers to be read sequentially.The auto-increment read function is enabled by setting the INC bit of control register 11to 1.The sequence always starts with the register indexed by the REG[6:0]bits in control register 11,and ends by the ML setting to 1after MC clock cycle for the LSB of the last register.。