vhdl数字频率计
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VHDL数字系统设计与仿真
作业三：数字频率计
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一．实验要求截图
二．设计思路截图
三．各模块设计思路，源程序及仿真
1.测量/校验选择模块
源程序：meas_test.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY meas_test IS
PORT(
func_sel,meas,test:IN STD_LOGIC;
CP1:OUT STD_LOGIC
);
END meas_test; ARCHITECTURE lion OF meas_test IS
BEGIN
PROCESS(func_sel,meas,test)
BEGIN
IF func_sel='1'
THEN CP1<=test;
ELSE
CP1<=meas;
END IF;
END PROCESS;
END lion;
仿真截图：
2.测频控制信号发生器模块
源程序：clk2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY clk2 IS
PORT(
clk: IN STD_LOGIC;
clk2: OUT STD_LOGIC
);
END clk2;
ARCHITECTURE lion OF clk2 IS
SIGNAL clk2_temp:STD_LOGIC;
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk='1')
THEN clk2_temp <= NOT clk2_temp;
END IF;
END PROCESS;
clk2<=clk2_temp; END lion;
仿真截图:
3.四级十进制计数模块
源程序：counter.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter IS
PORT(
RD:IN STD_LOGIC;
CP:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
C:OUT STD_LOGIC
);
END counter;
ARCHITECTURE lion OF counter IS
SIGNAL count:STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(RD,CP)
BEGIN
IF(RD='0')THEN
count<="0000000000000000";C<='0';
ELSE IF(CP'EVENT AND CP='1')
THEN IF(count="1001100110011001")
THEN count<="0000000000000000";C<='1';
ELSE IF(count(11 DOWNTO 0)="100110011001")
THEN count(15 DOWNTO 12)<=count(15 DOWNTO 12)+1;
count(11 DOWNTO 0)<="000000000000";
ELSE IF(count(7 DOWNTO 0)="10011001")
THEN count(15 DOWNTO 8)<=count(15 DOWNTO 8)+1;
count(7 DOWNTO 0)<="00000000"; C<='0';
ELSE IF(count(3 DOWNTO 0)="1001")
THEN count(15 DOWNTO 4)<=count(15 DOWNTO 4)+1; count(3 DOWNTO 0)<="0000";C<='0';
ELSE count<=count+1;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
Q<=count;
END lion;
4.送存选择/报警模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PASS_ALERT IS
PORT(
K: IN STD_LOGIC;
CLK: IN STD_LOGIC;
Q: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
C: IN STD_LOGIC;
D: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
dot: out STD_LOGIC_VECTOR(2 DOWNTO 0);
Y: out STD_LOGIC;
alert:OUT STD_LOGIC
);
END PASS_ALERT;
ARCHITECTURE lion OF PASS_ALERT IS
BEGIN
PROCESS(K,Q,C)
BEGIN IF(K='0')
THEN Y<='0';
IF(Q(15 DOWNTO 12)="0000" AND C='0')
THEN D<=Q(11 DOWNTO 0);dot<="001";alert<='0';
ELSE D<=Q(11 DOWNTO 0);dot<="001";alert<='1';
END IF;
ELSE IF(C='0')
THEN Y<='1';
D<=Q(15 DOWNTO 4);alert<='0';dot<="100";
ELSE D<=Q(15 DOWNTO 4);alert<='1';dot<="100";
END IF;
END IF;
END PROCESS;
END lion;
仿真截图：
5.锁存模块
源程序：lock_store.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LOCK_STORE IS
PORT(
Q:IN STD_LOGIC_VECTOR(11 DOWNTO 0);
--Q2:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
--Q1:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LD:IN STD_LOGIC;
D:OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
--D2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--D1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--dot:OUT STD_LOGIC;
);
END LOCK_STORE; ARCHITECTURE lion OF LOCK_STORE IS
BEGIN
PROCESS(LD)
BEGIN
IF(LD'EVENT AND LD='1')
THEN D<=Q;
END IF;
END PROCESS;
END lion;
仿真截图：
6.扫描显示电路模块
扫描源程序SCAN.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY SCAN IS
PORT(CLK:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(11 DOWNTO 0);
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SEL:OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END SCAN;
ARCHITECTURE lion OF SCAN IS
BEGIN
PROCESS(D)
VARIABLE init:BOOLEAN:=TRUE;
VARIABLE count:INTEGER:=0;
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF(D="000000000000")THEN count:=0;SEL<="00";Q<=D(3 DOWNTO 0);
ELSE IF(init) THEN count:=0;SEL<="00";Q<=D(3 DOWNTO
0);init:=FALSE;
