W134M资料

Direct Rambus™ Clock GeneratorW134M/W134S

CypressSemiconductorCorporation•3901NorthFirstStreet•SanJose,CA 95134•408-943-2600Document #: 38-07426 Rev. *B Revised December 11, 2003Features

•Differential clock source for Direct Rambus™ memory subsystem for up to 800-MHz data transfer rate

•Provide synchronization flexibility: the Rambus® Channel can optionally be synchronous to an external system or processor clock

•Power-managed output allows Rambus Channel clock to be turned off to minimize power consumption for mobile applications

•Works with Cypress CY2210, W133, W158, W159, W161, and W167 to support Intel® architecture platforms

•Low-power CMOS design packaged in a 24- pin QSOP (150-mil SSOP) packageDescription

The Cypress W134M/W134S provides the differential clocksignals for a Direct Rambus memory subsystem. It includessignals to synchronize the Direct Rambus Channel clock to anexternal system clock but can also be used in systems that donot require synchronization of the Rambus clock.

Block DiagramPin Configuration

PLL

Phase PCLKMMULT0:1REFCLK

SYNCLKNOutput Logic

LogicTestAlignment

STOPBS0:1CLK

CLKBS0S1VDDGNDCLKNCCLKBGNDVDDMULT0MULT1GND242322212019181716151413VDDIRREFCLKVDDGNDGNDPCLKMSYNCLKNGNDVDDVDDIPDSTOPBPWRDNB123456789101112元器件交易网www.cecb2b.com

W134M/W134S

Document #: 38-07426 Rev. *BPage 2 of 12Pin DefinitionsPin NameNo. Type Description

REFCLK2IReference Clock Input. Reference clock input, normally supplied by a system frequency synthesizer (Cypress W133).

PCLKM6IPhase Detector Input. The phase difference between this signal and SYNCLKN is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio Logic is not used, this pin would be connected to Ground.

SYNCLKN7IPhase Detector Input. The phase difference between this signal and PCLKM is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio Logic is not used, this pin would be connected to Ground.

STOPB11IClock Output Enable. When this input is driven to active LOW, it disables the differential Rambus Channel clocks.

PWRDNB12IActive LOW Power-down. When this input is driven to active LOW, it disables the differ-ential Rambus Channel clocks and places the W134M/W134S in power-down mode.

MULT 0:115, 14IPLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to determine the multiply ratio for the PLL for the input REFCLK.

CLK, CLKB20, 18OComplementary Output Clock. Differential Rambus Channel clock outputs.

S0, S124, 23IMode Control Input. These inputs control the operating mode of the W134M/W134S.

NC19–No Connect

VDDIR1RefVReference for REFCLK. Voltage reference for input reference clock.

VDDIPD10RefVReference for Phase Detector. Voltage reference for phase detector inputs and StopB.

VDD3, 9, 16, 22PPower Connection. Power supply for core logic and output buffers. Connected to 3.3V supply.

GND4, 5, 8, 13, 17, 21GGround Connection. Connect all ground pins to the common system ground plane.MULT10110MULT00011W134MPLL/REFCLK4.5685.333W134SPLL/REFCLK4685.333

S10101S00011MODE NormalOutput Enable TestBypassTestW134M/W134S

RefclkW133

PLLPhaseAlign

D

4DLLRACRMC

M N

GearRatioLogicPclkBusclk

SynclkPclk/M

Synclk/NW158W159W161W167

Figure 1. DDLL System ArchitectureCY2210元器件交易网www.cecb2b.com

W134M/W134S

Document #: 38-07426 Rev. *BPage 3 of 12Key Specifications

Supply Voltage:...................................... VDD = 3.3V±0.165V

Operating Temperature: ...................................0°C to +70°C

Input Threshold:..................................................1.5V typical

Maximum Input Voltage:........................................VDD+0.5V

Maximum Input Frequency:.....................................100 MHz

Output Duty Cycle:...................................40/60% worst case

Output Type:...........................Rambus signaling level (RSL)

DDLL System Architecture and Gear Ratio Logic

Figure1 shows the Distributed Delay Lock Loop (DDLL)system architecture, including the main system clock source,the Direct Rambus clock generator (DRCG), and the core logicthat contains the Rambus Access Cell (RAC), the RambusMemory Controller (RMC), and the Gear Ratio Logic. (Thisdiagram abstractly represents the differential clocks as asingle Busclk wire.)

The purpose of the DDLL is to frequency-lock and phase-alignthe core logic and Rambus clocks (Pclk and Synclk) at theRMC/RAC boundary in order to allow data transfers withoutincurring additional latency. In the DDLL architecture, a PLL isused to generate the desired Busclk frequency, while adistributed loop forms a DLL to align the phase of Pclk andSynclk at the RMC/RAC boundary.