Automating model checking for autonomous systems

4 操作本部分介绍如何设置和操作Model 4020分析仪。

4.1和4.5介绍准备步骤，从4.7开始介绍实际的操作。

4.2 事先断电检查在开始使用分析仪之前应断电检查，检查内容如下：1.看样气和载气的安装是否与安装和应用部分的要求一致（chapter 3）。

保证这些气体的安装在正确的位置，并且正确地接到分析仪的后部。

2.检查电路安装是否与安装部分（chapter 3）和输入输出表中的用法说明一致。

3.检查电路板和电缆/线的安装/连接是否正确。

4.确定记录器和报警器安装正确。

4.3 进入操作状态1.打开电源2.完成下述的空气调节之后，需要预热至少两个小时（加热传感器和取样系统）。

预热时间出厂时已经由软件设置好。

预热时，禁止点火。

4.4 气体调节4.4.1 空气1.调节空气瓶上的减压阀，将空气的压力调节到30psig。

2.调节仪器上的空气减压阀，将空气压力调节到指定的空气压力。

等空气流过传感器和预热完成之后，调节其他气体。

4.4.2 样气样气瓶压力调节到30psig（或者与样气压力匹配的压力），调节仪器上的样气调节阀，将样气压力调节到指定的样气压力。

4.4.3 标气1.将标气通入分析仪。

在样气和标气之间需要一个三通阀来实现二者间的切换。

2.将标气压力调节至30psig或者与样气压力匹配的压力。

3.调节仪器的样气压力，直到指定的样气压力，同时，旁路流量计读数为0.5到1.0SCFH。

4.4.4 燃烧气1.打开气瓶上的主阀门，将气瓶压力调节到30psig（或与样气压力匹配的压力）。

2.缓慢地打开气瓶上第二个阀门，以避免仪器上燃烧气减压阀受到过大的压力冲击。

注：LED红灯灭后，才能调节燃烧气。

4.5 点火当预热倒数计时器读数为零（传感器预热计时器）时，黄色加热器指示灯闪（表示温度控制其将温度保持在设置点上），红色点火失败指示灯亮。

预热完成后，4020会自动尝试点火，如果自动点火失败，一段时间后仪器会重新尝试点火，如果五次自动点火失败，就会显示一个点火失败信息。

UTMI+ Low Pin Interface (ULPI)SpecificationRevision 1.1October 20, 2004Revision HistoryDate CommentRevision Issue0.9 November 12, 2003 Pre-release.1.0rc1 January 3, 2004 Introduce PHY interface “modes”.Update interface timings. Clarify 4-bit data clocking.Clarify sending of RX CMD’s and interrupts.Introduce AutoResume feature.Route int pin to data(3) during 6-pin Serial Mode.Explain VBUS thresholds.Add T&MT diagram and updated text.Add new section to explain how PHY is aborted by Link.Various clarifications.1.0rc2 January 13, 2004 Add block diagram.Tighten interface timing.Modify suspend protocol to more closely resemble UTMI.Add SPKR_L and SPKR_MIC to signal list and T&MTconnector.Various clarifications.1.0rc3 January 19, 2004 Specify that PHY must send RX CMD after Reset.Link + PHY clock startup time of no more than 5.6ms for aperipheral is now mandatory.PHY output delay reduced from 10ns to 9ns.Added link decision time numbers for low speed.Various Clarifications.1.0 February 2, 2004 1.0rc3 adopted as 1.0 release.1.1rc1 September 1, 2004 Various clarifications and fixes to hold time numbers, sendingRXCMDs, FsLsSerialMode, Vbus control and monitoring,Test_J and Tesk_K signalling, Low Power Mode,Hostdisconnect, ID detection, HS SOF packets, interrupts,Carkit Mode, interface protection, No SYNC/EOP mode,linestate filtering, and AutoResume.1.1rc2 October 4, 2004 Re-arranged text in section 3.8.7.3. Updated contributors list.1.1 October 20, 2004 1.1rc2 adopted as 1.1 release.The present Specification has been circulated for the sole benefit of legally-recognized Promoters, Adopters and Contributors of the Specification. All rights are expressly reserved, including but not limited to intellectual property rights under patents, trademarks, copyrights and trade secrets. The respective Promoter's, Adopter's or Contributor's agreement entered into by Promoters, Adopters and Contributors sets forth their conditions of use of the Specification.iiPromotersARC International Inc.Conexant Systems, Inc.Mentor Graphics CorporationPhilipsSMSCTransDimension, Inc.ContributorsVertenten PhilipsBartOkur PhilipsBatuhanBillAnderson MotorolaMcInerney TransDimensionBillBooker CypressBrianARCBelangerChrisKolb ARCChrisChrisSchell PhilipsChung Wing Yan PhilipsSrokaPhilipsDaveWang PhilipsDavidWooten TransDimensionDavidSMSCEricKawamotoPhilipsMackayFarranFrazier ConexantFrankFredRoberts SynopsysFarooqConexantHassanLee TransDimensionHyunParr MentorIanStandiford TransDimensionJayPhilipsTjiaJeromeMentorSaundersMarkMohamed Benromdhane ConexantSMSCMorganMonksISINabilTaklaTengstrand ARCPeterRamanand Mandayam ConexantDouglas MentorRobSaleemMohamed Synopsys(Author)ShaunReemeyer PhilipsCypressSimonNguyenSubramanyam Sankaran PhilipsTexasInstrumentsViningSueRemple QualcommTerryChen ConexantTimothyConexantChangVincentQuestions should be emailed to lpcwg@.iiiTable of Contents1.Introduction (1)1.1General (1)1.2Naming Convention (1)1.3Acronyms and Terms (1)1.4References (1)2.Generic Low Pin Interface (2)2.1General (2)2.2Signals (2)2.3Protocol (3)2.3.1Bus Ownership (3)2.3.2Transferring Data (3)2.3.3Aborting Data (4)3.UTMI+ Low Pin Interface (5)3.1General (5)3.2Signals (6)3.3Block Diagram (7)3.4Modes (9)3.5Power On and Reset (10)3.6Interrupt Event Notification (10)3.7Timing (11)3.7.1Clock (11)3.7.2Control and Data (13)3.8Synchronous Mode (15)3.8.1ULPI Command Bytes (15)3.8.2USB Packets (18)3.8.3Register Operations (30)3.8.4Aborting ULPI Transfers (37)3.8.5USB Operations (39)3.8.6Vbus Power Control (internal and external) (52)3.8.7OTG Operations (52)3.9Low Power Mode (55)3.9.1Data Line Definition For Low Power Mode (55)3.9.2Entering Low Power Mode (55)3.9.3Exiting Low Power Mode (56)3.9.4False Resume Rejection (57)3.10Full Speed / Low Speed Serial Mode (Optional) (58)3.10.1Data Line Definition For FsLsSerialMode (58)3.10.2Entering FsLsSerialMode (59)3.10.3Exiting FsLsSerialMode (60)3.11Carkit Mode (Optional) (61)3.12Safeguarding PHY Input Signals (62)4.Registers (65)4.1Register Map (65)4.2Immediate Register Set (67)4.2.1Vendor ID and Product ID (67)4.2.2Function Control (68)4.2.3Interface Control (69)4.2.4OTG Control (71)4.2.5USB Interrupt Enable Rising (72)4.2.6USB Interrupt Enable Falling (73)4.2.7USB Interrupt Status (74)4.2.8USB Interrupt Latch (75)4.2.9Debug (76)4.2.10Scratch Register (76)4.2.11Carkit Control (77)4.2.12Carkit Interrupt Delay (77)iv4.2.13Carkit Interrupt Enable (78)4.2.14Carkit Interrupt Status (78)4.2.15Carkit Interrupt Latch (79)4.2.16Carkit Pulse Control (79)4.2.17Transmit Positive Width (80)4.2.18Transmit Negative Width (80)4.2.19Receive Polarity Recovery (80)4.2.20Reserved (81)4.2.21Access Extended Register Set (81)4.2.22Vendor-specific (81)4.3Extended Register Set (81)4.4Register Settings for all Upstream and Downstream signalling modes (81)5.T&MT Connector (83)5.1General (83)5.2Daughter-card (UUT) Specification (83)vFiguresFigure 1 – LPI generic data bus ownership (3)Figure 2 – LPI generic data transmit followed by data receive (3)Figure 3 – Link asserts stp to halt receive data (4)Figure 4 – Creating a ULPI system using wrappers (5)Figure 5 – Block diagram of ULPI PHY (7)Figure 6 – Jitter measurement planes (12)Figure 7 – ULPI timing diagram (13)Figure 8 – Clocking of 4-bit data interface compared to 8-bit interface (14)Figure 9 – Sending of RX CMD (17)Figure 10 – USB data transmit (NOPID) (18)Figure 11 – USB data transmit (PID) (19)Figure 12 – PHY drives an RX CMD to indicate EOP (FS/LS LineState timing not to scale) (20)Figure 13 – Forcing a full/low speed USB transmit error (timing not to scale) (21)Figure 14 – USB receive while dir was previously low (22)Figure 15 – USB receive while dir was previously high (23)Figure 16 – USB receive error detected mid-packet (24)Figure 17 – USB receive error during the last byte (25)Figure 18 – USB HS, FS, and LS bit lengths with respect to clock (26)Figure 19 – HS transmit-to-transmit packet timing (29)Figure 20 – HS receive-to-transmit packet timing (29)Figure 21 – Register write (30)Figure 22 – Register read (31)Figure 23 – Register read or write aborted by USB receive during TX CMD byte (31)Figure 24 – Register read turnaround cycle or Register write data cycle aborted by USB receive (32)Figure 25 – USB receive in same cycle as register read data. USB receive is delayed (33)Figure 26 – Register read followed immediately by a USB receive (33)Figure 27 – Register write followed immediately by a USB receive during stp assertion (34)Figure 28 – Register read followed by a USB receive (34)Figure 29 – Extended register write (35)Figure 30 – Extended register read (35)Figure 31 – Extended register read aborted by USB receive during extended address cycle (36)Figure 32 – PHY aborted by Link asserting stp. Link performs register write or USB transmit (37)Figure 33 – PHY aborted by Link asserting stp. Link performs register read (38)Figure 34 – Link aborts PHY. Link fails to drive a TX CMD. PHY re-asserts dir (38)Figure 35 – Hi-Speed Detection Handshake (Chirp) sequence (timing not to scale) (40)Figure 36 – Preamble sequence (D+/D- timing not to scale) (41)Figure 37 – LS Suspend and Resume (timing not to scale) (43)Figure 38 – FS Suspend and Resume (timing not to scale) (44)Figure 39 – HS Suspend and Resume (timing not to scale) (46)Figure 40 – Low Speed Remote Wake-Up from Low Power Mode (timing not to scale) (47)Figure 41 – Full Speed Remote Wake-Up from Low Power Mode (timing not to scale) (48)Figure 42 – Hi-Speed Remote Wake-Up from Low Power Mode (timing not to scale) (49)Figure 43 – Automatic resume signalling (timing not to scale) (50)Figure 44 – USB packet transmit when OpMode is set to 11b (51)Figure 45 – RX CMD V A_VBUS_VLD ≤Vbus indication source (54)Figure 46 – Entering low power mode (55)Figure 47 – Exiting low power mode when PHY provides output clock (56)Figure 48 – Exiting low power mode when Link provides input clock (56)Figure 49 – PHY stays in Low Power Mode when stp de-asserts before clock starts (57)Figure 50 – PHY re-enters Low Power Mode when stp de-asserts before dir de-asserts (57)Figure 51 – Interface behaviour when entering Serial Mode and clock is powered down (59)Figure 52 – Interface behaviour when entering Serial Mode and clock remains powered (59)Figure 53 – Interface behaviour when exiting Serial Mode and clock is not running (60)Figure 54 – Interface behaviour when exiting Serial Mode and clock is running (60)Figure 55 – PHY interface protected when the clock is running (62)Figure 56 – Power up sequence when PHY powers up before the link. Interface is protected (63)Figure 57 – PHY automatically exits Low Power Mode with interface protected (63)Figure 58 – Link resumes driving ULPI bus and asserts stp because clock is not running (64)viFigure 59 – Power up sequence when link powers up before PHY (ULPI 1.0 compliant links) (64)Figure 60 – Recommended daughter-card configuration (not to scale) (83)viiTablesTable 1 – LPI generic interface signals (2)Table 2 – PHY interface signals (6)Table 3 – Mode summary (9)Table 4 – Clock timing parameters (11)Table 5 – ULPI interface timing (13)Table 6 – Transmit Command (TX CMD) byte format (15)Table 7 – Receive Command (RX CMD) byte format (16)Table 8 – USB specification inter-packet timings (26)Table 9 – PHY pipeline delays (27)Table 10 – Link decision times (28)Table 11 – OTG Control Register power control bits (52)Table 12 – Vbus comparator thresholds (52)Table 13 – RX CMD VbusValid over-current conditions (53)Table 14 – Vbus indicators in the RX CMD required for typical applications (54)Table 15 – Interface signal mapping during Low Power Mode (55)Table 16 – Serial Mode signal mapping for 6-pin FsLsSerialMode (58)Table 17 – Serial Mode signal mapping for 3-pin FsLsSerialMode (58)Table 18 – Carkit signal mapping (61)Table 19 – Register map (66)Table 20 – Register access legend (67)Table 21 – Vendor ID and Product ID register description (67)Table 22 – Function Control register (68)Table 23 – Interface Control register (70)Table 24 – OTG Control register (71)Table 25 – USB Interrupt Enable Rising register (72)Table 26 – USB Interrupt Enable Falling register (73)Table 27 – USB Interrupt Status register (74)Table 28 – USB Interrupt Latch register (75)Table 29 – Rules for setting Interrupt Latch register bits (75)Table 30 – Debug register (76)Table 31 – Scratch register (76)Table 32 – Carkit Control Register (77)Table 33 – Carkit Interrupt Delay register (77)Table 34 – Carkit Interrupt Enable register (78)Table 35 – Carkit Interrupt Status Register (78)Table 36 – Carkit Interrupt Latch register (79)Table 37 – Carkit Pulse Control (79)Table 38 – Transmit Positive Width (80)Table 39 – Transmit Negative Width (80)Table 40 – Receive Polarity Recovery (81)Table 41 – Upstream and downstream signalling modes (82)Table 42 – T&MT connector pin view (84)Table 43 – T&MT connector pin allocation (84)Table 44 – T&MT pin description (85)viii1. Introduction1.1 GeneralThis specification defines a generic PHY interface in Chapter 2.In Chapter 3, the generic interface is applied to the UTMI+ protocol, reducing the pin count for discrete USB transceiver implementations supporting On-The-Go, host, and peripheral application spaces.Convention1.2 NamingEmphasis is placed on normal descriptive text using underlined Arial font, e.g. must.Signal names are represented using the lowercase bold Arial font, e.g. clk.Registers are represented using initial caps, bold Arial font, e.g. OTG Control.Register bits are represented using initial caps, bold italic Arial font, e.g. USB Interrupt Enable Falling. 1.3 Acronyms and TermsA-device Device with a Standard-A or Mini-A plug inserted into its receptacleB-device Device with a Standard-B or Mini-B plug inserted into its receptacleDeviceDRD Dual-RoleFPGA Field Programmable Gate ArraySpeedFS FullHNP Host Negotiation ProtocolHS Hi-SpeedLink ASIC, SIE, or FPGA that connects to an ULPI transceiverLPI Low Pin InterfaceSpeedLS LowOTG On-The-GoPHY Physical Layer (Transceiver)PLL Phase Locked LoopSE0 Single Ended ZeroSIE Serial Interface EngineSRP Session Request ProtocolT&MT Transceiver and Macrocell TesterULPI UTMI+ Low Pin InterfaceUSB Universal Serial BusUSB-IF USB Implementers ForumUTMI USB 2.0 Transceiver Macrocell InteraceUUT Unit Under Test1.4 References[Ref 1] Universal Serial Bus Specification, Revision 2.0[Ref 2] On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a[Ref 3] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, v1.05[Ref 4] UTMI+ Specification, Revision 1.0[Ref 5] CEA-2011, OTG Transceiver Specification[Ref 6] CEA-936A, Mini-USB Analog Carkit Interface Specification[Ref 7] USB 2.0 Transceiver and Macrocell Tester (T&MT) Interface Specification, Version 1.212. Generic Low Pin Interface2.1 GeneralThis section describes a generic low pin interface (LPI) between a Link and a PHY. Interface signals are defined and the basic communication protocol is described. The generic interface can be used as a common starting point for defining multiple application-specific interfaces.Chapter 3 defines the UTMI+ Low Pin Interface (ULPI), which is based on the generic interface described here. For ULPI implementations, the definitions in chapter 3 over-ride anything defined in chapter 2.2.2 SignalsThe LPI transceiver interface signals are described in Table 1. The interface described here is generic, and can be used to transport many different data types. Depending on the application, the data stream can be used to transmit and receive packets, access a register set, generate interrupts, and even redefine the interface itself. All interface signals are synchronous when clock is toggling, and asynchronous when clock is not toggling. Data stream definition is application-specific and should be explicitly defined for each application space for inter-operability.Control signals dir, stp, and nxt are specified with the assumption that the PHY is the master of the data bus. If required, an implementation can define the Link as the master. If the Link is the master of the interface, the control signal direction and protocol must be reversed.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. Both directions are allowed. All interface signals are synchronous to clock.data I/O Bi-directional data bus, driven low by the Link during idle. Bus ownership is determined by dir. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. LPI defines interface timing for single-edge data transfers with respect to rising edge of clock. An implementation may optionally define double-edge data transfers with respect to both rising and falling edges of clock.dir OUT Direction. Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives dir high to take ownership of the bus. When the PHY has no data to transfer it drives dir low and monitors the bus for Link activity. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PHY PLL is not stable.stp IN Stop. The Link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, stp indicates the last byte of data was on the bus in the previous cycle. If the PHY is sending data to the Link, stp forces the PHY to end its transfer, de-assert dir and relinquish control of the the data bus to the Link.nxt OUT Next. The PHY asserts this signal to throttle the data. When the Link is sending data to the PHY, nxt indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. When the PHY is sending data to the Link, nxt indicates when a new byte is available for the Link to consume.Table 1 – LPI generic interface signals22.3 ProtocolOwnership2.3.1 BusThe PHY is the master of the LPI bi-directional data bus. Ownership of the data bus is determined by the dir signal from the PHY, as shown in Figure 1. When dir is low, the Link can drive data on the bus. When dir is high, the PHY can drive data on the bus. A change in dir causes a turnaround cycle on the bus during which, neither Link nor PHY can drive the bus. Data during the turnaround cycle is undefined and must be ignored by both Link and PHY.The dir signal can be used to directly control the data output buffers of both PHY and Link.Figure 1 – LPI generic data bus ownershipData2.3.2 TransferringAs shown in the first half of Figure 2, the Link continuously drives the data bus to 00h during idle. The Link transmits data to the PHY by driving a non-zero value on the data bus. To signal the end of data transmission, the Link asserts stp in the cycle following the last data byte.In the second half of Figure 2, the Link receives data when the PHY asserts dir. The PHY asserts dir only when it has data to send to the Link, and keeps dir low at all other times. The PHY drives data to the Link after the turnaround cycle.The nxt signal can be used by the PHY to throttle the data during transmit and receive. During transmit, nxt may be asserted in the same cycle that the Link asserts stp.Figure 2 – LPI generic data transmit followed by data receive2.3.3 AbortingDataThe PHY can assert dir to interrupt any data being transmitted by the Link. If the Link needs to interrupt data being received from the PHY, it asserts stp for one clock cycle, as shown in Figure 3. This causes the PHY to unconditionally1 de-assert dir and accept a complete data transmit from the Link. The PHY may re-assert dir again only when the data transmit from the Link has completed.Figure 3 – Link asserts stp to halt receive data1 The PHY will not de-assert dir if the ULPI interface is not usable. For example, if the internal PLL is not stable.3. UTMI+ Low Pin Interface3.1 GeneralThis section describes how any UTMI+ core can be wrapped to convert it to the smaller LPI interface. The generic interface described in chapter 2 is used as a starting point. This section always over-rides anything stated in chapter 2. While this specification details support of UTMI+ Level 3, PHY implementers may choose to support any of the Levels defined in UTMI+.ULPI defines a PHY to Link interface of 8 or 12 signals that allows a lower pin count option for connecting to an external transceiver that may be based on the UTMI+ specification. The pin count reduction is achieved by having relatively static UTMI+ signals be accessed through registers and by providing a bi-directional data bus that carries USB data and provides a means of accessing register data on the ULPI transceiver.This specification relies on concepts and terminology that are defined in the UTMI+ specification [Ref 4]. Specifically, if a ULPI PHY design is based on an internal UTMI+ core, then that core must implement the following UTMI+ features.Linestate must accurately reflect D+/D- to within 2-3 clocks. It is up to individual Link designers to use Linestate to time bus events.Filtering to prevent spurious SE0/SE1 states appearing on Linestate due to skew between D+ and D-. Filtering of 14 clock cycles is required in Low Speed, and 2 clock cycles in Full Speed and Hi-Speed modes.The PHY must internally block the USB receive path during transmit. The receive path can be unblocked when the internal Squelch (HS) or SE0-to-J (FS/LS) is seen.TxReady must be used for all types of data transmitted, including Chirp.Due to noise on the USB, it is possible that RxActive asserts and then de-asserts without any valid data being received, and RxValid will not assert. The Link should operate normally with these data-less RxActive assertions.As shown in Figure 4, a PHY or Link based on this specification can be implemented as an almost transparent wrapper around existing UTMI+ IP cores, preserving the original UTMI+ packet timing, while reducing pin count and leaving all functionality intact. This should not be taken to imply that other implementations are not possible.Figure 4 – Creating a ULPI system using wrappers3.2 SignalsTable 2 describes the ULPI interface on the PHY. The PHY is always the master of the ULPI bus. USB and Miscellaneous signals may vary with each implementation and are given only as a guide to PHY designers.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. The PHY must be capable of providing a 60MHz output clock. Support for an input 60MHz clock is optional. If the PHY supports both clock directions, it must not use the ULPI control and data signals for setting the clock direction.Data bus. Driven to 00h by the Link when the ULPI bus is idle. Two bus widths are allowed:• 8-bit data timed on rising edge of clock.data I/O• (Optional) 4-bit data timed on rising and falling edges of clock.dir OUT Controls the direction of the data bus2. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PLL is not stable. This applies whether Link or PHY is the clock source.stp IN The Link must assert stp to signal the end of a USB transmit packet or a register write operation, and optionally to stop any receive. The stp signal must be asserted in the cycle after the last data byte is presented on the bus.nxt OUT The PHY asserts nxt to throttle all data types, except register read data and the RX CMD. Identical to RxValid during USB receive, and TxReady during USB transmit. The PHY also asserts nxt and dir simultaneously to indicate USB receive activity (RxActive), if dir was previously low. The PHY is not allowed to assert nxt during the first cycle of the TX CMD driven by the Link.USB InterfaceD+ I/O D+ pin of the USB cable. Required.D- I/O D- pin of the USB cable. Required.ID IN ID pin of the USB cable. Required for OTG-capable PHY’s.VBUS I/O V BUS pin of the USB cable. Required for OTG-capable PHY’s. Required for driving V BUS and the V BUS comparators.MiscellaneousXI IN Crystal input pin. Vendors should specify supported crystal frequencies. XO OUT Crystal output pin.C+ I/O Positive terminal of charge pump capacitor.C- I/O Negative terminal of charge pump capacitor.SPKR_L IN Optional Carkit left/mono speaker input signal.SPKR_MIC I/O Optional Carkit right speaker input or microphone output signal.RBIAS I/O Bias current resistor.Table 2 – PHY interface signals2 UTMI+ wrapper developers should note that data bus control has been reversed from UTMI to ensure that USB data reception is not interrupted by the Link.3.3 BlockDiagramAn example block diagram of a ULPI PHY is shown in Figure 5. This example is based on an internal UTMI+ Level 3 core [Ref 4], which can interface to peripheral, host, and On-The-Go Link cores. A description of each major block is given below.ULPI InterfaceUSBCableChargePumpCapacitor Figure 5 – Block diagram of ULPI PHYUTMI+ Level 3 PHY coreThe ULPI PHY may contain a core that is compliant to any UTMI+ level [Ref 4]. Signals for 16-bit data buses are not supported in ULPI. While Figure 5 shows the typical blocks for a Level 3 UTMI+ core, the PHY vendor must specify the intended UTMI+ level, and provide the functionality necessary for compliance to that level.ULPI PHY WrapperThe ULPI PHY wrapper of Figure 5 reduces the UTMI+ interface to the Low Pin Interface described in this document. All signals shown on the UTMI+ Level 3 PHY core are reduced to the ULPI interface signals clock, data, dir, stp, and nxt. The Register Map stores the relatively static signals of the UTMI+ interface. Crystal Oscillator and PLLWhen a crystal is attached to the PHY, the internal clock(s) and the external 60MHz interface clock are generated from the internal PLL. When no crystal is attached, the PHY may optionally generate the internal clock(s) from an input 60MHz clock provided by the Link.General BiasingInternal analog circuits require an accurate bias current. This is typically generated using an external, accurate reference resistor.DrvVbusExternal and ExternalVbusIndicatorThe PHY may optionally control an external VBUS power source via the optional pin DrvVbusExternal. For example, the external supply could be a charge pump or 5V power supply controlled using a power switch. The external supply is controlled by the DrvVbus and the optional DrvVbusExternal bits in the OTG Control register. The polarity of the DrvVbusExternal output pin is implementation dependent.If control of an external VBUS source is provided the PHY may optionally provide for a VBUS power source feed back signal on the optional pin ExternalVbusIndicator. If this pin is provided, the use of the pin is defined by the optional control bits in the OTG Control and Interface Control registers. See Section 3.8.6.3 for further detail.Power-On-ResetA power-on-reset circuit must be provided in the PHY. When power is first applied to the PHY, the power-on-reset will reset all circuitry and leave the ULPI interface in a usable state.Carkit OptionThe PHY may optionally support Carkit Mode [Ref 6]. While in Carkit Mode, the PHY routes speaker and microphone signals between the Link and the USB cable. In carkit mono mode, SPKR_L inputs a mono speaker signal and SPKR_MIC outputs the microphone signal, MIC. In carkit stereo mode, SPKR_L inputs the left speaker signal, and SPKR_MIC inputs the right speaker signal, SPKR_R.3.4 ModesThe ULPI interface can operate in one of five independent modes listed in Table 3. The interface is in Synchronous Mode by default. Other modes are enabled by bits in the Function Control and Interface Control registers. In Synchronous Mode, the data bus carries commands and data. In other modes, the data pins are redefined with different functionality. Synchronous Mode and Low Power Mode are mandatory.Mode Name Mode DescriptionSynchronous Mode This is the normal mode of operation. The clock is running and is stablewith the characteristics defined in section 3.6. The ULPI interface carriescommands and data that are synchronous to clock.Low Power Mode The PHY is powered down with the clock stopped. The PHY keeps dirasserted, and the data bus is redefined to carry LineState and interrupts.See section 3.9 for more information.6-pin FS/LS Serial Mode (optional) The data bus is redefined to 6-pin serial mode, including 6 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. This mode is valid only for implementations with an 8-bit data bus. See section 3.10 for more information.3-pin FS/LS Serial Mode (optional) The data bus is redefined to 3-pin serial mode, including 3 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. See section 3.10 for more information.Carkit Mode (optional) The data bus is redefined to Carkit mode [Ref 6], including 2 pins for serial UART data, and 1 pin to signal interrupt events. The clock may optionally be stopped. See section 3.11 for more information.Table 3 – Mode summary。

Service ManualRev 5.6B5 with software Pro2V080and Pro2V081 XT SERIESService Manual820 Lakeside Drive – Gurnee, IL 60031Phone: 1-800- 374-8266Fax: (847) 855-9650This document and the information contained herein, is the exclusive property of Drivecon, Inc. and represents a non-public, confidential and proprietary trade secret that may not be reproduced, disclosed to third parties, altered or otherwise employed in any manner whatsoever without the express written consent of Drivecon, Inc.Copyright © 2006 Drivecon, Inc. All rights reserved.CAUTION1. Before starting, read the instructions carefully.2. Verify all of the connections are in done in accordance to thedrawings.3. Verify the motor supply is connected correctly; faulty connections willdamage the drive.4. Check to make sure that the drive’s cover is properly installed.5. High voltages are present in the drive. Switch the power off and wait 5minutes before opening the cover.6. Insulation resistance test with a megger requires special precautions.7. Do not make any measurements inside the device when it isconnected to the 3-phase power supply.8. Do not touch the components on the circuit boards. Static voltagedischarge may cause damage to the IC-circuits.9. Check to make sure that all ventilation holes are clear and uncovered.10. Check to make sure that hot air coming from the dynamic brakingresistors cannot cause any damage.11. Do not make any inspections unless the supply has beendisconnected at the main disconnect switch.12. It is forbidden to use radiophones or portable phones near this devicewith the doors open.13. All the doors and covers must be closed during crane operation.CONTENTS1GENERAL (4)1.1Technical data (4)1.2Type mark coding (5)1.3Basic description (6)1.4Functional description (7)1.5Control methods (8)1.6Mechanical brake control (10)1.7Motor control modes (10)1.8EMC (11)1.8.1Fulfilled EMC-standards (12)2INSTALLATION (13)2.1Cooling (13)2.2Power cabling (13)2.3Control wiring (15)2.4EMC compatible grounding (16)3START-UP PROCEDURE (17)3.1Visual checks (17)3.2Checks before the first test run (17)3.3Test run without load (18)3.4Test run with load (18)3.5After the test run and autotuning (18)4PARAMETER ADJUSTMENTS (19)4.1Control keypad operation (19)4.1.1Navigation on the control keypad (20)4.1.2Value line editing (20)4.1.3Passwords (21)4.1.4Special button functions and shortcuts (21)4.1.5Monitoring (22)4.2Input selections (23)4.3Speed supervision settings (24)4.3.1Functional test run for SSU (26)4.4Open Loop motor parameter adjustments (27)4.4.1Open Loop speed control for hoisting (27)4.4.2Open Loop motor parameters for traveling (27)4.4.3Open Loop autotuning for traveling, frequency control (28)4.4.4Open Loop manual tuning for traveling (28)4.4.5Open Loop manual tuning for traveling, frequency control (29)4.4.6Open Loop manual tuning for traveling, current control (29)4.5Closed Loop motor parameter adjustments (30)4.5.1Closed Loop rated motor parameters (30)4.5.2Closed Loop autotuning, speed control (31)4.5.3Closed Loop manual tuning for hoisting, speed control (34)4.6 Brake Slip Feature (37)4.6.1 Description of brake slip feature (37)4.6.2 Activation of brake slip feature (38)4.6.3 Brake Slip Feature Field Testing Procedure (38)4.6.4 What to do in case of brake slip (39)4.6.5 Service on hoist motor/encoder/brake with Brake Slip feature active (40)5PARAMETER DESCRIPTIONS (41)6COMPONENTS (54)6.1Inverter (54)6.1.1Power supply unit (PSU) (56)6.1.2Control unit (CSU) (56)6.1.3Basic I/O board (Slot A) (57)6.1.4Relay / Thermistor board (Slot B) (58)6.1.5SSU Speed Supervision board (Slot C) (58)6.1.6I/O Extension board (Slot D) (59)6.1.7Relay Extension board (Slot E) (59)6.1.8Profibus board (Slot E) (60)6.2Reference potentiometer (61)6.3Speed sensors (62)6.3.1Encoder (62)6.3.2Bearing Sensor (63)6.3.3Proximity switch (64)6.3.4Buffer amplifier KAE234 (65)6.4Brake controllers (66)6.4.1REC12-690+DC (66)6.4.2ESD141 (66)7TROUBLESHOOTING (67)7.1Field repair actions (67)7.2Inverter fault codes (68)7.2.1Fault time data record (73)7.2.2Fault Counter (73)7.3Inverter Alarm codes (74)8SERVICE (75)8.1DC-bus electrolytic capacitors (75)8.1.1Re-forming after a long storage period (75)9DRAWINGS (76)1GENERAL1.1Technical dataOverloadability1.5 x In, 1min/10min;2.0 x In, 2s/20s Max. output voltage Equal to supply voltageSupplySupply voltage460-series 380-500VAC, 575-series 525-690VAC Allowable voltage fluctuation +/- 10%Nominal supply frequency 50/60Hz +/- 5%Signal Input LevelsDigital controls S1, S2, DIA3, DIA4, DIA5, DID1, DID2, DID3, DID4, DID5: 42 … 240VAC; 15m A Analog references AIN1: 0 … +10V and AIN2: -10 … +10V; 200k Ω load ; accuracy 0.5% Encoder feedback EA+/- and EB+/-; 0/24V; 3k Ω load; floating differential inputsControl featuresControl m ethodOpen loop or closed loop vector control Frequency control range 0 ... 250HzFrequency com mand Potentiometer, motor potentiometer, 2-4-step controller or 0 ... 10V analog signal Limit switch functions Slowdown and stop limit inputs for both directions Speed control range Open loop vector controls N ... 100% (s N = motor nominal slip)Closed loop vector control0 ... 100%Speed accuracyOpen loop vector control1% of nominal speed at speed range 10 ... 100%1/3 of m otor nom inal slip at speed below 10%Closed loop vector control0.01% of nom inal speedExtended speed range 100 ... 200% program mable Braking torque 150%ProtectionsStall preventionDuring acceleration and constant speedMotor overload protection T herm istor/Klixon based tem perature measurementOverload protectionFault is detected if the current momentarily exceeds 280% of RMS rated current Undervoltage / blown fuse Fault is detected if DC voltage drops below 333V (460-series), 460V (575-series) Overvoltage protection Fault is detected if DC voltage exceeds 911V (460-series), 1200V (575-series) Momentary power loss Imm ediate fault stopInverter overtemperature T emperature sensor on the heat sink Mechanical brake Brake contactor control relayBraking transistor Electronic supervision for the braking chopper and for the braking resistorBrake slip protection Only in closed loop and if protection function enabled, also a programm able relay output Ground fault Provided by electronic circuitryOverspeed, stall, speed differencesupervisionIndependent measurem ent using SSU board and a pulse wheel or encoderAmbient conditionsAm bient temperature -10°C ... +55°C (14°F ... 131°F) for ED ≤60%Storage tem perature -40°C ... +60°C (-31°F ... 140°F) dry. Power on >1h per year. Humidity <95%RH (no condensation)Altitude Maxim um 1000m at In. Above 1000m : In reduces 1% per each 100m.Above 3000m: consult factory.Vibration Operation: m axim um displacement amplitude 1m m at 3-15.8Hz.Maxim um acceleration amplitude 1G (9.81m/s²) at 15.8-150HzConforms to LV and EMC directives (optional).Power Class (460-series) 4004 4005 4009 4012 4016 4022 4031 4038 4045 4061 4072 4087 4105 4140 4168 4210 4245 4300 4385 4460 45904650Fram e SizeFr4 Fr4 Fr4 Fr4 Fr5 Fr5 Fr6 Fr6 Fr6 Fr7 Fr7 Fr7 Fr8 Fr8 Fr8 Fr9 Fr9 Fr10 Fr10 Fr10 Fr11 Fr11 Horsepower (Hp) at 460V 2 3 5 7.5 10 15 20 25 30 40 50 60 75100 125150 200 250 300 350 500 550 Output Current In (A) 4.5 5.6 9 12 16 22 31 38 45 61 7287105 140 168210 245 300 385 460 590 650 Max. Current 1m in (A) 10 10 15 20 27 36 48 63 72 90113 135 165 225 270315 368 450 578 690885975Max. Current 2s/20s (A) 111118243246627692122 144 174 210 280 336 349444 545 697 832 1068 1177 Power Class (575-series) 5005 5007 5010 5013 5018 5022 5027 5034 5041 5052 5062 5080 5100 5125 5144 5170Fram e SizeFr6 Fr6 Fr6 Fr6 Fr6 Fr6 Fr6 Fr7 Fr7 Fr8 Fr8 Fr8 Fr9 Fr9 Fr9 Fr9 Horsepower (Hp) at 575V 3 5 7.5101520 25 30 40 50 60 75 100 125 150 175 Output Current In (A) 5.5 7.5 10 13.5 18 22 27 34 41 52 62 80100 125 144170 Max Current 1min (A) 9 12 15 21 27 33 41 51 62 7893120 150 188 216255 Max. Current 2s/20s (A)111520273644546882104 124 160 200 213 2452891.2 Type mark codingXT Series drives can be summarized as "crane motor control systems, which controls the speed by changing the frequency of the supply voltage of a squirrel cage motor". A stepless speed adjustment can be achieved by this method.Type marking is shown below.Device name000 - Base Drive (430,440) or Pre-engineered Panel (488,489,etc…)XT - Series namex - d (Base drive vector), e (base drive vector with SSU board), s (open loop vector panel), v (closed loop vector panel)Supply voltage 4 380 - 500VAC, 50/60Hz 5 525 - 690VAC, 50/60HzPower class current handling type code See technical specificationsPanel Motion and Duty ClassXX=Base Drive only TC=Traverse class C TD=Traverse class D HC=Hoist class C HD=Hoist class D 000 XTx 4009TC 56 Software Revision codeThe latest revision may differ000 XTx4 009 TC 56 0 04Construction0 Basic wall mounted1 Through panelEMC-compatibility0 IT Network (Americas)N IEC 61800-3 Second Environment (Europe)Option board configuration 0 Standard A, B, D 1 Standard with speed supervision A, B, C, D 2 Profibus A, B, D, E 3 Profibus with speed supervision A, B, C, D, E 8 Relay A, B, D, E 9 Relay with speed supervision A, B, C, D, ESpecial1. N XP and normal boards2. N XP and lacquered boards3. NXP and fiber optic link and lacquered boards4. NXP2 and normal boards5. NXP2 and lacquered boards6. NXP2 and fiber optic link and lacquered boards1.3 Basic descriptionXT Series drives have many advantages and offer many new features, when compared to other inverter based systems, which might be used in crane applications.Inverter The XT Series drive is a crane specific inverter. The specific cranefeatures for the inverter hardware and the special software areachieved by combining the experience and know-how of craneapplications with the latest technology. The inverter uses vectorcalculations for several different motor control modes in both open andclosed loop.Crane user interface All XT Series drives have exactly the same interface with pre-designedlocations for all typical crane functions. The main part of this interfaceis carried out by a terminal strip, which has separated sections forsignals with main, control and electronics voltage levels.Brake control XT Series drive panels include a relay for brake contactor control. Thebrake contactor then controls the “parking” brake on the motor whetherit is 3-phase AC, 1-phase AC, or a DC brake coil.Electrical braking XT Series drives include an internal dynamic braking transistor, whichis dimensioned for all crane applications. The braking transistor willdissipate regenerative energy through an external braking resistor.This resistor is sized according to the drive voltage, power, and dutycycle.Control methods XT Series drives can be controlled by the electronic potentiometercontrol with 2-step pushbuttons (2 speed infinitely variable), thepotentiometer control with analog joystick-type control, the automationcontrol with PLC and radio controls, and by the multistep control with 2-5 step controllers. Any two of these control methods is programmableand available with every drive.Limit switch functions XT Series drives will come preprogrammed for slowdown and stop limit switch functions for both operating directions. If slowdown and/or stop limit switches are not used, their inputs may be programmed to other functions or to not used.Speed supervision In a non-loadbrake hoisting application the drive must include aoverspeed detection device. In XT Series drives this is called a speedsupervision unit (SSU) and is separate from the drive and is notdependent on software. This safety circuitry is used to monitor thespeed of the motor. In case of speed difference, overspeed or stall, thespeed supervision unit stops the motion immediately. A SSU board isstandard with any non-load brake hoist however can also be suppliedfor this application or any traveling application if requested.Protections XT Series drives include motor thermal protection that is based onmotor temperature measurement by thermistors or klixons placed in themotor windings. If this protection is not desired, it may be turned off inthe programming. All other protection functions are listed in thetechnical data.1.4 Functional descriptionSee circuit diagrams for following descriptions of operation.Operation when power is switched on - Slow down limit switches S11 and S21, and stop limit switches S12 and S22 are assumed to be normally closed, as well as the emergency stop button ES.- The control voltage is supplied to the drive’s control inputs (externally supplied 42VAC…230VAC control voltage). When the supply voltage is connected to the drive’s power supply and inverter will power up. If the control voltage ok and the ready circuit has all of its contacts closed, drive will be ready to operate in about 1-2 seconds.- If either one of the direction signals S1 or S2 is on, the display shows F6 and running can begin only after the direction signals have been turned off for 300ms.Normal operation – For the description of the speed reference setting options seechapter 1.5 "Control methods".– Operation starts when one of the directional inputs is given to thedrive. The drive will then close the ROB2 relay and energize the K7brake contactor, which will cause the “parking” brake to open. Thedrive will then accelerate according to the acceleration ramp settingsto the requested speed.– When the directional input is removed from the drive, it will stopaccording to the deceleration ramp settings and finish by controllingthe “parking” brake to set and hold the motor.– The dynamic braking resistor will dissipate the regenerative energyduring deceleration and hoisting in the down direction. The powersupplied to the resistor is controlled by the drive. If the brakingresistor fan(s) are included in an external resistor unit, they will startto operate when power is supplied to the braking resistors. The fancooling will continue for about 4-5 minutes after electricalregenerative braking to ensure that the temperature of the dynamicbraking resistors drops below 150°C (302°F).Other features – Slowdown limit switches S11 and S21 provide position dependentfrequency limiting.– Any reason that causes the ready circuit to open will stop theoperation of drive and sets the mechanical “parking” brake.– In case of an overload (motor overheating, etc.), the hoisting can bedisabled by removing the direction signal.– Thermistor or Klixon interface function can be used when required.– When the stop limit switch S12 or S22 opens, the brake contactor K7de-energizes and the mechanical “parking” brake will stop themotion.– Independent speed supervision unit (SSU) for applications withspeed feedback.– The speed measurement and supervision can be done either usingan encoder, bearing encoder, or pulse sensor. The measured signalsare square wave pulses. The frequency of the pulses is proportionalto the speed of the motor and if the frequency is too high, overspeedis detected. If there are no pulses a stall situation is detected. If theactual speed differs too much from the supply frequency to themotor, the speed difference supervision stops the motion.– When using a proximity switch or bearing sensor a buffer amplifiershould be used to amplify the sensor pulses and filter outdisturbances. This amplifier should be located as close to the motoras possible.1.5 Control methodsThere are four different control methods (command modes) available. At any given time 2 different control modes may be used. A selector switch and programming of the drive is required to select the desired control method when using 2 different control modes. Instructions on how to program the drive for each different type of control can be found below.EP Electronic motor potentiometer function.- Stepless control using a 2-step pushbutton controller (2 speedinfinitely variable).- EP3 stepless control using a 3-step controller (3 speedinfinitely variable).PO Potentiometer control using a joystick type controller.- Requires a single 15V power supply (supplied by the drive).- Additional amplifier is not required.AU Automation control- For any control device with an output in the range of 0-10V.- E.g. radio-controls, process computers.MS Multistep control (2-5 steps as standard).- Requires programmable digital inputs for each speedreference step.Command mode selection The command mode (EP, PO or AU) is selected by the CMS and AP inputs to the drive. Normally the selection can be done only when the motion is stopped (not when running), but in special applications it may be possible.PO- and AU-modes PO and AU modes select either of the analog inputs for speedreference. Both analog inputs can be adjusted from 0V to 10V (radio orPLC-reference) or from 10V to 6.7V (potentiometer). As default, Ain1 isused in PO-mode and Ain2 is used in AU-mode.Ain1 / PO Ain1 / PO Ain2 / AU Ain2 / AU Ain1 / PO DIA3 AP not used AP not used AP not used AP = 0 AP = 1DIA4 CMS notusedCMS = 0 CMS = 1 CMS = 1 CMS = 1EP-mode EP-mode selects the AP-button for speed reference. EP step 1 iscommand for minimum speed or hold speed. EP step 2 is theacceleration command.EP step 1 EP step 2 EP step 1 EP step 2DIA3 AP = 0 AP = 1 AP = 0 AP = 1DIA4 CMS notusedCMS notusedCMS = 0 CMS = 0Synchronization If required, two or more XT Series drives can be run in precise digitalsynchronization. A separate synchronization controller is needed forthis. The same speed reference (in EP- or PO-mode) and the correctionsignal are connected to each drive. The speed reference signal of eachdrive can also be modified separately by a PLC. Parameter selectionand proper tuning activate the synchronization functionality.Description of the control methodsEP2-control requires two 2-step pushbuttons, one for each direction. The operation is as follows: - the rest position means standstill (0-position) - while running the rest position means deceleration- when starting, step one means acceleration up to the minimum speed- when running step one (switch S1 or S2) means hold speed- step two (switch AP) means acceleration (up to the maximum speed if desired)- at the maximum speed step two does nothing because the maximum speed cannot be exceeded Pushbutton positionEP3-control requires a 3-step controller. The operation is as follows:- the rest position means standstill (0-position) - step one (switch S1 or S2) is the minimum speed command- step two (EP hold command) means hold speed - step three (switch AP) means acceleration (up to the maximum speed if desired)- when releasing the controller, step one meansdeceleration down to the minimum speed Pushbutton position rest = stopPO-control requires a controller with potentiometer. The operation is as follows:- when the controller is at the rest position the potentiometer is at the middle position causing zero speed- run commands are controlled separately by closing the direction switches (S1 and S2) - when the operator turns the controller to any direction the speed increases- the same turning angle of the controller causes a smaller change in speed, the closer the speed is to the minimum speedAU-control requires an analog reference from radio or PLC. The operation is as follows:- the speed linearly follows the input signal. 0V means zero speed and the higher the voltage, the higher the speed- run commands are controlled separately by closing the direction switches (S1 and S2)PO- and AU-modesMS-control requires a 2-5-step controller. The operation is as follows:- each step has its own frequency- the frequencies are freely selectable- when controller is set to a certain step, the drive will either accelerate or decelerate to match the requested speedMS-mode1.6 Mechanical brake controlThe brake is controlled so that while starting the motor generates torque first and then the brake is opened. The same applies for stopping; while the brake is being closed, the motor still generates torque. During a direction change, the brake is held open. The drive will decelerate the motor to a stop according to the set deceleration time when the run command is removed, so the brake is used only as a holding brake. This way brake wear is minimized. Only if a fault occurs or the emergency stop button is pushed will cause the brake to close immediately stopping the motor and the load.All motors used on cranes should use some type of electromechanical brake. Different applications may require a different type of brake. Also, different applications may require this brake to be used differently. As a default, XT Series drive panels are wired to control a single-phase AC brake. If a 3-phase brake is to be used, some wiring changes will be required. If a DC brake is being used, a brake rectifier will need to be used. The type brake rectifier that is required will depend upon the size and voltage of the brake coil.1.7 Motor control modesOpen loopXT Series drives have a built-in motor model, which calculates - one thousand times per second - the values of the motor. The input data needed for the calculation is the instantaneous value of the motor voltage from the ASIC and the measured motor current. Motor magnetic flux and shaft torque are calculated in the motor model based on the nameplate data parameters taken from motor.Open loopvector controlSpeed refInverterAsicCurrentVectorcalculationSpeedControlTorqueFluxrefM3~Frequency control Open loop (mode 0) In Open Loop Frequency Control, the frequency supplied to the motor follows the frequency reference signal given to the drive. The actual rotating speed depends on load and is equal to the slip below or above the output frequency. Even with frequency control, the vector calculation is used to keep the magnetization at a correct level for optimized torque.Current control Open Loop (mode 1) In Open Loop Current Control, the frequency supplied to the motor follows the frequency reference signal given to the drive. The motor is current controlled in smaller frequencies (typically <10Hz) and in higher frequencies the motor is voltage controlled. The current control ensures that in small frequencies the speed of the motor is almost independent of the load.Closed loopThe closed loop vector control also includes a motor model, which has simpler configuration than the open loop vector control. This is because an additional input data from the incremental encoder is available, thus eliminating additional calculations inside the drive. This measurement of the rotation of the motor is used as feedback to the motor model calculation and allows possibilities for additional checking and fine adjustments of the motor control. This is how 1000:1 speed control is achieved.Closed loop vector controlSpeed refInverterAsicCurrentVectorcalculationSpeedControlTorqueFluxrefSpeedGM3~Speed controlClosed loop (mode 3) In Closed Loop Speed Control, the frequency supplied to the motor follows the frequency reference signal given to the drive. The drive adjusts the motor frequency and with this function compensates the load-dependent slip. The slip compensation keeps the actual shaft speed constant and independent of loading conditions. With closed loop speed control it is even possible to reach zero speed with full torque.Torque control Closed loop (mode 4) In Torque Control, the shaft torque is kept equal to the reference signal provided to the drive. The motor speed depends very much on loading conditions - for example, an unloaded motor would run at full speed all the time. For safety reasons, the speed is limited between adjustable minimum and maximum speeds.1.8 EMCThe abbreviation "EMC" stands for the Electro Magnetic Compatibility. The XT Series drives contain EMC input filtering that reduces the voltage and current harmonics that are produced by the drive and generated back into the power supply. The XT Series drives used in North America have this filtering capacity modified to allow for the varying types and fluctuations in the power network. If the European Union EMC standards are necessary, the power supply must meet minimum requirements and the drive configuration for this must be specified when ordering. According to the European Union EMC directive "the apparatus shall be so constructed that:a) The electromagnetic disturbance it generates does not exceed a level allowing otherapparatus to operate as intendedb) The apparatus has an adequate level of intrinsic immunity of electromagnetic disturbance toenable it to operate as intended."Technical construction file The technical construction file describes how the frequency converters have been constructed to comply with the directive and standard requirements.Declaration of conformity With the declaration of conformity the manufacturer informs that device is manufactured to fulfill required EMC standards.CE-mark The CE marking is a declaration by a manufacturer or importer locatedin the European Economic Area that a product complies with the safetyand health requirements of the directive in question. The manufacturerdemonstrates for the authorities that the product complies with thesafety requirements within the EU.EMC Plan EMC Plan for inverters is intend to use as a guide in cases whendisturbance problems appear in crane installations, in the crane itself orin other devices in the installation environment.Environments Immunity and emission requirements are divided in two levels in the product standard according to the environments.PDSPDSFirst environment means an environment that includes domestic premises and also establishments directly connected to a low-voltage power supply network. The first environment is divided in to categories C1 and C2.XT Series drives are not intended to be used on a low-voltage public network, which supplies domestic premises. The drive may cause radio frequency interference to other devices if used on such a network.Second environment means environment that includes all establishments other than those directly connected a low-voltage power supply network. The second environment is divided in to categories C3 and C4.If rated current of the crane supply is less than 400 A, the inverters belong to the category C3, otherwise they belong to the category C4.Power drive system (PDS) means a system consisting of power and control equipment, including the XT Series drive.1.8.1Fulfilled EMC-standardsImmunityThe XT Series drive fulfills the immunity requirements defined in the EN/IEC 61800-3: 2004 for the second environment, EN 61000-6-1 (residential, commercial and light industry) and EN 61000-6-2 (industrial environment).EmissionsThe XT Series drive fulfills the emission requirements of the EN/IEC 61800-3: 2004 for the second environment.If a disturbance causes problems the EMC Plan can be used as the guide to solve those.。

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Controller blocks
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Motor and valve blocks
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Interlock blocks
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Mathematical block
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Counter blocks
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Services
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SIMATIC SIMATIC PCS neo SIMATIC Process Function Library (V3.0)
Function Manual
About this document
1
Deployment conditions
2
Basics
3
Library structure
4
Operator control blocks
CAUTION
indicates that minor personal injury can result if proper precautions are not taken.
NOTICE
indicates that property damage can result if proper precautions are not taken. If more than one degree of danger is present, the warning notice representing the highest degree of danger will be used. A notice warning of injury to persons with a safety alert symbol may also include a warning relating to property damage.