HEF4020B14-stage binary counterRev. 04 — 4 December 2008Product data sheet1.General descriptionThe HEF4020B is a 14-stage binary counter with a clock input (CP), an overridingasynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 toQ13).The counter advances on the HIGH to LOW transition of CP.A HIGH on MR clearsall counter stages and forces all outputs LOW, independent of the state of CP. Eachcounter stage is a static toggle flip-flop. A feature of the device is its high speed(typ.35MHz at V DD=15V).It operates over a recommended V DD power supply range of3V to15V referenced to V SS(usually ground). Unused inputs must be connected to V DD, V SS, or another input. It isalso suitable for use over the full industrial (−40°C to +85°C) temperature range.2.FeaturesI High speed operationI Fully static operationI 5 V, 10 V, and 15 V parametric ratingsI Standardized symmetrical output characteristicsI Operates across the full industrial temperature range−40°C to +85°CI Complies with JEDEC standard JESD 13-BI ESD protection:N HBM JESD22-A114E exceeds 2000VN MM JESD22-A115-A exceeds 200V3.ApplicationsI Industrial4.Ordering informationTable 1.Ordering informationAll types operate from−40°C to +85°C.Type number PackageName Description Version HEF4020BP DIP16plastic dual in-line package; 16-leads (300 mil)SOT38-4 HEF4020BT SO16plastic small outline package; 16 leads; body width 3.9mm SOT109-15.Functional diagramFig 1.Functional diagram001aad72214-STAGE COUNTER9Q07Q35Q44Q56Q613Q712Q814Q915Q101Q112Q123Q131011T C D MRCP Fig 2.Logic symbol Fig 3.IEC Logic symbol001aad723Q0911MR10CPQ37Q45Q54Q66Q713Q812Q914Q1015Q111Q122Q133001aad724911CT+ 10CTR14CT75461312141512133Fig 4.Logic diagram001aad725CPMRFF 0QT RDQ0Q FF 2QT RDQFF 7QT RDQ7Q FF 9QT RDQ9QFF 1QT RDQFF 8QT RDQ8QFF 10QT RDQ10QFF 11QT RDQ11QFF 12QT RDQ12QFF 13QT RDQ13QFF 3QT RDQ3QFF 4QT RDQ4Q FF 5QT RDQ5QFF 6QT RDQ6Q6.Pinning information6.1Pinning6.2Pin description7.Functional description[1]H = HIGH voltage level; L = LOW voltage level; X = don’t care;↑ = positive-going transition;↓ = negative-going transition.Fig 5.Pin configurationHEF4020BQ11V DD Q12Q10Q13Q9Q5Q7Q4Q8Q6MR Q3CP V SSQ0001aaj10112345678109121114131615Table 2.Pin descriptionSymbol PinDescriptionQ3 to Q137, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3parallel output (Q3 to Q13)V SS 8ground supply voltage Q09parallel outputCP 10clock input (HIGH-to-LOW edge triggered)MR 11master reset input (active HIGH)V DD16supply voltageTable 3.Functional table [1]Input OutputCPMR Q0, Q3 to Q13↑L no change ↓L count XHL8.Limiting values[1]For DIP16 package: P tot derates linearly with 12 mW/K above 70°C.[2]For SO16 package: P tot derates linearly with 8 mW/K above 70°C.Fig 6.Timing diagram001aad7261248163264128256512102420484096CP input MR inputQ0Q3Q4Q5Q6Q7Q8Q9Q10Q11819216384Q12Q13Table 4.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter ConditionsMin Max Unit V DD supply voltage −0.5+18V I IK input clamping current V I <0.5V or V I >V DD + 0.5 V -±10mA V I input voltage−0.5V DD + 0.5V I OK output clamping current V O <0.5V or V O >V DD +0.5V-±10mA I I/O input/output current -±10mA I DD supply current -50mA T stg storage temperature −65+150°C T amb ambient temperature −40+85°C P tottotal power dissipationT amb −40°C to +85°C DIP16 package [1]-750mW SO16 package[2]-500mW Ppower dissipation per output-100mW9.Recommended operating conditionsTable 5.Recommended operating conditionsSymbol Parameter Conditions Min Typ Max UnitV DD supply voltage3-15VV I input voltage0-V DD VT amb ambient temperature in free air−40-+85°C∆t/∆V input transition rise and fall rate V DD = 5 V-- 3.75ns/VV DD = 10 V--0.5ns/VV DD = 15 V--0.08ns/V 10.Static characteristicsTable 6.Static characteristicsV SS = 0 V; V I = V SS or V DD; unless otherwise specified.Symbol Parameter Conditions V DD T amb =−40°C T amb = 25°C T amb = 85°C UnitMin Max Min Max Min MaxV IH HIGH-level input voltage|I O| < 1µA 5 V 3.5- 3.5- 3.5-V10 V7.0-7.0-7.0-V15 V11.0-11.0-11.0-VV IL LOW-level input voltage|I O| < 1µA 5 V- 1.5- 1.5- 1.5V10 V- 3.0- 3.0- 3.0V15 V- 4.0- 4.0- 4.0VV OH HIGH-level output voltage|I O| < 1µA 5 V 4.95- 4.95- 4.95-V10 V9.95-9.95-9.95-V15 V14.95-14.95-14.95-VV OL LOW-level output voltage|I O| < 1µA 5 V-0.05-0.05-0.05V10 V-0.05-0.05-0.05V15 V-0.05-0.05-0.05VI OH HIGH-level output current V O = 2.5 V 5 V−1.7-−1.4-−1.1-mAV O = 4.6 V 5 V−0.52-−0.44-−0.36-mAV O = 9.5 V10 V−1.3-−1.1-−0.9-mAV O = 13.5 V15 V−3.6-−3.0-−2.4-mA I OL LOW-level output current V O = 0.4 V 5 V0.52-0.44-0.36-mAV O = 0.5 V10 V 1.3- 1.1-0.9-mAV O = 1.5 V15 V 3.6- 3.0- 2.4-mA I I input leakage current15 V-±0.3-±0.3-±1.0µAI DD supply current I O = 0A 5 V-20-20-150µA10 V-40-40-300µA15 V-80-80-600µAC I input capacitance----7.5--pF11.Dynamic characteristics[1]The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C L in pF).Table 7.Dynamic characteristicsV SS = 0 V; T amb = 25°C; for test circuit see Figure 8.Symbol Parameter Conditions V DD Extrapolation formula [1]Min Typ Max Unit t PHLHIGH to LOW propagation delayCP to Q0;see Figure 75 V 78 ns + (0.55 ns/pF) C L -105210ns 10 V 34 ns + (0.23 ns/pF) C L -4590ns 15 V22 ns + (0.16 ns/pF) C L -3065ns Qn to Qn +15 V 53 ns + (0.55 ns/pF) C L -80160ns 10 V 19 ns + (0.23 ns/pF) C L -3060ns 15 V12 ns + (0.16 ns/pF) C L -2040ns MR to Qn;see Figure 75 V 153 ns + (0.55 ns/pF) C L -180360ns 10 V 79 ns + (0.23 ns/pF) C L -90180ns 15 V62 ns + (0.16 ns/pF) C L -70140ns t PLHLOW to HIGH propagation delayCP to Q0;see Figure 75 V 78 ns + (0.55 ns/pF) C L -105210ns 10 V 39 ns + (0.23 ns/pF) C L -5095ns 15 V27 ns + (0.16 ns/pF) C L -3570ns Qn to Qn +15 V 43 ns + (0.55 ns/pF) C L -70140ns 10 V 14 ns + (0.23 ns/pF) C L -2550ns 15 V12 ns + (0.16 ns/pF) C L -2040ns t ttransition timesee Figure 75 V 10 ns + (1.00 ns/pF) C L -60120ns 10 V 9 ns + (0.42 ns/pF) C L -3060ns 15 V6 ns + (0.28 ns/pF) C L-2040ns t Wpulse widthCP = HIGH;minimum width;see Figure 7 5 V 5025-ns 10 V 2515-ns 15 V 2010-ns MR = HIGH;minimum width;see Figure 75 V 13065-ns 10 V 9550-ns 15 V 9045-ns t recrecovery timeMR input;see Figure 75 V 11560-ns 10 V 6535-ns 15 V5525-ns f maxmaximum frequencysee Figure 75 V 510-MHz 10 V 1325-MHz 15 V1835-MHz12.WaveformsTable 8.Dynamic power dissipation P DP D can be calculated from the formulas shown. V SS = 0 V; t r = t f ≤ 20 ns; T amb = 25°C.Symbol Parameter V DD Typical formula for P D (µW)where:P Ddynamic power dissipation5V P D = 600× f i +Σ(f o × C L )× V DD 2f i = input frequency in MHz,f o = output frequency in MHz,C L = output load capacitance in pF ,V DD = supply voltage in V ,Σ(C L × f o ) = sum of the outputs.10V P D = 2800× f i +Σ(f o × C L )× V DD 215VP D = 8200× f i +Σ(f o × C L )× V DD 2Measurement points are given in Table 9.Fig 7.Propagation delays,minimum pulse widths,transition and recovery times and maximum clock frequency MR INPUTV IQ0 or Qn OUTPUTt Wt PHLt rec 1/f maxV MV MV M001aae591t PLH t Wt tt tt PHLCP INPUTV IV OHV OLV SS V SSTable 9.Measurement pointsSupply voltage Input Output V DDV M V M 5 V to 15 V0.5V DD0.5V DDTest data is given in T able 10.Definitions for test circuit:DUT = Device Under Test.C L =load capacitance including jig and probe capacitance.R T =termination resistance should be equal to the output impedance Z o of the pulse generator.Fig 8.Test circuitV DDV IV O001aag182DUTC LR TGTable 10.Test dataSupply voltage Input Load V DD V I t r, t f C L5V to 15V V SS or V DD≤20ns50 pF13.Package outlineFig 9.Package outline SOT38-4 (DIP16)REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDECJEITASOT38-495-01-1403-02-13M Hc(e )1M EALs e a t i n g p l a n eA 1w Mb 1b 2eDA 2Z16198Epin 1 indexb0510 mmscaleNote1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.UNIT Amax.12b 1(1)(1)(1)b 2c D E e M Z H L mm DIMENSIONS (inch dimensions are derived from the original mm dimensions)A min. A max.b max.w M E e 11.731.300.530.380.360.2319.5018.55 6.486.20 3.603.050.2542.547.628.257.8010.08.30.764.20.51 3.2inches0.0680.0510.0210.0150.0140.0091.250.850.0490.0330.770.730.260.240.140.120.010.10.30.320.310.390.330.030.170.020.13DIP16: plastic dual in-line package; 16 leads (300 mil)SOT38-4Fig 10.Package outline SOT109-1 (SO16)Xw MθAA 1A 2b pD H EL pQdetail XE Z ecL v M A(A )3A89116ypin 1 indexUNIT Amax.A 1A 2A 3b p c D (1)E (1)(1)e H E L L p Q Z y w v θREFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IEC JEDEC JEITAmm inches1.750.250.101.451.250.250.490.360.250.1910.09.84.03.8 1.27 6.25.80.70.60.70.380oo 0.250.1DIMENSIONS (inch dimensions are derived from the original mm dimensions)Note1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.1.00.4 SOT109-199-12-2703-02-19076E07MS-0120.0690.0100.0040.0570.0490.010.0190.0140.01000.00750.390.380.160.150.051.050.0410.2440.2280.0280.0200.0280.0120.010.250.010.0040.0390.0160 2.5 5 mmscaleSO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-114.Abbreviations15.Revision historyTable 11.AbbreviationsAcronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MMMachine ModelTable 12.Revision historyDocument ID Release date Data sheet status Change notice Supersedes HEF4020B_420081204Product data sheet-HEF4020B_CNV_3Modifications:•The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.•Legal texts have been adapted to the new company name where appropriate.•Parallel output pins renamed Q0 to Q13 throughout.•T emperature statement added to Section 1 “General description”.•Section 2 “Features” added.•Table 1 “Ordering information” restructured.•Package version SOT38-1 changed to SOT38-4 in Section 4, and Figure 9. Package SOT74 removed from Section 4.•Figure 1 “Functional diagram”,Figure 4 “Logic diagram”,Figure 5 “Pin configuration”,Figure 7 “Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency” and Figure 6 “Timing diagram” changed for pin name changes.•Figure 2 “Logic symbol” and Figure 3 “IEC Logic symbol” added.•Table 2 “Pin description” edited for pin name changes.•Section 7 “Functional description” added.•Section 8 “Limiting values” and Section 10 “Static characteristics” added, taken from the HE4000B Family Specifications data sheet.•t RMR , t WCPH and t WMRH changed to t rec and t W for Table 7 “Dynamic characteristics” and Figure 7 “Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency”.•50% replaced by V M for Figure 7 “Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency”.•Table 9 “Measurement points”,Figure 8 “T est circuit” and Table 10 “T est data” added.HEF4020B_CNV_319950101Product specification -HEF4020B_CNV_2HEF4020B_CNV_219950101Product specification--16.Legal information16.1Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s)described in this document may have changed since this document was published and may differ in case of multiple devices.The latest product status information is available on the Internet at URL .16.2DefinitionsDraft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences of use of such information.Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s)and title.A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.16.3DisclaimersGeneral —Information in this document is believed to be accurate andreliable.However,NXP Semiconductors does not give any representations or warranties,expressed or implied,as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including withoutlimitation specifications and product descriptions, at any time and without notice.This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use —NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure ormalfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage.NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Limiting values —Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134)may cause permanent damage to the device.Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale,as published at /profile/terms , including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant,conveyance or implication of any license under any copyrights,patents or other industrial or intellectual property rights.16.4TrademarksNotice:All referenced brands,product names,service names and trademarks are the property of their respective owners.17.Contact informationFor more information, please visit:For sales office addresses, please send an email to:salesaddresses@Document status [1][2]Product status [3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development.Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.Product [short] data sheetProductionThis document contains the product specification.18.Contents1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Ordering information. . . . . . . . . . . . . . . . . . . . . 15Functional diagram . . . . . . . . . . . . . . . . . . . . . . 26Pinning information. . . . . . . . . . . . . . . . . . . . . . 36.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 37Functional description . . . . . . . . . . . . . . . . . . . 38Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 49Recommended operating conditions. . . . . . . . 510Static characteristics. . . . . . . . . . . . . . . . . . . . . 511Dynamic characteristics . . . . . . . . . . . . . . . . . . 612Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 914Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 1115Revision history. . . . . . . . . . . . . . . . . . . . . . . . 1116Legal information. . . . . . . . . . . . . . . . . . . . . . . 1216.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . 1216.2Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 1216.4T rademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 1217Contact information. . . . . . . . . . . . . . . . . . . . . 1218Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.© NXP B.V.2008.All rights reserved.For more information, please visit: For sales office addresses, please send an email to: salesaddresses@Date of release: 4 December 2008。