ADV7183中文资料
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PR E L I M I N A R Y Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.aVideo Decoder with 9-Bit ADC, 3-LineAdaptive Comb Filter & ScalerFEATURESAnalog Video to Digital YUV Video Decoder NTSC-(M/N), PAL -(B/D/G/H/I/M/N)Integrates Two 9-Bit Accurate ADCs Clocked from a Single 27 MHz Crystal Dual Video Clocking SchemesLine Locked Clock Compatible (LLC)Fixed Frequency Oversamping 10-Bit Operation Adaptive-Digital-L ine-L ength-Tracking (ADL L T ™)Real Time Clock & Status Information OutputIntegrated AGC (Automatic Gain Control) & Clamping Simplified Digital Interface On-Board Digital FIFOOptimised Programmable Video Source Modes Broadcast TV VCR/CamcorderSecurity/SurveillanceMultiple, Programmable Analog Input Formats: CVBS (Composite Video) SVHS (Y/C4 Analog Input Video ChannelsReal Time Horizontal and Vertical ScalingAdaptive 3-Line Luma and Chroma Comb Filter Automatic NTSC/PAL Identification VMI & VIP compliant video pixel portDigital Output Formats (16-Bit Wide Bus): YCrCb (4:2:2 or 4:1:1) CCIR601/CCIR656 8-Bit 0.5V to 2.0V pk-pk i/p range Differential Gain < 1%Differential Phase < 1oProgrammable Video ControlsPk-White/Hue/Brightness/Saturation/Contrast CCIR/Square Pixel OperationIntegrated On-Chip Video Timing Generator Synchronous or Asynchronous Output Timing Line Locked Clock OutputClose Captioning Passthrough Operation Vertical Blanking Interval Support Power Down Mode2-Wire Serial MPU Interface (I 2C Compatible)+5V/+3V CMOS Supply Operation 80-Pin LQFP PackageAPPLICATIONSVideo ConferencingHybrid Analog/Digital Set Top Boxes PC Video/Multimedia CamcordersSecurity Systems/SurveillanceGENERAL DESCRIPTIONThe ADV7183 is an integrated video decoder that automati-cally recognises and converts a standard analog basebandtelevision signal compatible with world wide standards NTSC or PAL into 4:2:2 or 4:1:1 component video data compatible with 16-bit/8-Bit CCIR601/CCIR656 8-Bit standards.The advanced and highly flexible digital output interface enables perfomance video decoding and conversion in both frame-buffer based and line locked clock based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics including tape based sources, broadcast sources, secruity/surveillance cameras and professional systems.Fully integrated line stores enable 3-line comb filtering in both luminance and chrominance data paths, plus real time horizon-tal and vertical scaling of captured video down to icon size.The 9-bit accurate A/D conversion provides professional quality SNR performance. This allows true 8-bit resolution in the 8-bit output mode.The 4 analog inputs channel accept standard composite or S-Video video signals in an extensive number of combinations.AGC and Clamp Restore circuitry allow an input video signal peak to peak range of 0.5V up to 2V. Alternatively these can be bypassed for manual settings.The fixed 27 MHz clocking of the ADCs and datapath for all modes allows very precise and accurate sampling and digital filtering. The Line Locked Clock output allows the output data rate, timing signals and output clock signals to be synchro-nous, asynchronous or line locked even with +/-5% line length variation. The output control signals allow glueless interface connection in almost any application.The ADV7183 modes are set up over a two wire serial bidirec-tional port (I 2C compatible).The ADV7183 is fabricated in a +5V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation.The ADV7183 is packaged in a small 80 pin LQFP package.June 98 Rev .00* ADV is a Registered Trademark of Analog Devices, Inc.One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.Tel: 617/329-4700World Wide Web Site: Fax: 617/326-8703© Analog Devices, Inc., 1997Preliminary InformationADV7183元器件交易网2June 98 REV. 00ADV7183Preliminary InformationA R Y F U N C T I O N A LB L OC KD I A G R A MC L O C K C L O C K SD A T A S C L O C K A I N 1A I N 2A I N 3A I N 4R E S E T F I E L DH S Y N C V S Y N C P 15-P 0P I X E L O /P P O R TL KH R E F V R E F H L O C KC K /C L K I NA L S BR E F O U TP W R D N I S O元器件交易网3June 98 REV. 00Preliminary InformationADV7183PR E L I M I N A R Y PIN DESCRIPTIONMnemonic Input/Output FunctionP15-P0O8-Bit Multiplexed YCrCb Pixel Port (P7-P0), 16-Bit YCrCb Pixel Port (P15-P0), 10-Bit Multiplexed Extended YCbCr Pixel Port (P9-P0) and 20-Bit YCbCr Pixel Port (P19-P0), P0 represents the LSB.XTAL I Input terminal for 27MHz crystal oscillator or connection for external oscillator with CMOS compatible square wave clock signalXTAL10Second terminal for crystal oscillator; not connected if external clock source is used DVSS1-4G Ground for Digital supply DVDD1-4P Digital Supply Voltage (5.0V)AVSS G Ground for Analog Supply AVDD PAnalog Supply Voltage (5.0V)AVDD1-3PAnalog Input Channel supply Voltage (5.0)AVSS1-4GAnalog Input Channels ground PVSS G PLL Supply GroundPVDD PPLL Supply Voltage (5.0)AIN1-4IVideo Analog Input ChannelsSCLOCK IMPU Port Serial Interface Clock Input.SDATA I/O MPU Port Serial Data Input/Output.ALSB ITTL Address Input. This signal set up the LSB of the MPU address.RD I Read signal, read data from FIFODV OData Valid signal, indicates data on pixel port is a valid sampleOE IOutput Enable, enables pixel port outputs or else tri-states themHREFO Horizontal reference output signal (enable via I2C); this signal is used to indicate dataon the YUV output. The positive slope indicates the begining of a new active line,HREF is always 720 Y samples longVREF O Vertical reference output signal or inverse composite blanking signal depending on configurationLLCREF O Clock reference ouput; this is a clock qualifier distributed by the internal CGC for a data rate of LLC2LLC1/PCLK O Dual function pin, Line locked clock system output clock (27MHz) or a FIFO output clcok ranging from 20-35MHZLLC2O Line locked clock system output clock/2 (13.5MHz)HLOCK O Horizontal locked: output signal indicating horizontal locking status RESETI/OSystem Reset, can be configured as an Input or Output signal.4June 98 REV. 00ADV7183Preliminary InformationPM I N A R Y PIN DESCRIPTIONMnemonic Input/Output FunctionPWRDN I Power down enable; place part in a power down status REFOUT O Internal Reference Output CML O Common Mode LevelAEFO Almost Empty Flag; FIFO control signalHFF/QCLK/GLI/OTripple function pin, Half Full Flag; FIFO control signal or QCLK; a qualified pixel output clcok when using FIFO modes or Real Time Control Output; contains information for locking subcarrierfrequency and phase locking.AFF O Almost Full Flag; FIFO control signal CLKIN IFIFO clock input pinFIELD OODD/EVEN field output signal HSYNC O Horizontal sync output signal VSYNC O Vertical sync output signalISO I Fast switch over I/P. allows the fast switch of video I/P channels CAPY1-2IADC Capacitor network CAPC1-2IADC Capacitor networkADV7183 PIN FUNCTIONALITYSS SS 4SSC 2C 1SS M LUT D D Y1SS SS 3SS 2SS 1L L VS YN CHSYN C DVS S 3DVD D3P 11P 10P9P8DVS S 2DVD D2AF FHFF/QCLK /G LAE FDVS S 1DVD D1CLKINn.c.n.c.P7P65June 98 REV. 00Preliminary Information ADV7183PR E L I O U T LIN E D IM E N S IO N SD im e nsions s ho w n in inche s and (m m ).80-Le ad LQ FP(ST -80)0.063 (1.60)0.057 (1.45)0.053 (1.35)0.014 (0.35)0.010 (0.25)0.029 (0.73)0.022 (0.57)。
