DS96F175C中文资料

°10 transceiver differential pairs° 2 transceiver differential clocks° 4 differential clocks°159 ground and 15 power connectionsFMC HPC0 Connector J22[Figure1-2, callout 33]The HPC connector at J22 implements a subset of the full FMC HPC connectivity:•58 differential user-defined pairs (34 LA pairs: LA[00:33]; 24 HA pairs: HA[00:23])•10 GTH transceiver differential pairs•Two GTH transceiver clocks•Two differential clocks•159 ground and 15 power connectionsThe VCU108 board FMC VADJ voltage VADJ_1V8_FPGA for the J22 and J2 FMC connectors is determined by the MAX15301 U30 voltage regulator described in the VCU108 Board Power System section. The HPC0 J22 connections to FPGA U1 are shown in Table1-34.Table 1-34:J22 VITA 57.1 FMC HPC0 ConnectionsJ22FMC HPC0 Pin Schematic Net Name I/O Standard FPGA(U1) PinJ22 FMCHPC0PinSchematic Net Name I/O Standard FPGA (U1)PinA/B Connections to FPGA U1A2 FMC_HPC0_DP1_M2C_P H2B1NC NA NA A3 FMC_HPC0_DP1_M2C_N H1B4 FMC_HPC0_DP9_M2C_P W4 A6 FMC_HPC0_DP2_M2C_P F2B5FMC_HPC0_DP9_M2C_N W3 A7 FMC_HPC0_DP2_M2C_N F1B8 FMC_HPC0_DP8_M2C_P Y2 A10 FMC_HPC0_DP3_M2C_P D2B9FMC_HPC0_DP8_M2C_N Y1 A11 FMC_HPC0_DP3_M2C_N D1B12FMC_HPC0_DP7_M2C_P M2 A14 FMC_HPC0_DP4_M2C_P T2B13FMC_HPC0_DP7_M2C_N M1 A15 FMC_HPC0_DP4_M2C_N T1B16FMC_HPC0_DP6_M2C_P P2 A18 FMC_HPC0_DP5_M2C_P R4B17FMC_HPC0_DP6_M2C_N P1 A19 FMC_HPC0_DP5_M2C_N R3B20FMC_HPC0_GBTCLK1_M2C_P(1)N9 A22 FMC_HPC0_DP1_C2M_P F7B21FMC_HPC0_GBTCLK1_M2C_N(1)N8 A23 FMC_HPC0_DP1_C2M_N F6B24FMC_HPC0_DP9_C2M_P T7 A26 FMC_HPC0_DP2_C2M_P E5B25FMC_HPC0_DP9_C2M_N T6 A27 FMC_HPC0_DP2_C2M_N E4B28FMC_HPC0_DP8_C2M_P V7 A30 FMC_HPC0_DP3_C2M_P C5B29FMC_HPC0_DP8_C2M_N V6E/F Connections to FPGA U1E2 FMC_HPC0_HA01_CC_P LVDS T14F1 FMC_HPC0_PG_M2C (7)LVCMOS18U44.18E3 FMC_HPC0_HA01_CC_N LVDS R13F4 FMC_HPC0_HA00_CC_P LVDS N14E6FMC_HPC0_HA05_P LVDS AA12F5FMC_HPC0_HA00_CC_N LVDS N13E7FMC_HPC0_HA05_N LVDS Y12F7FMC_HPC0_HA04_P LVDS AA13E9FMC_HPC0_HA09_P LVDS AA14F8FMC_HPC0_HA04_N LVDS Y13E10FMC_HPC0_HA09_N LVDS Y14F10FMC_HPC0_HA08_P LVDS W12E12FMC_HPC0_HA13_P LVDS W14F11FMC_HPC0_HA08_N LVDS V12E13FMC_HPC0_HA13_N LVDS V14F13FMC_HPC0_HA12_P LVDS V15E15FMC_HPC0_HA16_P LVDS V16F14FMC_HPC0_HA12_N LVDS U15E16FMC_HPC0_HA16_NLVDSU16F16FMC_HPC0_HA15_PLVDSV13Table 1-34:J22 VITA 57.1 FMC HPC0 Connections (Cont’d)J22 FMC HPC0 PinSchematic Net NameI/O StandardFPGA (U1) PinJ22 FMC HPC0 PinSchematic Net NameI/O StandardFPGA (U1)PinG13FMC_HPC0_LA08_NLVDS BF9H11FMC_HPC0_LA04_N LVDS BE7G15FMC_HPC0_LA12_P LVDS BE15H13FMC_HPC0_LA07_P LVDS BD12G16FMC_HPC0_LA12_N LVDS BF15H14FMC_HPC0_LA07_N LVDS BE12G18FMC_HPC0_LA16_P LVDS AY8H16FMC_HPC0_LA11_P LVDS BC11G19FMC_HPC0_LA16_N LVDS AY7H17FMC_HPC0_LA11_N LVDS BD11G21FMC_HPC0_LA20_P LVDS AY15H19FMC_HPC0_LA15_P LVDS AV9G22FMC_HPC0_LA20_N LVDS AY14H20FMC_HPC0_LA15_N LVDS AV8G24FMC_HPC0_LA22_P LVDS AN15H22FMC_HPC0_LA19_P LVDS AV15G25FMC_HPC0_LA22_N LVDS AP15H23FMC_HPC0_LA19_N LVDS AW15G27FMC_HPC0_LA25_P LVDS AM13H25FMC_HPC0_LA21_P LVDS AN16G28FMC_HPC0_LA25_N LVDS AM12H26FMC_HPC0_LA21_N LVDS AP16G30FMC_HPC0_LA29_P LVDS AK14H28FMC_HPC0_LA24_P LVDS AK15G31FMC_HPC0_LA29_N LVDS AK13H29FMC_HPC0_LA24_N LVDS AL15G33FMC_HPC0_LA31_P LVDS AP12H31FMC_HPC0_LA28_P LVDS AJ13G34FMC_HPC0_LA31_NLVDSAR12H32FMC_HPC0_LA28_NLVDSAJ12Table 1-34:J22 VITA 57.1 FMC HPC0 Connections (Cont’d)J22 FMC HPC0 Pin Schematic Net Name I/O StandardFPGA (U1) Pin J22 FMC HPC0 Pin Schematic Net Name I/O StandardFPGA (U1)PinThe VCU108 evaluation board uses power regulators and PMBus compliant PoL controllers from Maxim Integrated Circuits to supply the core and auxiliary voltages listed inTable1-36.Table 1-36:Onboard Power System DevicesDevice Type ReferenceDesignator PMBusAddress DescriptionPower Rail NetNamePower RailVoltageMAX20751EKX U1640x70Maxim multiphase masterwith smart slavesVT1697SBFQX 60AVCCINT_FPGA0.95VMAX15301U90x11Maxim InTune digital POLcontroller 10A VCC1V8_FPGA 1.80VMAX15301U300x12Maxim InTune digital POLcontroller 10A VADJ_1V8_FPGA 1.80VMAX15301U40x14Maxim InTune digital POLcontroller 10A VCC1V2_FPGA 1.20VMAX20751EKX U1660x72Maxim multiphase masterwith smart slaveVT1697SBFQX 17AMGTAVCC_FPGA 1.00VMAX20751EKX U1650x73Maxim multiphase masterwith smart slaveVT1697SBFQX 17AMGTAVTT_FPGA 1.20VMAX8869EUE U167NA Maxim fixed LDO 1A MGTVCCAUX 1.80VMAX15301U1500x1A Maxim InTune digital POLcontroller 10A UTIL_1V35 1.35VMAX15301U1560x1B Maxim InTune digital POLcontroller 20A UTIL_3V3 3.30VMAX17502U82NA Maxim synchronous buckswitcher 1A SYS_5V0 5.00VMAX15053U124NA Maxim adjustablesynchronous buck switcher2ASYS_1V0 1.00VMAX15027U125NA Maxim adjustable LDO 1A SYS_1V8 1.80VMAX15053U151NA Maxim adjustablesynchronous buck switcher2ASYS_2V5 2.50VTPS51200U24NA TI source-sink V TT regulator3A DDR4_C1_VTT0.60VTPS51200U134NA TI source-sink V TT regulator3A DDR4_C2_VTT0.60VTPS51200U143NA TI source-sink V TT regulator3A RLD3_C1_VTERM0.60V。