IC-1000pad

iPasolink 1000 配置指导书1 iPasolink 1000 产品介绍1.1iPasolink 1000 产品介绍对于移动和固定的宽带业务的需求，引领了当今技术、网络、商业各方面的变革。

统一和标准化的IP网络和端到端的网络管理提供了更多额外的业务，例如基于包交换网络的传统语音业务和汇聚层链路带宽的共享与增值。

但是，合理的骨干链路演进的决策取决于每个运营商的不同商业动机和目的，例如对OPEX，CAPEX，灵活性，控制，规模的需求。

iPasolink 1000产品提供高密度节点传输的应用，例如，12条链路的交叉连接，多链路环节点的汇聚与分配和大容量D/I中继站的应用等等。

该产品提供基于全TDM和全Ethernet业务的各种灵活组合方式和基于链路的环保护。

iPasolink 1000的每条链路传输容量高达460Mbps，在频段6/7/8/10/11/13/15/18/23/26/28/32/38和42GHz提供自适应的调制解调方式。

同时，iPasolink 1000可以提供高速率接口，例如10GbE接口和汇聚移动和固定宽带业务的CWDM接口。

iPasolink 1000拥有14个前面板插入式的多功能卡插槽，这些插槽适合多种接口卡模块，这些模块可以满足不同D/I和网络的需求。

多功能iPasolink 1000产品由此而来。

iPasolink 1000的基本配置可以提供12个1+0系统，6个1+1双路系统或热备份系统，空间分集系统，基于NEC最先进的交叉极化干扰抵消技术的XPIC系统，它通过两个极化方式在同一个昂贵的和有限的频率资源内进行传输，容量可以高达920Mbps。

上述的所有这些配置的实现无需对包头或者包数据进行限制或压缩。

1.2 外形尺寸及重量ODU: 237(W)x237(H)x101(D); 3.5 kg （6GHz~11GHz ） ODU: 239(W)x247(H)x68(D); 3 kg （13GHz~42GHz ） IDU 1+0/1+1: 482(W)x132(H)x240(D); 15 kgiPasolink 1000 IDUiPasolink 1000 ODU 6-11GHziPasolink 1000 ODU 13 – 42GHz1.3工作温度IDU：-10℃～+55℃ODU：-40℃～+55℃1.4工作电压及功耗工作电压：-48VDC功耗：ODU (6~11GHz) : 30WODU (13~24GHz) : 23WIDU Main board : 45WIDU Fan unit : 12WIDU Modem(ODU interface) : 10WIDU 16xE1 interface : 8WIDU STM-1 interface : 8WIDU 4xGbE(2xSFP+2xRJ-45) : 8WIDU Option Multi service engineer for PWE : 10W IDU Option AUX : 3W2. iPasolink 1000 IDU 主要模块介绍2.1 主要功能模块介绍2.1.1 iPasolink 1000 IDU 通用机框iPasolink 1000 IDU 机框为3U 高度标准机框。

CMP Pad ☐ Grooving •Perforation •XY groove •Circulation groove •Combination groove •Spiral groove IC1000TM SeriesNITTA HAAS INCORPORATED☐Physical PropertyOur IC1000 CMP pad can achieve good performance balance of stability, reliability and polishing performance. IC1000 has been qualified for a lot of CMP processes that need the highest requirement in industry and still maintain high market share.Because our pads are designed with unique and special materials, processing andapplication/evaluation skills, they can deliver an excellent performance to our customers. IC1000 is the de-facto standard as CMP pad. This product has an unique structure which has very small and uniform pores based on a special polyurethane material. It canachieve better slurry retention ability and high polishing removal rate with appropriate pad surface groove that helps slurry to spread quickly to under the wafer.Type A2 Spec. Range Thickness (mm)1.17 － 1.37 Compressibility (%)0.5 － 4.0 Hardness (Shore-D)52 － 62 Specific Gravity (g/cm3) 0.74 － 0.85☐ Stacked Pad •Stacked pad with SUBA TM series can achieve good removal rate uniformity.IC1000/SUBA400 Cross Sec.※ IC1000™ and SUBA TM are the trademark of Nitta Haas Inc. or The Dow Chemical Company ("Dow") or an affiliated company of Dow. ※ The values such as a physical properties indicated, show the standard value. The product specifications are not guaranteed. The specifications are subject to change for improvement without notice.。

Technological Breakthrough in Pad Life Improvement and its Impact on CMP CoCSidney Huey, Steven T. Mear, Yuchun Wang, Raymond R. JinApplied Materials, 3111 Coronado Drive, M/S 1510, Santa Clara, CA 95054(408)986-3277 (phone), (408)235-6803 (fax), raymond_jin@ (e-mail)John Ceresi, Peter Freeman, Doug Johnson, Tuyen Vo, Stan EppertRodel, 451 Bellevue Road, Newark, DE 19713AbstractMany IC fabs have expressed a great deal of interest in CMP pad life improvement with the expectation that improved pad performance will reduce process variability and improve CMP cost-of-consumables (CoC). Critical parameters that impact grooved-pad life and that can reduce pad life variability have been identified through designed experiments performed on a multiple head/platen CMP tool. The most important parameters effecting pad life are groove quality and groove size. New technologies have been developed to control these critical parameters in conjunction with extensive process optimization. Lathing technology (in tools and processes) plays a critical role in achieving high groove quality and desirable groove size. In many extended wafer runs and several accelerated pad wear runs, pad life was more than doubled by optimizing these critical parameters on polyurethane-based grooved-pads. Low defect counts of <20 at 0.2µm, low within wafer non-uniformity (WIWNU) of 4% with a 5 mm edge exclusion, and a stable removal rate of >2750 Ang./min. were achieved for thermal oxide CMP in the extended runs. The new pads double pad life when used with optimized processes, and achieve planarity comparable to conventional pads. Significant pad life improvement was attributed mainly to the implementation of larger and more consistent grooving, and optimized pad conditioning and polishing processes for the CMP tool.In general, the pad cost contributes approximately one third of the total CMP CoC. In this case study, average CMP pad life was found to be 250 wafers/pad with a variance of 100 to 400 wafers/pad. Pad CoC significantly increases for pad lives < 350 wafers/pad. The pad CoC at 350 wafers/pad is half of that at 225 wafers/pad. Based on several extended runs, new pads coupled with an optimized polish process demonstrated the feasibility of more than 500 wafers/pad. At this longer pad life, the potential to reduce CoC is even greater.IntroductionIncreasing CMP polishing pad life reduces costs of consumables (CoC) by allowing users to replace pads less frequently. Replacing pads less frequently not only reduces the number of pads required for a given wafer output, but also reduces the total amount of time required to re-qualify a tool after a pad change. This improvement in tool availability is the real benefit obtained from longer pad life. This paper summarizes the efforts made to develop a new longer-life pad, the Rodel® IC1010-DV, and presents performance data demonstrated in both laboratory and field settings.The Rodel® IC1000 is an industry standard pad. However, pad life is relatively short (250 wafers/pad on average on the Applied Materials Mirra® CMP polisher) and can exhibit pad life variability of between 100 to 400 wafers/pad. Figure 1 shows the results from a case study on pad life.This paper will first present results of pad experiments conducted to determine the parameters that effect and control pad life. Data from these experiments were used in the development of the IC1010-DV pad. The paper next presents process data for several extended runs that demonstrate excellent process performance and stability over the life of the pad. The IC1010-DV demonstrates a 2X increase in pad life when compared to IC1000, the reference pad for IC1010-DV development. Finally, a cost analysis is presented comparing CoC for the IC1010-DV and IC1000 pads.This paper was published in the proceedings of 1999 ASMC co-sponsored by IEEE/SEMI, pp.54-58.Figure 1. IC1000 pad life averages about 250 wafers/pad but exhibits a high level of variability.In terms of physical make-up, the IC1010-DV is similar to the IC1000 in many ways. For example, both pads incorporate the same hard polyurethane top pad adhered to a soft felt bottom pad. However, there are several significant differences, such as top pad thickness, groove dimensions, and different groove lathing techniques as shown in Table 1. The IC1010-DV pad features (1) improved grooving quality resulting from an improved grooving process, (2) tighter top pad specific gravity control/spec, (3) increased groove depth and (4) a thicker top pad.Table 1. Comparison of IC1010-DV and IC1000 pads.Pad Parameter IC1010-DV*IC1000Top Pad80 mil A2 StylePolyurethane 50 mil A2 Style PolyurethaneBottom Pad50 mil SUBA IV50 mil SUBA IV Nominal Groove Dimensions – depth (mils)Ratio of width/depth/pitch: same for both pads3015Top Pad Specific Gravity Specification (g/cc)0.78 - 0.840.74 - 0.85*The IC1010-DV pad has the following characteristics:Unique concentric grooving configuration with 0.030” depthPrestackedPSA V bonding IC1010-DV top pad to Suba IV sub padPSA II on Suba IV for adhesion to platenImproved cake uniformityImproved groove depth uniformityPad Life Factors and the Design of IC1010-DVTo determine the factors that affect and control pad life, many different pad experiments were conducted and pad properties measured. Of these efforts, two experiments produced surprising results: the grooving bit age experiment, which studied effects of groove quality, and grooving gradient experiments, which studied the effect of groove dimensions. The details and results of these two experiments are summarized below. These experimental results were critical in discovering the dimensions and developing the improved grooving techniques used to manufacture the new IC1010-DV pad.Impact of Grooving QualityAn experiment was designed using the IC1000 and executed to determine the effects of poor groove quality on pad performance and pad life. By using manufacturing bits of different wear/age, standard “K” grooves were cut into pads adjacent to each other within a specific pad lot, to minimize pad material variation. The grooves were visually examined and found to vary with the age of the cutting bit. The newer bit produced clean high-quality grooves of proper dimensions, but the older bit produced rough-edged grooves with somenoticeable residual debris within the grooves. Both pads were tested under the same controlled conditions. Figure 2 shows rate and WIWNU for extended runs conducted on three different pads. Figure 2 shows that WIWNU drifted out of control much earlier on the pads manufactured with the old bit compared to the high-quality new bit grooved pad and a standard reference pad. Results also show WIWNU stayed in control until the grooves on the pad started to disappear. This result shows a pad should provide stable process performance until the grooves begin to disappear.Figure 2. Rate and WIWNU as a function of wafers polished using IC1000 pads from three different lots. Impact of Grooving DimensionsAn experiment was designed and executed using the IC1000 to determine the effect of groove dimension and variation on pad performance and pad life. A pad lot was grooved with varying depth dimensions as a function of radius. Figure 3 depicts the two types of pads tested. Pad 5-15 is an exaggerated representation of the typical groove pattern profile on standard IC1000 pads. Figure 4 presents rate and WIWNU data associated with each of these pads over 1200 wafers. Results show that process is not affected by groove depth variability if there is sufficient groove depth over the entire pad. However, the results also show that when the grooves wear away on any part of the pad, process performance is affected and WIWNU drifts out of control.Figure 4. Rate and WIWNU as a function of IC1000 pad wearDesign of IC1010-DVResults of these two experiments led to the following guidelines:•pad life is defined by minimum groove depth on the pad and pad wear rate,•groove quality affects process performance and stability, and can cause premature end of pad life,•groove depth variation and quality does not affect initial process qualification.Using these guidelines, the IC1010-DV was designed with the goal of increasing pad life by 2X. While typical IC1000/K-groove depth is 15mils and top pad thickness is 50mils, IC1010-DV groove depth is30mils and top pad thickness is 80mils. The IC1010-DV pad groove depth of 30mils was selected to offer twice the groove depth/life of K-groove. Pad thickness was increased from 50 to 80mils to ensure that pad compressibility at the end of IC1010-DV pad life is less than or equal to the pad compressibility at the start of IC1000 pad life (80mil thick pad minus 30mil grooves leaves 50mil pad thickness).Extended Run Process Results for IC1010-DVThe fourteen extended runs completed using IC1010-DV pads show equivalent or better process performance than that generated by IC1000 pads. IC1010-DV pads have been tested successfully at several IC fabs as a replacement for the IC1000 pad. The 2X increase in pad life was demonstrated consistently. Table 2 summarizes process performance results. Figures 6-7 show excellent rate, WIWNU, and defect performance and stability over >500 wafers/pad. The average pad life for the IC1000 is 250 wafers/pad when under conditions similar to those used to evaluate the IC1010-DV. Figure 6 also shows planarity performance for the IC1010-DV pad was comparable to performance obtained using the IC1000 pad. Table 2. Summary of process performance achieved on the IC1010-DV Pad as compared to the IC1000 padResult Run #1Run#2Compared to IC1000Wafers Polished (per 2 pad set)11001300~ 2X pad lifeAverage RR (Å/min)35373320ComparableAverage WIWNU (5mm EE) 2.7 2.5Comparable with process change Average WTWNU (5mm EE) 2.2 4.0Comparable with process change Average HTHNU (5mm EE) 1.6 1.3Comparable with process change Others Planarity equal or better than IC1000.Defects better than IC1000 at the end ofpad life.Pad life variability improved.Pad wear rate depends strongly onconditioning disk type.Significant pad life improvement coupled with comparable or improved polishing performance was attributed mainly to the IC1010-DV’s larger and more consistent grooves, uniform pad wear, uniformtransportation of slurries and polishing bi-products to and from polishing zones, and uniform temperature distribution on the wafers during polishing.(a)(b)Figure 6. IC1010-DV pad extended run removal rate, WIWNU (a) and planarity data (b)Figure 7. IC1010-DV pad extended run 6420-adders defect dataCoC, Relative Tool Availability, and Throughput –IC1010-DV vs. IC1000Longer pad life reduces the costs associated with a significant CMP consumable item – the pad. Figure 8 shows the results of a pad CoC analysis based on Mirra CMP polisher experience and calculated using an Applied Materials cost model based on the SEMATECH cost of ownership model. CoC is shown to exhibit a strong sensitivity to pad life at lower pad life times (<350 wafers/pad). The impact of pad life on CoC becomes far less significant at longer pad life times. Pad CoC significantly increases at pad lives < 350 wafers/pad. Pad CoC at 350 wafers/pad is half of that at 225 wafers/pad.$0.00$1.00$2.00$3.001002003004005006007008009001000Pad Life $/W a f e r f r o m P a d Figure 8. Pad CoC as a function of pad life.The net benefit of longer pad life is a reduction in the time spent on CMP tool re-qualification after pad changes. Fewer pad changes could also lead to better process stability by reducing the contribution of pad-to-pad variation. In a volume production fab, pad life significantly affects CMP tool availability as shown in Figure 9. And pad life has a much greater impact on tool availability and wafer output as throughput increases.0100020003000400050006000700080001020304050Throughput (wph)W a f e r S t a r t s p e r W e e k Pad Life =250Pad Life =500Pad Life =100075808590951001020304050Throughput (wph) R e l a t i v e A v a i l a b i l i t y (%)Pad Life =250Pad Life =500Pad Life =1000Figure 9. Pad life effect on tool availability and output as a function of throughput.ConclusionA longer-life polishing pad – the IC1010-DV has been successfully developed. On the Mirra CMP polisher, the IC1010-DV pad exhibits twice the pad life of the standard IC1000 pad, and equivalent or improved polishing performance. Low defect counts at the end of pad life, improved or equivalentplanarity, and equivalent removal rate and non-uniformity were achieved by using IC1010-DV pads. These results have been achieved on Mirra CMP systems installed in both lab and field environments. Significant pad life improvement was attributed mainly to the implementation of larger and more consistent grooving during pad manufacture, and optimized pad conditioning and polishing processes for the Mirra CMP system.Longer and more consistent pad life reduces pad consumables cost in CMP operations and improves CMP tool availability and wafer output because less time is spent on pad changing and CMP tool requalification.。

UG411: EFP0111 Evaluation Kit User's GuideThe EFP0111 Evaluation Kit is an excellent way to evaluate andcharacterise the EFP01 Energy Friendly Power Management IC (PMIC) in the Boost Bootstrap configuration.The EFP01 is an extremely flexible, highly efficient, multi-output power management IC with integrated Coulomb counter for lossless charge measurements. The kit contains an EFP0111 Evaluation Board (BRD8100B), which features an EFP0111 in the Boost Bootstrap configuration. The input and output power rails of the EFP01 are exposed on terminal blocks and test points making it easy to evaluate and characterize the EFP01 with external hardware. The board can be plugged into a computer using the USB Mi-cro-B connector for conveniently controlling the EFP01's register settings and reading back data. The EFP0111 Evaluation Board is supported in Simplicity Studio and the EFP Configuration Tool.TARGET DEVICE•EFP0111 multi-output PMIC in Boost Bootstrap configurationKIT FEATURES•Wire to board terminal blocks for EFP0111 input and output power connections•Test points for easy probing•Host MCU with two push buttons and three LEDs•Convenient control of the EFP from a computerSOFTWARE SUPPORT•Simplicity Studio•EFP Configuration ToolTable of Contents1. Introduction (3)1.1 Kit Contents (3)1.2 Getting Started (3)2. Hardware (4)2.1 Block Diagram And Hardware Layout (4)2.2 EFP01 (5)2.2.1 Operating Conditions (5)2.2.2 Overview and Typical Connection (6)2.2.3 Digital Interface (7)2.2.4 On-Board LDO (7)2.2.5 Design Notes (7)2.3 Host MCU (8)2.3.1 EFP01 Interface (8)2.3.2 Push Buttons and LEDs (8)2.3.3 Breakout Pads (8)2.4 On-board Debugger (9)2.4.1 Virtual COM Port (9)3. Design Files (10)4. Kit Revision History (11)4.1 SLEVK1000B Revision History (11)5. Document Revision History (12)1. IntroductionThe EFP0111 Evaluation Kit (OPN: SLEVK1000B) is an excellent starting point to evaluate and characterize the EFP01 Energy Friendly Power Management IC (PMIC) in the Boost Bootstrap configuration. The EFP01 is an extremely flexible, highly efficient, multi-output power management IC with integrated Coulomb counter for lossless charge measurements.The kit contains an EFP0111 Evaluation Board (BRD8100B), which features an EFP0111 in the Boost Bootstrap configuration. The in-put and output power rails of the EFP01 are exposed on terminal blocks and test points instead of powering the host MCU, making it easy to evaluate and characterise the EFP01 with external hardware. The board can be plugged into a computer using the USB Micro-B connector for conveniently controlling the EFP01's register settings and reading back data. Writing and reading registers is handled through the host MCU, which is embedded on the board and connected to the digital interface of the EFP01. An on-board SEGGER J-Link debugger provides the host MCU with a virtual COM port and debugging capabilities on the USB connector.The EFP0111 Evaluation Board is supported in Simplicity Studio and the EFP Configuration Tool.1.1 Kit ContentsThe following items are included in the box:•1x EFP0111 Evaluation Board (BRD8100B)•1x USB 2.0 AM to Micro BM cable1.2 Getting StartedDetailed instructions for how to get started with your new EFP0111 Evaluation Kit can be found on the Silicon Labs web pages:/start-efp2. HardwareThis section describes the hardware on the EFP0111 Evaluation Board. The main part of the board is the EFP01 with terminal blocks and test points, while the host MCU with peripherals and the on-board debugger is there to provide an easy interface to the registers of the EFP01.2.1 Block Diagram And Hardware LayoutThe block diagram and hardware layout of the EFP0111 Evaluation Kit is illustrated in the two figures below.Figure 2.1. Kit Block DiagramEFP0111 PMICInput power:Output power:Test points Test pointsHost MCU sectionButtonsLEDs padsUSB Micro-B connector:- Virtual COM port - Debug accessOn-board USB debuggerEFP0111 section55 mmVOA VOB VOC VOA_SW VIN GNDFigure 2.2. EFP0111 Evaluation Kit Hardware Layout2.2 EFP01The EFP0111 on the evaluation board is configured in the Boost Bootstrap configuration. It takes an input voltage between 1.5 - 5.5 V (after start-up) and generates four outputs. More information regarding the operating conditions of the device is given in section 2.2.1 Operating Conditions . A simplified block diagram of the EFP0111 power supply connection is shown in the figure below.MCUFigure 2.3. Boost Bootstrap Configuration2.2.1 Operating ConditionsThe default operating conditions of the EFP0111 on the board are as specified in the table below. The output voltages can be set to other values by configuring the appropriate registers. Take precautions to not exceed the maximum supported input voltage as this may cause damage to the device.Table 2.1. Default Operating Conditions1Unless otherwise stated, 1.5 - 5.5 V is used throughout this document as the input voltage range of the device.2On the EFP0111 Evaluation Board, VIO is generated by an on-board LDO set to 3.3 V. The EFP01 itself supports a wider VIO voltage range.2.2.2 Overview and Typical ConnectionThe input and output power rails of the EFP01 are exposed on terminal blocks instead of being used on the board itself. The terminal blocks are of the M2 screw thread type and are suited for wires with a wire gauge of 16-30 AWG. A power supply between 1.5 - 5.5 V should be applied on the "PWR IN" terminal block, while one or several loads can be connected to the "PWR OUT" terminal block.Power to the VIO terminal must also be applied in addition to power on VIN for proper operation of the EFP01. This is normally done by connecting the EFP0111 Evaluation Board to a power source using the USB Micro-B connector. The 5 volt power net from the USB bus is regulated down to 3.3 V, which is used to power VIO on the EFP01, the host MCU and the on-board debugger. Failure to power VIO may cause improper operation of the EFP01, and the EFP01 may draw several hundred μA of extra current consumption from the VIN terminal. For advanced use-cases it is possible to disconnect VIO and the digital interface of the EFP01 from the rest of the board as described in section 2.2.3 Digital Interface .The power rails VIN, VOA, VOB, VOC and VOA_SW are routed to test points on the board, which is marked in the silk print on the board with reference to Figure 2.3 Boost Bootstrap Configuration on page 5 and the schematics. In addition to a surface mount test point suitable for miniature probes, clips and hooks, a footprint that fits a standard 2x1, 2.54 mm pitch pin header is also available for each rail. Pad 1 of this footprint is connected to the power rail, while pad 2 is connected to ground. The test points are routed directly to the input/output capacitors of the power rails, and they are primarily intended for low current sensing. The switch nodes of the two DC/DC regulators are also available.Note: In addition to applying power to the "PWR IN" terminal block, remember to also apply power to the VIO terminal of the EFP01.This is normally done by connecting the USB Micro-B connector on the EFP0111 Evaluation Board to a power source. Also note that all ground connections on the board, including ground on the USB Micro-B connector, are connected together to the same ground plane on the board.The figure below shows an overview of the power terminal blocks and test points, and how a typical measurement setup on theInsert USB cable (provides power to VIO)VIN power Supply 1.5 - 5.5 VLoad Note:Figure 2.4. Typical Connection2.2.3 Digital InterfaceThe EFP01 is connected to the host MCU through two I 2C lines (SCL and SDA), one interrupt line (IRQn), a power rail (VIO) and ground. Except for the ground connection, the EFP can be disconnected from the rest of the board by removing four 0 Ω resistors which are located on the secondary side of the board. The lines are exposed on the footprint for a 2x4, 2.54 mm pitch pin header (P202) as illustrated in the figure below. This header can be used for connecting the EFP01 to an external host or hardware. This is, however,considered an advanced use-case and the user needs to make sure the connection does not violate any absolute maximum ratings of the devices on the board or the external hardware.Important: If doing any modifications on the board, make sure to not violate any absolute maximum ratings of the devices on the board or the external hardware.V I OI R Q n S C LS D AP C 0P C 1P C 133V 3To Host MCU To EFP01P202Figure 2.5. Interface Between the EFP Digital Block and the Host MCU2.2.4 On-Board LDOAn LDO is present on the board that draws current from the USB Micro-B connector and generates 3.0 V. This power rail is not used elsewhere on the board. Applications that only draw a small amount of current, such as testing different register settings with no or high impedance loads, may take advantage of this rail to simplify the hardware setup. This rail is exposed on pad 1 of the footprint (ST208)for a 2x1, 2.54 mm pitch pin header. Pad 1 of this footprint can be shorted to pad 2 in order to connect the 3.0 V rail to the VIN net.Care must be taken to not connect an external power source to the VIN terminal block (P200) when these pads are shorted together.Important: The intended use-case for the on-board LDO is for high impedance loads and in the absence of a power source on the VIN terminal block. Do not apply a power source on the VIN terminal block (P200) while ST208 is shorted.ST208VIN 3.0 VPWR INV I N GN DP200Figure 2.6. Optional On-board LDO Available For Low Current Applications2.2.5 Design NotesThe printed circuit board (PCB) for this evaluation board has been designed to support both the EFP0108 Evaluation Kit (SLEVK1000A)and the EFP0111 Evaluation Kit (SLEVK100B). The kit has not been designed to optimize the BOM with respect to a given application,and hence, more optimum designs might exist. For guidelines on more optimized BOMs please consult the datasheet.2.3 Host MCU 2.3.1 EFP01 InterfaceThe connection between the host MCU and the EFP01 is illustrated below. The connection can be removed with the 0 Ω resistors as described in section 2.2.3 Digital Interface .Host MCU (EFM32TG11)Figure 2.7. Interface Between the Host MCU and the EFP012.3.2 Push Buttons and LEDsThe kit has two user push buttons marked BTN0 and BTN1. They are connected directly to the the host MCU (EFM32TG11) and are debounced by RC filters with a time constant of 1 ms. The buttons are connected to pins PB11 and PC14.The kit also features three user LEDs that is controlled by GPIO pins on the host MCU (EFM32TG11). The LEDs are connected in an active-high configuration. The LEDs are connected to pins PA0, PA1 and PA2.Host MCU (EFM32TG11)Figure 2.8. Buttons and LEDs2.3.3 Breakout PadsThe host MCU (EFM32TG11) has four GPIO pins that are not used on the board. These are routed to breakout pads together with the 3V3 rail and ground as illustrated in the figure below.3V3GN D P E 10P E 11P E 12P E 13Figure 2.9. Host MCU (EFM32TG11) Breakout Pads2.4 On-board DebuggerThe EFP0111 Evaluation Board contains a microcontroller separate from the host MCU (EFM32TG11) that provides the user with an on-board J-Link debugger through the USB Micro-B debugging port. This microcontroller is referred to as the "on-board debugger", and is not programmable by the user. The debugger allows the user to download code and debug applications running in the host MCU, and it provides a virtual COM port (VCOM) to the host computer that is directly connected to the host MCU's serial port.Figure 2.10. On-Board Debugger Connections2.4.1 Virtual COM PortThe virtual COM port is a connection to a USART of the host MCU, and allows serial data to be sent and received from the device. The on-board debugger presents this as a virtual COM port on the host computer that shows up when the USB cable is inserted.Data is transferred between the host computer and the debugger through the USB connection, which emulates a serial port using the USB Communication Device Class (CDC). From the debugger, the data is passed on to the host MCU through a physical USART con-nection.The serial format is 115200 bps, 8 bits, no parity, and 1 stop bit.Note: Changing the baud rate for the COM port on the PC side does not influence the USART baud rate between the debugger and the target device.3. Design FilesDesign files are available through Simplicity Studio when the kit documentation package has been installed.4. Kit Revision History The kit revision can be found printed on the kit packaging label, as outlined in the figure below.SLEVK1000BEFP0111 Evaluation Kit12480204210-01-20A01Figure 4.1. Kit Label4.1 SLEVK1000B Revision HistoryKit Revision History | Building a more connected world.Rev. 1.1 | 11Document Revision History 5. Document Revision HistoryRevision 1.115 January 2020•Updated kit revision history.Revision 1.020 December 2019•Initial document release.Simplicity StudioOne-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux!IoT Portfolio /IoTSW/HW/simplicityQuality/qualitySupport and Community Silicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701USADisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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