(完整版)TMS320C6455高速SRIO接口设计

1Prerequisites PreliminaryApplication ReportSPRAAA8A–August2006Implementing Serial Rapid I/O PCB Layout on aTMS320C6455Hardware Design Todd Hiers DSP Hardware ApplicationsThis application report contains implementation instructions for the Serial Rapid I/O(SRIO)interface on the TMS320C6455DSP device.The approach to specifyinginterface timing and physical requirements for the SRIO interface is quite different thanprevious approaches for other interfaces.Serial Rapid I/O is an industry-standard high-speed switched-packet interconnect.Physical layer data transmission utilizes analog serializer/deserializers(serdes)to feedlow-output-swing differential CML buffers.Proper printed circuit board(PCB)design forthis interface resembles analog or RF design,and is very different than traditionalparallel digital bus design.Due to this analog nature of SRIO,it is not possible to specify the interface in atraditional DSP digital interface manner.Furthermore,it is undesirable to specify theinterface in terms of the raw physical requirements laid out by the SRIO specification.Understanding the SRIO specification and producing a compliant PCB based on theexplicit and implicit requirements there demands significant time,experience,andexpensive tools.For the TMS320C6455SRIO interface,the approach is to reduce the specification to aset of easy-to-follow PCB routing rules.TI has performed the simulation and systemdesign work to ensure SRIO interface requirements are met.This document describesthe content of this SRIO implementation.Contents1Prerequisites (1)2TMS320C6455Supported Serial RapidIO Devices (2)3Description of the Serial Rapid I/O Hardware Design Files (2)4PCB Routing Rules (2)5Device Settings (7)6References (10)The goal of the C6455collateral is to make system implementation easier for the customer by providing the system solution.For this Serial RapidIO(SRIO)interface,it is not assumed that the system designer is familiar with SRIO,serializer-deserializer(SERDES)technology,or RF/Microwave PCB design.However, it is still expected that the PCB design work be supervised by a knowledgeable high speed digital PCB designer and an assumption is made that the PCB designer is using established high speed design rules.SPRAAA8A–August2006Implementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware Design1 Submit Documentation Feedback2TMS320C6455Supported Serial RapidIO Devices3Description of the Serial Rapid I/O Hardware Design Files4PCB Routing Rules 4.1Minimum PCB Stackup4.2General Trace/Space and Via SizesPreliminaryTMS320C6455Supported Serial RapidIO DevicesRapidIO is an industry-standard high-speed switched-packet interconnect.The RapidIO specification allows a device to connect to any other device,so long as the two devices conform to a commonphysical-layer specification.TI DSPs support connecting to any Serial RapidIO device that complies with the Serial RapidIO specification revision 1.2or later.The SRIO Hardware Design files included with this report are described inTable 1.Table 1.SRIO Hardware Design FilesThe minimum PCB stackup for routing the TMS320C6455is a six-layer stackup as described in Table 2.Table 2.Minimum PCB StackupLayer Type Description 1Signal Top Routing 2Plane Ground 3Plane Split Power 4Signal Internal Routing5Plane Ground 6SignalBottom RoutingAdditional layers may be added as needed.All layers with SRIO traces must be able to achieve 100ohms differential impedance.Note:The provided sample board file shows a twelve-layer stackup,but not all of these layers are necessary to use the SRIO interface.The key concern for RapidIO signal traces is to achieve 100Ohm differential impedance.This differential impedance is impacted by trace width,trace spacing,distance between planes,and dielectric material.Verify with a proper PCB manufacturing tool that the trace geometry for all SRIO traces results in exactly 100Ohms differential impedance traces.Of secondary concern is the insertion loss caused by the traces.Due to the skin effect,wider traces will have lower losses than narrower ones.Therefore,longer SRIO runs should use wider traces for lower yers in the stackup that are set to 100Ohm differential impedance with wider traces may be less desirable for routing other signals.Table 3shows recommendations for minimum trace width by SRIO signal run lengthImplementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware Design2SPRAAA8A–August 2006Submit Documentation Feedback4.3Serial RapidIO Interface Routing Requirements4.3.1Receiver EndPreliminaryPCB Routing RulesTable 3.Minimum Trace WidthSignal Run Length,up to Minimum trace width 10in /25cm 4mil /.1mm 20in /50cm 6mil /.15mm 30in /75cm8mil /.2mmThe C6455sample PCB is routed using 4mil traces and 4mil minimum trace spacing.100Ohmsdifferential impedance is achieved with 4mil traces and 10mil spaces on the Top and Bottom layers,and 4mil traces with 5mil spaces on internal layers.Escape and general SRIO routing vias have 8mil holes with 18mil pads.Micro and/or blind/buried vias are neither required nor prohibited.The PCB BGA padC6455by the Flip Chip Ball Grid Array Package Reference Guide available at The C6455is a 0.8mm ball pitch part and should follow the 0.8The PCB for the SRIO link partner device should follow its manufacturer's guidelines.The approach used in this reference design for specifying suitable RapidIO routing breaks the physical connection down into three component pieces:receiver end,transmitter end,and interconnect.The receiver and transmitter end are the pieces closest to the packages of the connected devices.The receiver end goes from the BGA pads to the capacitors.The transmitter end is simply the BGA escape paths for the differential pairs.Those two pieces of the reference layout are designed to be copied exactly into the target board.The interconnect joins the receiver and transmitter ends,and it is not intended to be copied directly,as board placements will vary from the sample.Figure 1below shows the connection on the receiver end.The trace from the BGA pad to the capacitor be on the top layer.On the other side of the capacitor,it is recommended to via to another layer.The BGA breakout should be implemented exactly as shown.The trace widths and separation should be altered based on the board stackup to meet the 100Ωdifferential impedance requirement.Also,traces may be necked down to escape the BGA,if necessary.An 0402or smaller size,0.1µf capacitor is recommended for AC coupling of the data lines.SPRAAA8A–August 2006Implementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware Design 3Submit Documentation FeedbackPreliminary PCB Routing RulesFigure1.Receiver END BGA Breakout4.3.2Transmitter EndFigure2below shows the connection on the transmitter end.This trace may be on any signal layer the top.Internal layers are recommended for their superior shielding characteristics.The BGA breakout should be implemented exactly as shown.The trace widths and separation should be altered based on the board stackup to meet the100Ωdifferential impedance requirement.Also,traces may be necked down to escape the BGA,if necessary.4Implementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware Design SPRAAA8A–August2006Submit Documentation Feedback4.3.3Interconnect4.3.4Length MatchingPreliminaryPCB Routing RulesFigure 2.Transmitter End BGA BreakoutThe geometry of the traces to link the transmitter and receiver ends is determined by the placement in the target system.Therefore,it is not possible to specify an exact layout for the interconnect.Instead,the trace may be placed as required,so long as it meets the following requirements:•Edge-coupled,matched-length (±50mils)differential pair •No stubs•No more than 30inches (75cm)pin-to-pin,for 8-mil (.2mm)wide traces over FR4material •100Ωdifferential impedance•No more than 3sets of vias (not including via for BGA breakout on transmit end)•Other signals are separated by at least 2x the differential spacing •Internal layers are strongly preferred.Avoid top and bottom layers•If connectors are used,they must be of a suitable 100ohm differential-impedance,high-speed type,and count as 1”of trace for each connector pair•If cabling is used,it must be of a suitable controlled-impedance type (100ohm differential or 50ohm single ended),and counts as 1"of trace for each 1'of cable.•If a mid bus probe is used,it must follow both TI’s and the probe manufacturer’s guidelines,and counts as 2”of traceIf the SRIO peripheral will be used in 1x mode,then there is no lane-to-lane length matching requirement.If the SRIO peripheral will be used in 4x mode,then:•All TX lanes connected to a device must all be +/-5inches (12.5cm)in length from each other •All RX lanes connected to a device must all be +/-5inches (12.5cm)in length from each other •There is no requirement that the TX lengths match the RX lengthsSPRAAA8A–August 2006Implementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware Design5Submit Documentation Feedback4.3.5Mid Bus Probe (Optional)4.3.6Connectors (Optional)4.3.7Cabling (Optional)PreliminaryPCB Routing RulesA mid bus probe can be used to observe traffic flowing down a link.Because the probe requires a special attachment point,it can degrade signal quality.The following rules must be observed to include a mid bus probe:•Follow the Probe manufacturer’s guidelines for probe pads and layout•If the stubs can be kept under 250mils (6.35mm)then connecting the probe lands as stubs to the transmission line is acceptable•If the stubs cannot be kept under 250mils (6.35mm)then the probe lands should be connected in-line with the rest of the transmission lineAny connectors used must be controlled impedance (50Ohm single ended or 100Ohm differential)and suitable for microwave transmissions.Suitable connectors are typically categorized as “backplane”type connectors.The connectors should have less than 1dB insertion loss below 6GHz.Some suggested connectors are:•CN074–AMC Connector •Tyco Z-DOK•Tyco Z-PAK HM ZdAny cabling used must be controlled impedance (50Ohm single ended or 100Ohm differential)and suitable for microwave transmissions.Recommended cable types are listed below:•50Ohm Coaxial –Commonly used with SMA connectors,4cables required for 1x link,16for 4x link q RG142q RG316q RG178•Infiniband –assembled cables available in 1x and 4x widthsImplementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware Design6SPRAAA8A–August 2006Submit Documentation Feedback4.4Power SupplyRequirements5Device SettingsPreliminaryDevice SettingsThe power supply and bypassing requirements foras part of the TMS320C6455Design Guide and Comparisons to TMS320TC6416T Figure 3.Power Plane SplitsSome of the SERDES register values should be set based on parameters from the physical PCB.Others are not dependent on the PCB,but are set based on the SRIO electrical specification.The following sections describe the recommended settings for the receivers and transmitters.More these registers can be found in the TMS320C645x Serial Rapid IO (SRIO)User’s Guide SPRAAA8A–August 2006Implementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware Design 7Submit Documentation Feedback5.1Receive Channel ConfigurationPreliminaryDevice SettingsTable 4lists the recommended settings for receiver channels that can be set in the SERDES Receive Channel Configuration Registers (SERDES_CFGRXn_CNTL).Table 4.SERDES Receive Channel Configuration Register SettingsBits Field Setting Description19:22EQ 0001Fully Adaptive Equalization 18:16CDR000First Order.Sufficient for SRIO clocking scheme(asynchronous with low frequency offset)15:14LOS 00Disabled.Loss of Signal detection not used in SRIO 13:12ALIGN01Comma Alignment.SRIO uses comma alignment during lane initialization10:8TERM 001Common point is 80%ofVDDT.This is the appropriate setting for AC coupled lines 7INVPAIR 0Non-inverted –use when TXP connects to RXP and TXN connects to RXN1Inverted –use when TXP connects to RXN and TXN connects to RXP (1)6:5RATE 00Full –Use for 3.125GHz and 2.5GHz line rates01Half –Use for 1.25GHz line rate4:2BUS-WIDTH 00010-bit.SRIO uses 10-bit character groups.ENRX0Disabled –for unused lanes 1Enabled –for active lanes(1)On inverted pairs,polarity inversion can be done at the receiver end or the transmitter end,but not bothImplementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware Design8SPRAAA8A–August 2006Submit Documentation Feedback5.2Transmit Channel Configuration PreliminaryDevice SettingsTable5lists the recommended settings for transmitter channels that can be set in the SERDES Transmit Channel Configuration Registers(SERDES_CFGTXn_CNTL).Table5.SERDES Transmit Channel Configuration Register Settings Bits Field Setting Description16ENFTP1Fixed Phase.Required for4xmode.Do not care in1x mode.15:e for lines up to10inches(25cm)e for lines up to14inches(35cm)e for lines up to18inches(45cm)e for lines up to22inches(55cm)e for lines up to26inches(65cm)e for lines up to30inches(75cm) 11:e for lines up to10inches(25cm)e for lines up to20inches(50cm)e for lines up to30inches(75cm) 8CM1Raised Common Mode.Helpfulin preventing signal distortionat SWING amplitudes over750mV 7INVPAIR0Non-inverted–use when TXPconnects to RXP and TXNconnects to RXN1Inverted–use when TXPconnects to RXN and TXNconnects to RXP(1) 6:5RATE00Full–Use for3.125GHz and2.5GHz line rates01Half–Use for1.25GHz linerate4:2BUS WIDTH00010-bit.SRIO uses10-bitcharacter groups.0ENTX0Disabled–for unused lanes1Enabled–for active lanes(1)On inverted pairs,polarity inversion can be done at the receiver end or the transmitter end,but not bothSPRAAA8A–August2006Implementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware Design9 Submit Documentation Feedback6ReferencesPreliminaryReferencesmay be downloaded from the RapidIO Trade Association’s web site,The TMS320C645x Serial Rapid IO (SRIO)User’s Guide explains the functional operation of the SRIO peripheral.The TMS320C6455Design Guide and Comparisons to TMS320TC6416T (SPRAA89)containsinformation related to powering,clocking,and configuring the C6455,including the SRIO peripheral.The High Speed DSP Systems Design Guide (SPRU889)contains general guidance on many matters of high performance DSP system design.The Flip Chip Ball Grid Array Package Reference Guide provides guidance with respect to PCB design and Texas Instruments BGA packages.It rules,PCB assembly parameters,rework process,thermal management,troubleshooting tips plus other critical information.10Implementing Serial Rapid I/O PCB Layout on a TMS320C6455Hardware DesignSPRAAA8A–August 2006Submit Documentation FeedbackIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. 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第12卷 第1期 太赫兹科学与电子信息学报Vo1．12，No．1 2014年2月 Journal of Terahertz Science and Electronic Information Technology Feb．，2014 文章编号：2095-4980(2014)01-0136-05基于TMS320C6455 DSP的PCI接口设计熊 璐(中国电子科技集团公司 第10研究所，四川 成都 610036)摘 要：TMS320C6455是TI公司的一款高性能数字信号处理芯片(DSP)，具有丰富的外部接口。

本文介绍了该芯片外围设备组件互连(PCI)接口控制器的性能特点，DSP内部的工作机制，地址映射方式，详细分析了2种工作方式的总线传输特点和性能，并给出了将其应用于卫星基带信号接收卡的设计实例。

通过使用TMS320C6455 DSP的PCI控制器简化了硬件接口设计，具有灵活高效的特点，已在工程应用中取得了良好效果。

关键词：TMS320C6455接口；外围设备组件互连；地址映射；总线传输；中断中图分类号：TN111文献标识码：A doi：10.11805/TKYDA201401.0136Peripheral Component Interconnect interface design based onTMS320C6455 Digital Signal ProcessingXIONG Lu(The 10th Research Inst. of the CETC，Chengdu Sichuan 610036，China)Abstract：TMS320C6455 is a kind of high-performance fixed-point Digital Signal Processing(DSP), which integrates various peripherals. This paper firstly introduces the features of the PeripheralComponent Interconnect(PCI) interface controller, the way to communicate with other modules in DSP andthe address mapping of slave/master work mode. Then bus transfer characteristics and performance of twowork modes is analyzed in detail and the application of its PCI interface controller on satellites basebandsignal receiver is also given. TMS320C6455’s PCI interface controller can simplify the hardware design,and have the characteristics of flexible and efficient, therefore it has good application prospects inengineering practice.Key words：TMS320C6455；Peripheral Component Interconnect；address mapping；bus transfer；interruptPCI总线是一种高性能局部总线，其数据总线为32 bit，可扩展为64 bit，最大数据传输速率为128 MBps~ 528 MBps。

基于TMS320C6455的目标跟踪系统设计与实现
张庆龙;张辉;毛征;赵齐月;刘金
【期刊名称】《国外电子测量技术》
【年(卷),期】2015(0)5
【摘要】介绍了一种基于高速处理芯片TMS320C6455和FPGA架构的目标跟踪系统。

该系统以DSP与FPGA为主体设计一套图像处理设备,利用局域熵算法来实现简单背景下小目标的跟踪。

FPGA采用Xilinx公司生产的XC5VSX95T,用来对原始图像数据进行预处理。

DSP芯片采用TI公司生产的TMS320C6455,通过局域熵算法对预处理后的图像进行实时跟踪并且将目标信息返回FPGA。

FPGA获得跟踪结果后,将目标信息与原图像叠加,通过显示器将图像结果进行显示。

局域熵算法经过优化后,目标检测跟踪时间大大缩短,满足硬件系统实时性的要求。

【总页数】4页(P75-78)
【关键词】DSP;局域熵;目标跟踪
【作者】张庆龙;张辉;毛征;赵齐月;刘金
【作者单位】北京工业大学电子信息与控制工程学院
【正文语种】中文
【中图分类】TN820.4
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编号：_______________本资料为word版本，可以直接编辑和打印，感谢您的下载基于SRIO协议的板级芯片互联技术甲方：___________________乙方：___________________日期：___________________引言软硬件结合构建宽带互联并行处理的数据处理系统是实现高速实时数据处理的有效方案。

基于这样的方案设计理念，采用多DSP、多FPGA通过SRIO互联来实现一个高速互联的计算网络，数据可以在DSP 之间及DSP与FPGA之间高速传输。

这样的互联计算网络在数据交互、任务切换、算法分解、计算负载均衡等方面具有较强的适应性、可扩展性。

本文介绍了这种基于SRIO互联技术的高速实时数据处理硬件平台，并在该平台上研究了多DSP之间、DSP与FPGA之间的SRIO通信技术。

1 SRIO标准RapiclI /。

是面向嵌入式系统开发提出的高可靠、高性能、基于包交换的新一代高速互联技术，已于2004年被国际标准化组织（ISO）和国际电工协会（IEC）批准为ISO/IECDIS 18372标准。

SRI。

则是面向串行背板、DSP和相关串行数据平面连接应用的串行RapidIO接口。

串行RapidIO包含一个3层结构的协议，即物理层、传输层、逻辑层。

物理层定义电气特性、链路控制、低级错误管理；传输层定义包交换、路由和寻址机制；逻辑层定义总体协议和包格式。

可以实现最低引脚数量，采用DMA 传输，支持复杂的可扩展拓扑，多点传输；可选的 1. 25 Gbps、2 . 5 Gbps、3 . 125 Gbps三种速度能满足不同应用需求，是未来十几年中嵌入式系统互联的最佳选择之一。

2基于C6455高速SRIO接口的互联系统2. 1 C6455 的SRIO 端口TMS320C6455（简称C6455）是德州仪器（TD公司新推出的一款DSP产品，可实现更高性能，精简代码，更多片上存储器及超高带宽的集成外设。

基于TMS320 C6455的以太网通信程序的设计
邓伟;王文菊
【期刊名称】《电子设计工程》
【年(卷),期】2013(21)7
【摘要】文中介绍了TMS320 C6455 DSP EMAC接口的构成以及工作原理和关键数据结构,参考相关的以太网驱动程序,完成了基于C6455 DSP的以太网通信程序的设计.该网络通信程序实现了某款信号处理机与上位机之间的高速通信接口.系统测试结果表明,利用C6455实现的以太网通信接口完全满足系统设计要求,并且系统具有组成简单、系统集成度高等优点.该方案在其他多功能信号处理设备方面具有一定的应用价值.
【总页数】4页(P165-168)
【作者】邓伟;王文菊
【作者单位】通信信息控制和安全技术重点实验室浙江嘉兴314033;中国电子科技集团公司第三十六研究所浙江嘉兴314033;中国电子科技集团公司第三十六研究所浙江嘉兴314033
【正文语种】中文
【中图分类】TN332
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第一章dsp数据采集板构成DSP板结构框图DSP板的结构如上图所示。

信号处理板是系统的核心，是所有算法实现的基础，同时信号处理板又负责整个系统的控制和条度。

信号处理板的功能主要有：·8000MMAC/s·100Mbit/s的高速以太网通信·RS422·64个数字IO·24路14bit差分/单端ADC，最高采样300kSa/s·2路高速DAC，12bit，125MSa/s·8路低速DAC，IIC接口[这个没有使用，因为速度太慢]·256MByteDDRIIRAM·4个LED指示灯1、DSPTMS320C6455的功能框图该平台的核心器件数字信号处理器采用德州仪器最新款的高性能数字信号处理器TMS320C6455。

与以往的数字信号处理器相比，TMS320C6455具有更强大的运算能力和更大的IO带宽。

TMS320C6455工作在1GHz，可实现每秒80亿次乘法累加（MAC），TMS320C6455增加了更多的片内存储器，具有256K的一级程序缓存和256K的一级数据缓存，具有2M的可配置的二级缓存和256K的只读存储器。

TMS320C455采用697脚的BGA 封装。

TMS320C6455不但具有强大的处理能力还有丰富的对外接口，来构成一个完整的应用系统，该信号处理平台的大部分器件都是接在TMS320C6455上的。

TMS320C6455的主要接口如下·64位，133-MHz EMIFA接口可以与同步存储器连接，例如SBSRAM、ZBT SRAM。

也可以同异步存储器实现无缝连接，例如SRAM、FLASH和EEPROM。

该接口还可以和标准同步器件和用户逻辑器件连接，例如FPGA、CPLD、ASICs。

·四个高速串行IO接口·32位DDR2内存接口·32（16）位HPI，32位PCI接口·一个Inter-Integrated Circuit接口·两个MCBSP接口·一个10/100/1000MBPs自适应以太网接口·两个64位的定时器·一个UTOPIA接口·16个通用数字IO口2、FPGAVirtexII1000的资源情况FPGA采用Xinlix公司的Virtex II系列的XC2V1000，该器件的密度为100万门。

TMS320C6455高速SRIO接口设计引言数字信号处理技术已广泛应用于通信、雷达、声纳、遥感、图形图像处理和语音处理等领域。

随着现代科技的发展，尤其是半导体工艺的进入深亚微米时代，新的功能强劲的高性能数字信号处理器(DSP)也相继推出，如ADI（美国模拟器件）公司的TigerSHARC系列和TI（德州仪器）公司的C6000系列，但是，要实现对运算量和实时性要求越来越高的DSP 算法，如对基于分数阶傅立叶变换的Chirp信号检测与估计，合成孔径雷达(SAR)成像，高频地波雷达中的自适应滤波和自适应波束形成等算法，单片DSP 仍然显得力不从心。

这些挑战主要涉及两个主题：一是计算能力，指设备、板卡和系统中分别可用的处理资源。

采用多DSP、多FPGA系统，将是提高运算能力的一个有效途径。

二是连接性，从本质上说就是实现不同设备、板卡和系统之间的“快速”数据转移。

对于一些复杂的信息系统，对海量数据传输的实时性提出了苛刻的要求，多DSP之间、DSP与高速AD采集系统、DSP与FPGA间的高速数据传输，是影响信号处理流程的主要瓶颈之一。

TI公司最新推出的高性能TMS320C6455（下文称C6455）处理器，具有高速运算能力的同时集成了高速串行接口SRIO，方便多DSP以及DSP与FPGA之间的数据传输，在一定程度上满足了高速实时处理和传输的要求。

本文在多DSP+FPGA通用信号处理平台的基础上，深入研究了多DSP间，DSP与FPGA间的SRIO 的数据通信和加载技术的软硬件设计与实现。

这些技术包括了目前SRIO接口的各种应用方式，可作为SRIO接口及C6455开发提供参考[1-3]。

1 C6455特性及SRIO标准介绍C6455是目前单片处理能力最强的新型高性能定点DSP，它是TI 公司基于第三代先进VeloviTI VLIW(超长指令字)结构开发出来的新产品。

最高主频为1.2GHz，16位定点处理能力为9600MMAC/s。

TMS320C6455高速SRIO接口设计引言数字信号处理技术已广泛应用于通信、雷达、声纳、遥感、图形图像处理和语音处理等领域。

随着现代科技的发展，尤其是半导体工艺的进入深亚微米时代，新的功能强劲的高性能数字信号处理器(DSP)也相继推出，如ADI（美国模拟器件）公司的TigerSHARC系列和TI（德州仪器）公司的C6000系列，但是，要实现对运算量和实时性要求越来越高的DSP 算法，如对基于分数阶傅立叶变换的Chirp信号检测与估计，合成孔径雷达(SAR)成像，高频地波雷达中的自适应滤波和自适应波束形成等算法，单片DSP 仍然显得力不从心。

这些挑战主要涉及两个主题：一是计算能力，指设备、板卡和系统中分别可用的处理资源。

采用多DSP、多FPGA系统，将是提高运算能力的一个有效途径。

二是连接性，从本质上说就是实现不同设备、板卡和系统之间的“快速”数据转移。

对于一些复杂的信息系统，对海量数据传输的实时性提出了苛刻的要求，多DSP之间、DSP与高速AD采集系统、DSP与FPGA间的高速数据传输，是影响信号处理流程的主要瓶颈之一。

TI公司最新推出的高性能TMS320C6455（下文称C6455）处理器，具有高速运算能力的同时集成了高速串行接口SRIO，方便多DSP以及DSP与FPGA之间的数据传输，在一定程度上满足了高速实时处理和传输的要求。

本文在多DSP+FPGA通用信号处理平台的基础上，深入研究了多DSP间，DSP与FPGA间的SRIO 的数据通信和加载技术的软硬件设计与实现。

这些技术包括了目前SRIO接口的各种应用方式，可作为SRIO接口及C6455开发提供参考[1-3]。

1 C6455特性及SRIO标准介绍C6455是目前单片处理能力最强的新型高性能定点DSP，它是TI 公司基于第三代先进VeloviTI VLIW(超长指令字)结构开发出来的新产品。

最高主频为1.2GHz，16位定点处理能力为9600MMAC/s。