Wafer Fabrication

Wafer FabricationFor more info, Please visit the following websites:http://www.leb.e-technik.uni-erlangen.de/lehre/mm/html/start.htmJust copy it from the websites.The first step in wafer production is the fabrication of a silicon single crystal. A small crystal, called the seed crystal, is rotated and slowly withdrawn from the molten hyper-pure silicon to give a cylindrical crystal. The silicon crystal is sliced to obtain thin disks, known as wafers on which chips are made, hundreds at a time, during the following processing. After slicing, the wafers are finely ground, mirror-smooth polished and cleaned.The most common semiconductor material used today is silicon. In addition to silicon, numerous other materials have been studied, and gallium arsenide (GaAs) is used instead of silicon in some applications at present (e.g. high-frequency devices).All processes require extremely clean rooms with filtered air to have a low concentration of particles of dust or other contaminants so that a high chip yield can be attained.Three important steps during crystal fabricationOxidation Processes in SemiconductorManufacturingToday's ULSI technology is to a large extent based on the excellent properties of thermally grown silicon dioxide layers. SiO2 is used as gate dielectric in MOS devices, as implantation or doping mask, and for device isolation purposes.Most of the silicon oxidation processes today are carried out at atmospheric pressure in oxidation furnaces at temperatures between 800 and 1,200°C. Theappropriate oxidant gases are dry oxygen, wet oxygen (water steam). For wet oxidation, the water steam can be extracted by influx of gases (oxygen, argon, or nitrogen) into a vessel filled with water. Another possibility is to initiate a reaction of oxygen and hydrogen at the inlet of the reactor tube. The wafers are placed verticallyor horizontally in quartz boats and the temperature of the hot zone is controlled withan accuracy of 1°C, in order to grow oxide layers in a reproducible manner.It has been proven by a number of experiments that thermal oxidation of silicon proceeds by diffusion of the oxidant through the growing oxide. The oxidation reaction itself takes place at the oxide-silicon interface. During oxidation, theoxide-silicon interface moves into the silicon material as the silicon is oxidized. Taking into account the densities of silicon and of SiO2, it can be shown that about 44% of the oxide layer grows into the silicon substrate. The remaining 56% grows on topof the silicon, resulting in a non-planar surface if oxidation is local.The lateral and vertical isolation of device structures in ULSI determines to a large extent the performance of the technology with respect to packaging density and parasitic effects. Classical local oxidation (LOCOS) has been widely used to laterally isolate the active regions of an integrated circuit. The oxide is grown at those parts of the wafer surface where a Si3N4 masking layer has its openings. Before starting the oxidation there is already a thin oxide layer in between the nitride layer and thesilicon substrate. Because of diffusion of the oxidant into the region below the nitride, also the oxide beneath the nitride is growing leading to the characteristic bird's beak shape after completion of the process. This situation is illustrated in the Figure 1, which shows the result of an oxidation in wet oxygen at 950°C for 10 hours(from: C. Claeys, J. Vanhellemont, G. Declerck, J. Van Landuyt, R. Van Overstraeten, S. Amelinckx, VLSI Science and Technology/1984, K.E. Bean, G. Rozgoni, Eds., The Electrochemical Society, Pennington, 1984, p. 272.).Figure 1: TEM picture of a bird's beak, obtained by using classical LOCOS.Figure 2: Loading of wafers into oxidation furnance.Deposition Processes in SemiconductorManufacturing TechnologyFor the deposition of conducting and insulating materials in semiconductor processing, a wide range of different techniques is used. Among them, physical vapor deposition (PVD) and chemical vapor deposition (CVD) are the most important ones.Materials in semiconductor manufacturing that can be deposited by CVD are for example: Silicon dioxide, silicon nitride, polysilicon, tungsten, copper, titanium nitride, aluminum. the link:Examples for CVD processes.Examples for CVD Processes Used in Semiconductor Manufacturing.Materials in semiconductor manufacturing that can be deposited using PVD are for example: aluminum, titanium, titanium nitride, tantalum, copper.Sputter reactorPrinciple of Physical Vapor Deposition (Sputter Deposition)At low pressure, a voltage is applied to two parallel electrodes resulting in a plasma discharge. The accelerated gas ions impinge onto the cathode (target) and metal atoms are emitted from the target which deposit on the wafer leading to layer growth.Reactor for sputter depositionUsually the conformality (perfect conformality means, that for all positions at the device surface the same layer thickness is achieved) of CVD layers is much better than the conformality of PVD layers. This is demonstrated by the 2 movies: the first one shows a 3D simulation of a sputter deposition of aluminum into a contact hole, the second one shows a 3D simulation of tungsten CVD into the same contact hole. The CVD process yields better layer conformality than the PVD process.The 3D simulations shown in the movies have been carried out using the topography simulator SC-TOP from the software house SIGMA-C. Within SC-TOP, a 3D module for layer deposition developed at FhG-IIS-B is used.Sputter deposition of aluminum(130 kB) Tungsten CVD(121 kB)3D simulation of aluminum sputter deposition in a contact holeBlue: initial surface before depositionGreen: evolving surface of the deposited aluminumIt can be seen that the conformality of the layer is poor, that means the layer thickness inside the contact hole is much smaller than the thickness on top of the structure.3D simulation of tungsten CVD in a contact holeBlue: initial surface before depositionGreen: evolving surface of the deposited tungstenAlthough the conformality is rather good, an enclosed gas volume (so-called void) remains after the opening of the hole is closed by the growing layer.It is also possible to perform simulations on equipment scale. For instance, the temperature distribution in a CVD furnace can be calculated by means of simulation. As an example we show the simulation of the heating of a deposition furnace, carried out with the program PHOENICS-CVD by Cham.Heating of a deposition furnace(356 kB)Lithography in Semiconductor ManufacturingTechnologyLithography is the process of transferring geometric shapes on a mask to the surface of a silicon wafer. These shapes make up the parts of the circuit, such as gate electrodes, contact windows, metal interconnections, an so on. The final integrated circuit (IC) is made by sequentially transferring the features from each mask level by level, to the surface of the silicon wafer. For example, between each successive image transfer an ion implant, drive-in, oxidation, or metallization operation may take place.In the IC lithographic process, a photosensitive polymer film is applied to the silicon wafer, dried, and then exposed with the proper geometrical patterns through a photomask to ultraviolet (UV) or other radiation. After exposure, the wafer is brought into contact (e.g. by dipping or spraying) with a solution that develops the images in the photosensitive material. Depending on the type of polymer used, either exposed (in the case of positive resists) or non-exposed (for negative resists) areas of the film are removed in the developing process. After development the resist acts as a mask, for instance for etching patterns into underlying layers.Resists are made that are sensitive to UV light, electron beams, or ion beams. At present, optical lithography is the prevailing method. In the figure below, an example for the application of resist on the wafer is shown.In the animation below, we show a 3D simulation of the development process of a positive resist layer which has been exposed to light with anwavelength of 365 nm (so called i-line) through a mask with a square opening. Such kind of pattern is used for example to etch contact holes in insulating material underneath the resist. The simulation has been carried out with the lithography simulator SOLID-C which has been developed at FhG and which is commercially available from the softwarehouse SIGMA-C.Start the animation (346 kB)3D simulation of a lithographic development processWe show a 3D simulation of the development process of a positive resist layer which has been exposed to light with an wavelength of 365 nm (i-line) through a mask with a 0.5 micron square mask opening. The wavy shape of the developed resist is due to standing waves which form in the resist during exposure and which lead to significantly varying exposure doses for different depths in the resist layer.Etching Processes in Semiconductor ManufacturingEtching processes are used to partly remove material in order to create patterns to obtain the desired device or interconnect geometry. Particles in the etching component (a liquid or gas) remove material by attacking the open surface.The material may be isotropically removed, known as chemical or "wet" etching, or be etched in a plasma reactor ("dry"-etching). In the case of a dry-etching process, the total etch rate consists of an ion-assisted rate and a purely chemical etch rate due to etching by neutral radicals, which may still have a directional component. The total etch rate can depend on shadowing within the reactor and by the structure on the substrate itself, the angle-dependent flux distribution of particles from the reactor volume, the angle of incidence of the particles relative to the surface normal direction, reflection/re-emission of etching particles, and surface diffusion effects. Reactive ion etching (RIE) provides high anisotropy which is achieved by etching that is enhanced (via different mechanisms) by ions impinging onto the surface. The main advantage of RIE is enhanced directionality which becomes increasingly important as device sizes decrease substantially and etching must proceed in vertical direction without affecting adjacent features.Bench used for wet-etching of 300 mm wafers.In the animation below, we show an etching process where a contact hole is opened by a combination of an isotropic chemical etching step followed by a highly directional RIE step. The process has been simulated by using the program SC-TOP by SIGMA-C.Start the animation (82 kB)Simulation of an etching process to open a contactholeIn the animation shown above, a rotationally symmetric contact hole is etched using a resist layer as mask. What is shown is a slice through the middle of the contact hole.The hole is etched by an isotropic wet-etching step followed by a reactive ion-etching step which is highly directional. The advantage is that it is easier to fill such a contact by metal sputtering than a contact that is created by a directional process only. The reason is that the upper part of the contact (created by the isotropic etch step) is widened so that metal atoms from the reactor volume can better reach positions inside the contact than in the case of a directionally etched contact.Diffusion Processes in Semiconductor TechnologyDiffusion of impurity atoms in silicon during processing is important for the electrical characteristics of silicon devices. Various ways of introducing dopants into silicon by diffusion are used and have been studied with the goals of controlling dopant distribution, total dopant concentration, uniformity, and reproducibility.Diffusion is used to form base, emitter, and collector regions in bipolar device processing, to form source,drain and channel regions, and to dope polysilicon in MOS processing. Dopant atoms that span a wide range of concentrations can be introduced into silicon in many ways. The most commonly used methods are1.Diffusion from a chemical source in a vapor form at hightemperatures,2.Diffusion from a doped-oxide source, and3.Diffusion and annealing from an ion-implanted layer (see ionimplantation).The electrical activation of ion-implanted species is carried out by annealing. This causes a redistribution of the impurity atoms which should be as low as possible. In order to optimize the electrical behavior of the device, it is important to know how the impurities redistribute during the anneal. The development of appropriate models and simulation programs to predict the diffusion is one major topic in semiconductor technology research.Vertical furnace which can be used for diffusion, oxidation,or for chemical vapor deposition (CVD) processes.Below we show several examples of how dopants redistribute during diffusion processes. The simulations have been carried out with the 1D process simulator ICECREM from FhG-IIS-B.You can have a look at the following 1D simulations:Diffusion from a source with constant concentration(144 kB)Diffusion of a shallow profile in a semi-infinite half-space.(141 kB) Redistribution of boron after ion implantation(192 kB)Boron diffusion in oxidizing atmosphere(182 kB)Phosphorus diffusion in oxidizing atmosphere(179 kB)Codiffusion of arsenic and boron(178 kB)Diffusion of boron at high concentrations(148 kB)Ion Implantation Processes in SemiconductorManufacturingIntroductionFor performing ion implantation, atoms or molecules are ionized, accelerated in an electric field and implanted into the target material. A widevariety of combinations of target material and implanted ions are possible. The dose of the implanted ions can vary between 1011 and 1018 cm-2. Usually, the acceleration energy lies between several keV and several hundred keV, but with special equipment it is possible to work with energies up to several MeV. The range of the implanted ions in the substrate depends on the mass of the implanted ions, their energy, the mass of the substrate atoms, crystal structure and the direction of incidence. As an example, the mean range of 100 keV phosphorus ions in silicon is about 150 nm.Main advantages of ion implantation (in comparison to diffusion) for the doping of semiconductors are:Short process times, good homogeneity and reproducibility of the profilesExact control of the amount of implanted ions by integrating the current. This is of particular importance for low concentrations, e.g.for adjusting the threshold voltage of MOS transistorsRelatively low temperatures during the processDifferent materials can be used for masking, e.g. oxide, nitride, metals, and resistImpla ntation through thin layers (e.g. SiO2 or Si3N4) is possibleLow penetration depth of the implanted ions. This allows modification of thin areas near the surface with high concentration gradientsSequences of implantation steps (with different energi e s and doses) allow optimization of the dopant profilesThere are also some disadvantages, such as:Damage of the substrate is caused by the implanted ionsThe change of material properties is restricted to the substrate domains close to the surfaceAdditional effects during or after implantation (such as channeling or diffusion) make it difficult to achieve very shallow profiles and to theoretically predict the exact profile shapes.Depth ProfilesThe larger is the energy of the ions during ion implantation, the deeper penetrate the ions into the target. The ion trajectories are statistically distributed in the target due to the collisions of the ions with the target atoms being affected by partly randomly distributed impact parameters. Therefore not all ions stop at the same depth but there is a certain depth distribution of the ions after ion implantation. The depth distributions of the implanted ions in silicon are presented in the following figures:Energy dependence of depths profiles for boron implantationDose dependence of depths profiles for boron implantationBoron, implantation energy 100 keVEnergy dependence of depths profiles for phosphorus implantationDose dependence of depths profiles for phosphorus implantationEnergy dependence of depths profiles for arsenic implantationDose dependence of depths profiles for arsenic implantationArsenic, implantation energy 100 keVThe maximum of a typical implantation profile in crystalline silicon is mainly formed by the randomly moving ions. At larger depth, a contribution of channeled ions is dominant. The channeling effect is only possible in a crystalline material. For larger implantation doses, the silicon crystal is damaged and channeling becomes less probable. Therefore, the maximum of the doping distribution grows approximately proportional to the dose of implantation while the tail has the tendency to saturate at certain doses. This effect is seen for phosphorus and arsenic ions. For boron, the damage probability is lower and the saturation of the channeling tail is not seen up to doses 5*1015 cm-2 for a conventional 7 degree tilted ion implantation.As you may see in this picture, the heavier is the ion, the shorter is its penetration range at the same energy.Monte-Carlo Method for Simulation of Ion Implantation Since the process of ion implantation has a statistical nature, it is straight-forward to use statistical methods to simulate it on computers. The most important of such methods is the Monte-Carlo method. which is based on the usage of random numbers. Particularly, the position where an ion hits the crystalline target is calculated using random numbers. Furthermore, the atoms of any material are in a permanent movement due to thermal vibrations. The actual positions of the vibrating atoms in the target are also simulated using random numbers. The trajectories of the ion are determined by the interactions of the implanted ions with the target atoms. The final position of an implanted ion is where it has lost its complete energy. As an example we show ion trajectories calculated with the Monte-Carlo method in crystalline silicon:Trajectories of boron ionsTrajectories of arsenic ionsThe more ion trajectories are used in a Monte-Carlo simulation the more accurate is the result. This example (77 kB) shows how the simulated doping distribution in an NMOS transistor depends on the number of the simulated ion trajectories.The Monte-Carlo simulation results shown here have been calculated with the code MCIMPL developed at The Institute for Microelectronics, TU ViennaThe dose and energy dependences of implantation profiles have been simulated using ICECREM process simulator developed at the Fraunhofer Institute of Integrated CircuitsCoupled 2D Process and Device Simulation The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) in combination with other electronic devices allows the amplification of voltages and a high signal-power gain. MOSFETs are widely used in power electronics and above all, they are the core of integrated circuit (IC) technology at the present time. Because of the small size, millions of MOSFET devices can be integrated into one single chip. This opportunity and the fact that MOSFETs consume only very little energy, are the key to the rapid development of modern ASIC s (application specific ICs) and memory chips.In MOS technology, typical device dimensions like the gate length are reduced below one micron, e.g. in today's (1999) state-of-the-art memory products the minimum feature size is 0.25 microns. In these advanced devices, trade-off relationships cause limitations to the device performance and new physical effects arise. In order to reduce the development time and the immense costs, computer simulations become moreimportant. TCAD (technology computer aided design) based layout and the simulation of new devices offer the possibility to approximately predict the electrical behavior before processing any material. After calibration, the number of experiments to optimize an existing technology is reduced by the use of modern 1D, 2D and 3D simulation programs. Moreover, simulations help to estimate the influence of process fluctuations on device behavior which becomes more serious in the sub-micron-regime.A typical simulation setup consists of a coupled process and device simulation. The process simulation is performed to determine the device geometry and the dopant distribution in the active regions resulting from a sequence of process steps. Using the process simulation result as input, the electrical behaviour of the component can be simulated by means of device simulation.You can get more information about process simulation and have a look at an example of an advanced NMOS transistor here.A detailed look on a two-dimensional device simulation of this transistor gives you an insight into the device during the development of the characteristic curve.The simulations shown in this presentation have been carried out by using the software DIOS ISE (process simulation) and DESSIS ISE (device simulation), both from the software house ISE AG.Simulation of the Process Flow for the Fabrication of an NMOS TransistorYou can have a look at the following process steps:Step 1Step 2Step 3Step 4Step 5Step 6Step 7Step 8Step 9Step 10Step 11Step 12Step 13Step 14Step 15Step 16Step 17Step 18Step 19Step 20Step 21For more info, Please visit the following websites: http://www.leb.e-technik.uni-erlangen.de/lehre/mm/html/start.htmJust copy it from the websites.。