(1)-balanced-systems-new

  • 格式:pdf
  • 大小:800.93 KB
  • 文档页数:47

Systems/application software faces real challenges
To utilize parallelism in multicore is much more complex Resource competition in multicore cause new problems Software needs reconstructions to adapt its new home
Bad News in demand
CPU cycles per Watt decreases. (less energy efficient). Cache capacity: always limited. Improvement of data access latencies significantly lags behind.
Foot Steps of Challenges in HPC
1970s-80s: Killer applications demand a lot of CPU cycles
a single processor was very slow (below 1MH) challenges: parallel algorithms, architecture, implement
CPU Cycle Time
SRA A M ccess Time
DRA A M ccess Time
Disk Seek Time
Device Name CPU Cycle Time SRAM Access Time DRAM Access Time Disk Seek Time
1980(ns) 1,000 300 625 87,000,000
4
challenge II: Networks of Workstations for HPC
Moore’s Law in 37 Years (IEEE Spectrum, May 2008)
5
Implications and New Challenges
Single-core CPU reached its peak performance
Date Communication in Computer Systems
Source
Transfer Bandwidth Time
Destination
Latency Time
Destination-perceived latency reduction is still limited due Destination-perceived latency reduction is still limited due to imbalanced improvement of bandwidth and latency to imbalanced improvement of bandwidth and latency
Increased DRAM capacity enables large working sets
1971 ($400/MB) to 2006 (0.09 cent/MB): 444,444 times lower Buffer cache is increasingly important to break “disk wall”
1980s: communication bottlenecks and burden of PP
challenge I: fast interconnection networks challenge II: automatic PP, and shared virtual memory 1990s: “Memory Wall” and utilization of commodity processors challenge I: cache design and optimization
100
50% per year
10
DRAM
1
00 98 02 20 94 88 80 82 84 86 90 92 96 19 20 19 19 19 19 19 19 19 19 19 20 04
Latency Gaps Am ong CPU, Cache, DRAM, and Disk
100000000 10000000 1000000 100000 ns 10000 1000 100 10 1 1980 1985 1990 Year 1995 2000
Desktops, laptops, PDAs, etc. directly connect to the Internet or via wireless
Major Resources in Computing and Network Systems
Good News in supply
CPU cycles: oversupplied for many applications. Memory bandwidth: improved dramatically. Memory capacity: increasingly large and low cost. I/O bandwidth: improved dramatically. Disk capacity: huge and cheap. Cluster and Internet bandwidths: very rich.
Ultra high performance but expensive. (customer designed nodes/networks)
Cluster systems, e.g. ICT’s Downing (and many other Top-500’s)
Low cost, but low sustained performance. (commodity nodes/networks) Google has been a successfully scalable example.
Balancing System Resource Supply and Demand for Effective Computing
Xiaodong Zhang
Ohio State University
Computing is Pervasive and Powerful
Computing resources become cheap and prolific.
6
Multi-Core is the only Choice to Continue Moore’s Law
1.73 x
Much better performance
1.73 x
Similar power consumption
1.00 x 1.00 x
1.13 x 0.87 x
1.02 x
0.51 x
1.2 87,000 0.3 0.375 0.9 451,807 0.7 560,000 2 11.66 2.5 1.25 37.5 1,666,666
Limited by the mechanic components, the disk’s performance is seriously lagging behind the CPU and memory. In 1980, one disk seek costs 87,000 cycles, in 2000, one disk seek costs over 5,000,000 cycles. The disks in 2000 are more than 57 times “SLOWER” than their ancestors in 1980.
2000(ns) 1.6 20 100 8,000,000
Improvement 625.00x 15.00x 6.25x 10.87x
Latencies of Cache, DRA and Disk in CPU Cycles M
5,000,000
5000000 4500000 4000000 3500000 3000000 Cycles 2500000 2000000 1500000 1000000 500000 0 1980 1985 1990 Year SRAM Access Time DRAM Access Time Disk Seek Time 1995 2000
7
CPU-DRAM Gap is no longer a Major Bottleneck
100000
• Cache optimization only. • Limited cache capacity would not hold working sets of data intensive applications.
Global systems, e.g., TeraGrid. Microsoft/IBM “cloud computing”
Utilizing global computing resources, but high Internet cost and overhead.
Clients are pervasive in everywhere in the globe
Latency Lags Bandwidth (CACM, Patterson)
• In the last 20 years, 100–2000X improvement in bandwidth 5-20X improvement in latency Between CPU and on-chip L2: bandwidth: 2250X increase latency: 20X reduction Between L3 cache and DRAM: bandwidth: 125X increase Latency: 4X reduction Between DRAM and disk: bandwidth: 150X increase latency: 8X reduction Between two nodes via a LAN: bandwidth: 100X increase latency: 15X reduction