半导体工艺2

Chapter 2 Basic VLSI/ULSI FabricationProcess TechnologyI. Evolution of IC Process TechnologyII. Main LSI/VLSI processes developed in historyIII. CMOS core based ULSI technology---basis of presentMicroelectronicsIV. Main elemental devices and process flow of IC fabrication V. Major chip fabrication material and technologyVI. Ultra clean technologies-of vital importance for VLSI/ULSI manufacturingI. Evolution of IC Process Technologyz IC circuitry evolution determined by process progress ---Bipolar process: RTL, DTL, TTL, STTL, LSTTL, ECL, I 2L…..---MOS Process: PMOS, NMOS, CMOS---JFET, MESFETz Process technology---Most active factor in IC progress ---PN junction formed by growth doping or metal/Ge(Si) alloy doping in 1950s---PN junction formed by blanket diffusion doping in 1950s ---Transistor formed by planar process based on diffusion, oxidation and lithograph in late 1950s*Double diffused mesa transistor process*Transistor by planar processz Transistor and other circuit elements formed by planar technology---On-chip resistor: by diffusion;poly-Si by deposition--- On-chip capacitor: metal/I/Si;M/I/M; Poly-Si/I/Poly-Si (I-SiO2or other dielectric film)--- On-chip inductor: spiral metal linewith ground shieldII. Main LSI/VLSI processes developed in historyz Main LSI/VLSI/ULSI requirements:---High integration density---High speed---High reliability---Low powerz PMOS:---Early LSI/VLSI products: calculators, electronic game,...---Low speedz NMOS:---Higher speed than PMOS---Main VLSI process in 80’s for DRAM, microprocessorsz Standard bipolar (LSTTL, ECL…)---High driving capability---Applied for high-speed devices: Early high-speed computer, communication system, …---Lower integration density and higher power consumptionz I2L bipolar---Lower power & higher integration than standard bipolar ---Lower speedz CMOS---Lowest power consumption than all others---Noise resistance and higher reliability---Main stream of VLSI/ ULSI process since late 80’sz BiCMOS---Combination of high speed and low power---High process complexityz GaAs MESFET IC---High-speed devices for communication, etc.---Possibility of integration with photonic devicesIII. CMOS core based ULSI technology---basis of present Microelectronicsz Low power consumption---essential requirement for ULSI/SoC chipz CMOS based Si process---dominant ULSI technologyz Combination of CMOS core process and special process modules→Various ULSI chip technologies---DRAM,SRAM, Flash EPROM, Logic, BiCMOSCommunication ICs,…→System on Chip (SoC) technologyIV. Main elemental devices and process flow of IC fabrication z All IC are based on few main device effects---pn junction: transistor, diode, JFET---Field effect: PMOS, NMOS---Schottky barrier effect: SBD, MESFET*Their fundamental physics---Interface effectsz Schematic crosssection and processtechnology for0.18μm CMOS ofBell Labz Main Si chipfabrication processflow diagramEtchingz Wafer fabrication process module—Process module—a group of process steps to form a part structure of IC—The entire IC wafer manufacturing process consists of 14-20 process modules—A typical process module consists of 10-20 process steps —Process integration—of vital importance for success of a certain fabrication technologyV. Major chip fabrication material and technology(1) Si material— Large-diameter and defect-free Si crystal growth Φ100ÆΦ125ÆΦ150ÆΦ200ÆΦ300ÆΦ450(mm) — Thin Si layer epitaxial growthn-Si layer/p-Si substrate, n/n+, p/p+— SiGe/Si hetero-epitaxy; strained SiGe or strained Si— SOI(Si on Insulator) materialBy SIMOX (O+-implant), bonding/smart-cut— Gettering technology(2) Fine pattern microstructure formation technology— Reticle/mask pattern generation by e-beam— Optical lithographyUV Lamp g-line=436nm Æ 0.5μmi-line=365nm Æ 0.35μmDUV Eximer Laser*KrF 248nm Æ 250, 180 nm …*ArF 193nm Æ 130, 110, 90, 65nm，45nm*ArF 193nm (Immersion) Æ32nm, 22nmF2 157nm(?); Ar2 126nm(?)*EUV Laser plasma source: 13nmPhase shift mask and other wave-front technologyÆPattern feature < λStep-and-Scan exposure system— E-beam lithography (for mass production tool still in R&D) Direct writing on wafer and other methods— Mix-and-Match lithography— High resolution resist material and process— High resolution etching technology (Ex. HDP-RIE)— Self-aligned microstructure formationBy selective etching, reaction, epitaxy and other methods(3) Selective Doping Technology— Si transistor--product of doping engineering*Device type and performance--determined by impurity doping profile ( element, concentration, distribution)— Low energy ion implant and shallow junction formation---Of vital importance for nano-meter CMOS fabrication— High energy ion implant for n/p wells— Rapid thermal process (RTP) and dopant atom diffusion control(4) Dielectric Thin Film Material and Process— Ultra thin gate oxide growth---Of key important for advanced CMOS: 30nm Æ 0.8nmBy using nitrided oxide— High-K dielectrics for gate application*Intensive investigation on a series of materials with k~10-100HfO2, Al2O3, ZrO2, ZrSi x O y, TaO x N y, HfSi x O y, TiO2, La2O3, SrTiO3 …— Low-K dielectrics for inter-metal isolationInorganic/Organic K<3.9*High-density plasma (HDP) CVD deposition*SOG (Spin-On-Glass), SOP (Spin-On-Polymer)(5) Device Isolation Technology: from pn junction isolation tonew dielectric isolation— Modified LOCOS (Local Oxidation of Si)Poly-Si buffered LOCOS (PBL)— Shallow trench isolation (STI)(6) Contact and Interconnection— Polycide (silicide/poly-Si) gate electrode & interconnect (WSi2)— Salicide process – Self-aligned silicide formation on S/G/D TiSi2Æ CoSi2, NiSi— New type of metal gate technology— Diffusion barrier (TiN, TaN…)— High conductive and reliable interconnect material & process: Al-Si-Cu alloy, W-plug, Cu-damascene— Multilevel interconnection4-5 levels Æ >10 levels— CMP planarization(7) Si based hetero-structure material and device process (A field expecting more invention and creation in the years ahead) — Si/SiGe/Si hetero-junction bipolar transistor (HBT) process— Strained Si/SiGe or SiC channel PMOS/NMOS devices— GaAs on Si and other semiconductors on SiExample: --GaAs-MESFET on GaAs/STO(Strontium Titanium Oxide) /SiO2/Si(A work of Motorola: SST, July/2002)VI. Ultra clean technologies-of vital importance forVLSI/ULSI manufacturingz Wafer environment cleanliness and utility purity (wafer, gas, chemicals…)*Minimum defect density requirement for different DRAM generationsDRAM process technology 4M 16M 64M 256M 1GDesign rule(μm) 0.8 0.5 0.35 0.25 0.13Critical layer 9 10 11 13Critical particle size (nm) 120 90 50 30Killing defect size (μm) 0.27 0.18 0.1 0.06Defect density measured at thekilling defect size (D/cm2)0.50 0.40 0.32 0.22Defect density measured at 0.12μm particle size (D/cm2)2.53 0.90 0.22 0.055Defect density/critical levelmeasured at 0.12μm particlesize (D/cm2)0.28 0.09 0.02 0.004Defect improvement factor 1 3 14 65(source :KLA)Clean room class 1 0.1 0.1 0.1/mini-environment)0.1/mini-environment)DI water required specificationsResistivity (MΩ·cm)>18.0 >18.1 >18.2>0.085μm <10 <2 <0.5 Particle(pieces/cc) >0.05μm<5<1 Bacteria (Unit/L) <10 <1 <1TOC (ppb) <20 <5 <1 Oxygen (ppb) <50 <10 <5Silica (ppb) <3 <1 <0.2Na, Cl (ppb) <0.1 <0.05 <0.01 Metal ion (ppb) <0.1 <0.05 <0.01 Required chemicals specifications0.2μm <50<10<1 Particles0.1μm <100<10 Anion (ppb) <500 <100 <50Metal (ppb) <10 <1 <0.2 Required bulk gas specificationsParticle level: size(μm)-pcs/cc 0.1-<5 0.1-<50.05-<5Impuritylevel(O2,CO,CO2,CH4)(ppb)<10 <5 <1H20 level (ppb) <100 <10 <0.13Metal level (μg/m3) 10.10.01z Control of the wafer environment is of crucial importance for wafer manufacturing process*Cleanroom fab by carefully designed filtration and laminar- flow circulation for the air to create a clean environment; higher and higher cleanliness required for ULSI*Pure/clean and dust-free materials for all utilities and equipments*Ultra-clean mini-environment required for update ULSI; Transport of wafers between minienviroments by means of SMIF (standard mechanical interfaces) podsExample of cleanroom layout and its cleanlinessz Wafer-cleaning process—critical step in IC manufacturing to obtain an ultraclean wafer surface--free from particles, organic contamination, metal contamination, surfacemicro-roughness andnative oxide*Various contaminants to beremoved by cleaning process*Wafer cleanliness hascrucial effect on thequality of ultra thingate oxide and otherthin film/thin layer;many process factorsmay cause surfacecontaminationz RCA cleaningprocess and itsmodified recipe arecommonly used in Si-IC process*RCA cleaningprocess—first developed by Kern and Puotinen in 1960 at RCA and published in 1970*Two sequential RCA Standard Cleaning solutions based onH2O2, NH4OH, and HCl: SC-1 & SC-2SC-1: NH4OH/H2O2/H2O (1:1:5 to 0.5:1:5); 70-80°C, 10-15 min To remove organic films by oxidation and certain metals (Au, Ag, Cu, Ni, Zn, Cd, Co, Cr and IB/IIB group metals) by complexing; Native oxide etching & re-oxidation→ to dislodge particles; Microroughness from Si-etching by NH4OH--∴less NH4OH is preferred and H2O2 depletion should be avoidedSC-2: HCl/H2O2/H2O (1:1:6 to 1:1:8); 70-80°C, 10-15 minTo remove alkali ions and cations like Al+3, Fe+3 and Mg+2 (they form NH4OH insoluble hydroxides in SC-1) and other metal residue/contamination by forming a soluble complex*Effort to modify recipe of RCA cleaning process: IMEC cleaning process with more diluted solutions for better cleaning effect and with better enviromental protectionz Other important solutions for wafer cleaningSPM (Sulfuric-Peroxide Mixture) solution: H2SO4/H2O2 (1:1 to 4:1); 120-150°C, 10 min; To remove organics and stripe photoresistDHF (Diluted HF) solution: HF/H2O (1:10 to 1:50); room temperature, 1 min; to remove chemical oxide grown by SC-1, SC-2, SC-3 cleaning processz Standard wafer cleaning processing*SPM clean→ DI H2O rinse→ HF/H2O etching→ DI H2O rinse→ SC-1 clean →DI H2O rinse→ SC-2 clean→ DI H2O rinse → HF/H2O etching → DI H2O rinse → Dry*Depletion of H2O2 in SC-1 solution should be avoided to protect Si surface from NH4OH etching*Ultrasonic agitation is used to dislodge particles。