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M50FLW040BNB1P中文资料

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1/52PRELIMINARY DATAAugust 2004This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.M50FLW040A M50FLW040B4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors)3V Supply Firmware Hub / Low Pin Count Flash MemoryFEATURES SUMMARYsFLASH MEMORY–Compatible with either the LPC interfaceor the FWH interface (Intel Spec rev1.1) used in PC BIOS applications– 5 Signal Communication Interfacesupporting Read and Write Operations – 5 Additional General Purpose Inputs forplatform design flexibility–Synchronized with 33MHz PCI clock s8 BLOCKS OF 64 KBYTES – 5 blocks of 64 KBytes each– 3 blocks, subdivided into 16 uniformsectors of 4 KBytes eachTwo blocks at the top and one at the bottom (M50FLW040A)One block at the top and two at the bottom (M50FLW040B)sENHANCED SECURITY–Hardware Write Protect Pins for BlockProtection–Register-based Read and WriteProtectionsSUPPLY VOLTAGE–V CC = 3 to 3.6V for Program, Erase andRead Operations–V PP = 12V for Fast Program and Erase sTWO INTERFACES–Auto Detection of Firmware Hub (FWH) orLow Pin Count (LPC) Memory Cycles for Embedded Operation with PC Chipsets –Address/Address Multiplexed (A/A Mux)Interface for programming equipment compatibility.s PROGRAMMING TIME: 10µs typical sPROGRAM/ERASE CONTROLLER–Embedded Program and Erase algorithms –Status Register BitssPROGRAM/ERASE SUSPEND–Read other Blocks/Sectors duringProgram Suspend–Program other Blocks/Sectors duringErase SuspendsELECTRONIC SIGNATURE –Manufacturer Code: 20h–Device Code (M50FLW040A): 08h –Device Code (M50FLW040B): 28hM50FLW040A, M50FLW040BTABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2.Logic Diagram (FWH/LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 3. Logic Diagram (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 1.Signal Names (FWH/LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 2.Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 4.PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 5.TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 6.TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 3.Addresses (M50FLW040A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 4.Addresses (M50FLW040B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . .10 Input/Output Communications (FWH0/LAD0-FWH3/LAD3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Input Communication Frame (FWH4/LFRAME).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1010 CPU Reset (INIT).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Top Block Lock (TBL).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1011 Reserved for Future Use (RFU).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .11 Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Row/Column Address Select (RC).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 V CC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 V PP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 V SS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Table 5.Memory Identification Input Configuration (LPC mode). . . . . . . . . . . . . . . . . . . . . . . . . .12BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122/52M50FLW040A, M50FLW040BBus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 6.FWH Bus Read Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 7.FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 7.FWH Bus Write Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 8.FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 8.LPC Bus Read Field Definitions (1-Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 9.LPC Bus Read Waveforms (1-Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 9.LPC Bus Write Field Definitions (1 Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 10.LPC Bus Write Waveforms (1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 10.A/A Mux Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table mand Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Read Electronic Signature Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 12.Electronic Signature Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Quadruple Byte Program Command (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Double/Quadruple Byte Program Command (FWH Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table mands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Program/Erase Controller Status (Bit SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Erase Suspend Status (Bit SR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Erase Status (Bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Program Status (Bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 V PP Status (Bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Program Suspend Status (Bit SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..22 Block Protection Status (Bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Reserved (Bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233/52M50FLW040A, M50FLW040B4/52Table 14.Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS . . .24Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Read Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 15.Configuration Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 16.Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 17.General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register . . . . . . . . . . . . . .25 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 18.Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 19.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 20.Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 21.FWH/LPC Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 22.A/A Mux Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 11.FWH/LPC Interface AC Measurement I/O Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 12.A/A Mux Interface AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 23.Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 24.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 14.FWH/LPC Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 25.FWH/LPC Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figure 15.FWH/LPC Interface AC Signal Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Table 26.FWH/LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 16.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 27.Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Figure 17.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Table 28.A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Figure 18.A/A Mux Interface Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Table 29.A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Figure 19.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline. . . . . . . .36 Table 30.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data37 Figure 20.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . .38 Table 31.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . .38 Figure 21.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . .39M50FLW040A, M50FLW040B Table 32.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data .39PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 33.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Table 34.M50FLW040A Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 35.M50FLW040B Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only). . . . .45 Figure 24.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . .46 Figure 25.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . .47 Figure 26.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . .48 Figure 27.Sector/Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Figure 28.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . .50REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 36.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .515/52M50FLW040A, M50FLW040B6/52SUMMARY DESCRIPTIONThe M50FLW040 is a 4 Mbit (512Kb x8) non-vola-tile memory that can be read, erased and repro-grammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines, an optional 12V power supply can be used to reduce the erasing and programming time.The memory is divided into 8 Uniform Blocks of 64KBytes each, three of which are divided into 16uniform sectors of 4KBytes each (see APPENDIX A. for details). All blocks and sectors can be erased independently. So, it is possible to pre-serve valid data while old data is erased. Blocks can be protected individually to prevent accidental program or erase commands from modifying their contents.Program and erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re-quired to update the memory contents. The end of a program or erase operation can be detected andany error conditions identified. The command set to control the memory is consistent with the JE-DEC standards.Two different bus interfaces are supported by the memory:s The primary interface, the FWH/LPCInterface, uses Intel ’s proprietary Firmware Hub (FWH) and Low Pin Count (LPC)protocol. This has been designed to remove the need for the ISA bus in current PCChipsets. The M50FLW040 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.s The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers, for production lineprogramming prior to fitting the device in a PC Motherboard.The memory is supplied with all the bits erased (set to ’1’).M50FLW040A, M50FLW040BNote: 1.ID3 is Reserved for Future Use (RFU) in LPC mode.Table 1. Signal Names (FWH/LPC Interface) Table 2. Signal Names (A/A Mux Interface) FWH0/LAD0-FWH3/LAD3Input/Output CommunicationsFWH4/LFRAMEInput Communication FrameID0-ID3Identification InputsGPI0-GPI4General Purpose InputsIC Interface ConfigurationRP Interface ResetINIT CPU ResetCLK ClockTBL Top Block LockWP Write ProtectRFUReserved for Future Use. LeavedisconnectedV CC Supply VoltageV PP Optional Supply Voltage for FastProgram and Erase OperationsV SS GroundNC Not Connected InternallyIC Interface ConfigurationA0-A10Address InputsDQ0-DQ7Data Inputs/OutputsG Output EnableW Write EnableRC Row/Column Address SelectRB Ready/Busy OutputRP Interface ResetV CC Supply VoltageV PPOptional Supply Voltage for FastProgram and Erase OperationsV SS GroundNC Not Connected Internally7/52M50FLW040A, M50FLW040B8/529/52M50FLW040A, M50FLW040BTable 3. Addresses (M50FLW040A)Table 4. Addresses (M50FLW040B)Note:Also see APPENDIX A., Table 34. and Table 35. for a full listing of the Block Addresses.BlockSize (KByte)Address Range Sector Size (KByte)6470000h-7FFFFh 16 x 4KBytes 6460000h-6FFFFh 16 x 4KBytes6450000h- 5FFFFh 5 x 64KBytes 6440000h- 4FFFFh 6430000h-3FFFFh 6420000h-2FFFFh 6410000h-1FFFFh 6400000h-0FFFFh16 x 4KBytes BlockSize (KByte)Address Range Sector Size (KByte)6470000h-7FFFFh 16 x 4KBytes6460000h- 6FFFFh 5 x 64KBytes 6450000h- 5FFFFh 6440000h- 4FFFFh 6430000h-3FFFFh 6420000h-2FFFFh 6410000h-1FFFFh 16 x 4KBytes 6400000h-0FFFFh16 x 4KBytesM50FLW040A, M50FLW040B10/52SIGNAL DESCRIPTIONSThere are two distinct bus interfaces available on this device. The active interface is selected before power-up, or during Reset, using the Interface Configuration Pin, IC.The signals for each interface are discussed in the Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions section and the Address/Address Multiplexed (A/A Mux) Signal Descriptions sec-tion, respectively, while the supply signals are dis-cussed in the Supply Signal Descriptions section.Firmware Hub/Low Pin Count (FWH/LPC) Signal DescriptionsPlease see Figure 2. and Table 1..Input/Output Communications (FWH0/LAD0-FWH3/LAD3).All Input and Output Communica-tions with the memory take place on these pins.Addresses and Data for Bus Read and Bus Write operations are encoded on these pins.Input Communication Frame (FWH4/LFRAME).The Input Communication Frame bus operation. When Input Communication Frame is Low, V IL , on the rising edge of the Clock, a new bus operation is initiated. If Input Communication Frame is Low, V IL , during a bus operation then the operation is aborted. When Input Communication Frame is High, V IH , the current bus operation is ei-ther proceeding or the bus is idle.Identification Inputs (ID0-ID3).Up to 16 memo-ries can be addressed on a bus, in the Firmware Hub (FWH) mode. The Identification Inputs allow each device to be given a unique 4-bit address. A ‘0’ is signified on a pin by driving it Low, V IL , or leaving it floating (since there is an internal pull-down resistor, with a value of R IL ). A ‘1’ is signified on a pin by driving it High, V IH (and there will be a leakage current of I LI2 through the pin).By convention, the boot memory must have ad-dress ‘0000’, and all additional memories are giv-en addresses, allocated sequentially, from ‘0001’.In the Low Pin Count (LPC) mode, the identifica-tion Inputs (ID0-ID2) can address up to 8 memo-ries on a bus. In the LPC mode, the ID3 pin is Reserved for Future Use (RFU). The value on ad-dress A19-A21 is compared to the hardware strap-ping on the ID0-ID2 pins to select the memory that is being addressed. For an address bit to be ‘1’,the corresponding ID pin can be left floating or driven Low, V IL (again, with the internal pull-down resistor, with a value of R IL ). For an address bit to be ‘0’, the corresponding ID pin must be driven High, V IH (and there will be a leakage current of I LI2 through the pin, as specified in Table 24.). For details, see Table 5..General Purpose Inputs (GPI0-GPI4).TheGeneral Purpose Inputs can be used as digital in-puts for the CPU to read, with their contents being available in the General Purpose Inputs Register.The pins must have stable data throughout the en-tire cycle that reads the General Purpose Input Register. These pins should be driven Low, V IL, or High, V IH , and must not be left floating.Interface Configuration (IC).The Interface Con-figuration input selects whether the FWH/LPC in-terface or the Address/Address Multiplexed (A/A Mux) Interface is used. The state of the Interface Configuration, IC, should not be changed during operation of the memory device, except for select-ing the desired interface in the period before pow-er-up or during a Reset.To select the FWH/LPC Interface, the Interface Configuration pin should be left to float or driven Low, V IL . To select the Address/Address Multi-plexed (A/A Mux) Interface, the pin should be driv-en High, V IH . An internal pull-down resistor is included with a value of R IL ; there will be a leakage current of I LI2 through each pin when pulled to V IH .Interface Reset (RP).The Interface Reset (RP)input is used to reset the device. When Interface IL , the memory is in Reset mode (the outputs go to high impedance,and the current consumption is minimized). When IH , the device is in normal op-eration. After exiting Reset mode, the memory en-ters Read mode.is used to Reset the device when the CPU is reset.It behaves identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical AND) of RP and INIT.Clock (CLK).The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0/LAD0-FWH3/LAD3.The Clock conforms to the PCI specification.The Top Block Lock in-put is used to prevent the Top Block (Block 7) from being changed. When Top Block Lock, TBL, is driven Low, V IL , program and erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock,TBL, is driven High, V IH , the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL, does not affect the protec-tion of the Main Blocks (Blocks 0 to 6). For details,see APPENDIX A..Top Block Lock, TBL, must be set prior to a pro-gram or erase operation being initiated, and must not be changed until the operation has completed,otherwise unpredictable results may occur. Simi-larly, unpredictable behavior is possible if WP is。

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PTH04070W中文资料

PTH04070W中文资料

FEATURESAPPLICATIONSDESCRIPTIONInhibit*See The Capacitor Application Information#See The Specification Table for ValuePTH04070WSLTS227–SEPTEMBER2004 3-A,3.3/5-V INPUT ADJUSTABLE SWITCHING REGULATOR•Ambient Temp.Range:–40°C to85°C•Up to3-A Output Current at85°C•Surface Mount Package• 3.3-V/5-V Input Voltage•Safety Agency Approvals:UL/CUL60950,EN60950VDE(Pending)•Wide-Output Voltage Adjust(0.9V to3.6V)•160W/in3Power Density•Telecommunications,Instumentation,•Efficiencies Up To94%and General-Purpose Circuits•On/Off Inhibit•Undervoltage Lockout(UVLO)•Output Overcurrent Protection(Nonlatching,Auto-Reset)•Overtemperature ProtectionThe PTH04070W is a highly integrated,low-cost switching regulator module that delivers up to3A of output current.Occupying less PCB area than a standard TO-220linear regulator IC,the PTH04070W provides output current at a much higher efficiency and with much less power dissipation,thereby eliminating the need for a heat sink.Their small size(0.5×0.4in),high efficiency,and low cost makes these modules attractive for a variety of applications.The input voltage range of the PTH04070W is from3V to5.5V,allowing operation from either a3.3-V or5-V input ing state-of-the-art switched-mode power-conversion technology,the PTH04070W can step down to voltages as low as0.9V from a5-V input bus,with typically less than1W of power dissipation.The output voltage can be adjusted to any voltage over the range,0.9V to3.6V,using a single external resistor.Operating features include an undervoltage lockout(UVLO),on/off inhibit,output overcurrent protection,and overtemperature protection.Target applications include telecommunications,test and measurement applications, and high-end consumer products.The modules are available in both through-hole and surface-mount package options,including tape and reel.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2004,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.ABSOLUTE MAXIMUM RATINGSRECOMMENDED OPERATING CONDITIONSPACKAGE SPECIFICATIONSPTH04070WSLTS227–SEPTEMBER 2004These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.ORDERING INFORMATIONPTH04070(Basic Model)Output Voltage Part Number Description Package DesignatorPTH04070WAH Horizontal T/H EVD 0.9V -3.6V PTH04070WAS (1)Horizontal SMDEVE(1)Add a T suffix for tape and reel option on SMD packages.over operating free-air temperature range unless otherwise noted (1)PTH04070UNIT T A Operating free-air temperature Over V in range-40to 85°C Solder reflow temperature Surface temperature of module body or pins235°C T stg Storage temperature-40to 125°C(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.MINMAX UNIT V I Input voltage3 5.5V T AOperating free-air temperature–4085°CPTH04070x (Suffix AH &AS)Weight 1.5gramsFlammability Meets UL 94V-OPer Mil-STD-883D,Method 2002.3,1msec,1/2sine,Mechanical shock 500Gs (1)mountedMechanical vibration Mil-STD-883D,Method 2007.2,20-2000Hz20Gs(1)(1)Qualification limit.2ELECTRICAL CHARACTERISTICSPTH04070W SLTS227–SEPTEMBER2004at25°C free-air temperature,VI =5V,VO=3.3V,IO=IO(Max),C1=47µF,C2=47µF(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITI O Output current T A=85°C,natural convection airflow03AV I Input voltage range Over I O range3 5.5VV O(tol)Set-point voltage tolerance T A=25°C±2%(1) Temperature variation-40≤T A≤+85°C±0.5%V OLine regulation Over V I range±1mVLoad regulation Over I O range±5mVIncludes set-point,line,load,Total output voltage variation3%(1)-40≤T A≤+85°CV I≥4.5V0.9 3.6V O(adj)Output voltage adjust range VV I<4.5V0.9V I–1.1(2)T A=25°C,I O=2AR SET=475Ω,V O=3.3V(2)92%R SET=2.32kΩ,V O=2.5V V(2)90%R SET=4.87kΩ,V O=2V88%ηEfficiencyR SET=6.65kΩ,V O=1.8V87%R SET=11.5kΩ,V O=1.5V85%R SET=26.1kΩ,V O=1.2V82%R SET=84.5kΩ,V O=1V80%Output voltage ripple20MHz bandwith10mV PPI O(trip)Overcurrent threshold Reset,followed by autorecovery7AC3=47µF,1A/µs load step from50%to100%I O maxTransient responseRecovery time70µsV O over/undershoot100mVV I=increasing 2.953UVLO Undervoltage lockout VV I=decreasing 2.7 2.8Input high voltage(V IH)V I–0.5Open(3)V Inhibit control(pin5)Input low voltage(V IL)–0.20.6Input low current(I IL)–10µAI I(stby)Input standby current Pins5and2connected1mAF S Switching frequency Over V I and I O ranges700kHzExternal input capacitance Ceramic type(C1)47(4)µFCeramic type(C2)47(5)200µF External output capacitance Nonceramic type(C3)47(5)560(6)Equivalent series resistance(nonceramic)4(7)mΩPer Bellcore TR-332,50%stress,MTBF Calculated reliability48106HrsT A=40°C,ground benign(1)The set-point voltage tolerance is affected by the tolerance and stability of R SET.The stated limit is unconditionally met if R SET has atolerance of1%with with100ppm/°C or better temperature stability.(2)The minimum input voltage is3V or(V O+1.1)V,whichever is greater.A5-V input bus is recommended for output voltages higher than2V.(3)This control pin has an internal pullup to the input voltage V I.If it is left open circuit,the module operates when input power is applied.Asmall low-leakage(<100nA)MOS field effect transistor(MOSFET)is recommended for control.See the application information for further guidance.(4)An external47-µF ceramic capacitor is required across the input(V I and GND)for proper operation.Locate the capacitor close to themodule.(5)An external47-µF ceramic capacitor is required across the output(V O and GND)for proper operation.Locate the capacitor close to themodule.Adding another47µF of electrolytic capacitance close to the load improves the response of the regulator to load transients. (6)This is the calculated maximum capacitance.The minimum ESR limitation often results in a lower value.See the capacitor applicationinformation for further guidance.(7)This is the typical ESR for all the electrolytic(nonceramic)e7mΩas the minimum when calculating the total equivalentseries resistance(ESR)using the max-ESR values specified by the capacitor manufacturer.3PIN ASSIGNMENTPTH04070WSLTS227–SEPTEMBER 2004TERMINAL FUNCTIONSTERMINALI/O DESCRIPTIONNAME NO.V I 1IThe positive input voltage power node to the module,which is referenced to common GND.This is the common ground connection for the V I and V O power connections.It is also the 0VDC GND 2reference for the Inhibit and V O Adjust control inputs.V O3O The regulated positive power output with respect to the GND node.A 1%resistor must be connected between this pin and GND (pin 1)to set the output voltage of the module higher than 0.9V.If left open-circuit,the output voltage defaults to this value.The temperature V O Adjust4Istability of the resistor should be 100ppm/°C (or better).The set-point range is from 0.9V to 3.6V.The electrical specification table gives the standard resistor value for a number of common output voltages.Refer to the application information for further guidance.The Inhibit pin is an open-collector/drain-negative logic input that is referenced to GND.Applying a low-level ground signal to this input disables the module's output.When the Inhibit control is active,the Inhibit 5Iinput current drawn by the regulator is significantly reduced.If the Inhibit pin is left open-circuit,the module will produce an output voltage whenever a valid input source is applied.4TYPICAL CHARACTERISTICS (5-V INPUT)(1)(2)E f f i c i e n c y − %I O − Output Current − A04812162000.511.522.53− O u t p u t V o l t a g e R i p p l e − m V V O I O − Output Current − AP P00.30.60.91.21.50.511.522.53− P o w e r Di s s i p a t i o n − WP D I O − Output Current − AI O − Output Current − AT e m p e r a t u r e D e r a t i n g −5C PTH04070WSLTS227–SEPTEMBER 2004EFFICIENCYOUTPUT RIPPLEvsvsOUTPUT CURRENTOUTPUT CURRENTFigure 1.Figure 2.POWER DISSIPATIONTEMPERATURE DERATINGvsvsOUTPUT CURRENTOUTPUT CURRENTFigure 3.Figure 4.(1)The electrical characteristic data has been developed from actual products tested at 25°C.This data is considered typical for the converter.Applies to Figure 1,Figure 2,and Figure 3.(2)The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures.Derating limits apply to modules soldered directly to a 100mm x 100mm double-sided PCB with 1oz.copper.Applies to Figure 4.5TYPICAL CHARACTERISTICS (3.3-V INPUT)(3)(4)E f f i c i e n c y − %I O − Output Current − A 04812162000.51 1.52 2.53I O − Output Current − A− O u t p u t V o l t a g e R i p p l e − m V V O P P0.30.60.91.21.500.51 1.52 2.53− P o w e r D i s s i p a t i o n − WP DI O − Output Current − AI O − Output Current − AT e m p e r a t u r e D e r a t i n g − 5CPTH04070WSLTS227–SEPTEMBER 2004EFFICIENCYOUTPUT RIPPLEvsvsOUTPUT CURRENTOUTPUT CURRENTFigure 5.Figure 6.POWER DISSIPATIONTEMPERATURE DERATINGvsvsOUTPUT CURRENTOUTPUT CURRENTFigure 7.Figure 8.(3)The electrical characteristic data has been developed from actual products tested at 25°C.This data is considered typical for the converter.Applies to Figure 5,Figure 6,and Figure 7.(4)The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures.Derating limits apply to modules soldered directly to a 100mm x 100mm double-sided PCB with 1oz.copper.Applies to Figure 8.6APPLICATION INFORMATIONAdjusting the Output Voltage of the PTH04070W Wide-Output Adjust Power ModulesR set+10k W0.891VV out*0.9V*3.24k WPTH04070WSLTS227–SEPTEMBER2004 The V O Adjust control(pin4)sets the output voltage of the PTH04070W product.The adjustment range is from 0.9V to3.6V.The adjustment method requires the addition of a single external resistor,R set,that must be connected directly between the V O Adjust and GND pin2.Table1gives the standard external resistor for a number of common bus voltages,along with the actual voltage the resistance produces.For other output voltages,the value of the required resistor can either be calculated using the following formula, or simply selected from the range of values given in Table2.Figure9shows the placement of the required resistor.Table1.Standard Values of R set for Common OutputVoltagesV out R set V out(Required)(Standard Value)(Actual)3.3V(1)475Ω 3.298V2.5V(1) 2.32kΩ 2.502V2V 4.87kΩ 1.999V1.8V 6.65kΩ 1.801V1.5V11.5kΩ 1.504V1.2V26.1kΩ 1.204V1V84.5kΩ 1.001V0.9V Open0.9V(1)The minimum input voltage is3V or(V O+1.1)V,whichever isgreater.(1)A0.05-W rated resistor may be used.The tolerance should be1%,with a temperature stability of100ppm/°C(orbetter).Place the resistor as close to the regulator as possible.Connect the resistor directly between pins4and2using dedicated PCB traces.(2)Never connect capacitors from V O Adjust to either GND or V O.Any capacitance added to the V O Adjust pin will affectthe stability of the regulator.Figure9.V O Adjust Resistor Placement7PTH04070WSLTS227–SEPTEMBER 2004Table 2.Calculated Set-Point Resistor ValuesV a Req'd R set V a Req'd R set V a Req'd R set 0.900Open 1.47512.3k Ω 2.55 2.16k Ω0.925353k Ω 1.5011.6k Ω 2.60 2.00k Ω0.950175k Ω 1.5510.5k Ω 2.65 1.85k Ω0.975116k Ω 1.609.49k Ω 2.70 1.71k Ω1.00085.9k Ω 1.658.64k Ω 2.75 1.58k Ω1.02568.0k Ω 1.707.90k Ω 2.80 1.45k Ω1.05056.2k Ω 1.757.24k Ω 2.85 1.33k Ω1.07547.7k Ω 1.80 6.66k Ω 2.90 1.22k Ω1.10041.3k Ω 1.85 6.14k Ω 2.95 1.11k Ω1.12536.4k Ω 1.90 5.67k Ω 3.00 1.00k Ω1.15032.4k Ω 1.95 5.25k Ω 3.05904Ω1.17529.2k Ω 2.00 4.86k Ω 3.10810Ω1.20026.5k Ω 2.05 4.51k Ω 3.15720Ω1.22524.2k Ω 2.10 4.19k Ω 3.20634Ω1.25022.2k Ω 2.15 3.89k Ω 3.25551Ω1.27520.5k Ω 2.20 3.61k Ω 3.30473Ω1.30019.0k Ω 2.25 3.36k Ω 3.35397Ω1.32517.7k Ω 2.30 3.12k Ω 3.40324Ω1.35016.6k Ω 2.35 2.90k Ω 3.45254Ω1.37515.5k Ω 2.40 2.70k Ω 3.50187Ω1.40014.6k Ω 2.45 2.51k Ω 3.55122Ω1.42513.7k Ω 2.502.33k Ω3.6060Ω1.45013.0k Ω8CAPACITOR RECOMMENDATIONS for the PTH04070W WIDE-OUTPUT Input CapacitorOutput CapacitorsCeramic CapacitorsTantalum CapacitorsCapacitor TablePTH04070W SLTS227–SEPTEMBER2004ADJUST POWER MODULESThe minimum recommended input capacitor(s)is47-µF of ceramic capacitance,in either an X5R or X7R temperature tolerance.The ceramic capacitors should be located within0.5in.(1,27cm)of the regulator's input pins.Electrolytic capacitors can also be used at the input,but only in addition to the required ceramic capacitance.The minimum ripple current rating for nonceramic capacitors should be at least200mA rms.The ripple current rating of electrolytic capacitors is a major consideration when they are used at the input.When specifying regular tantalum capacitors for use at the input,a minimum voltage rating of2×(maximum dc voltage+ac ripple)is highly recommended.This is standard practice to ensure reliability.Polymer-tantalum capacitors are not affected by this requirement.For improved ripple reduction on the input bus,additional ceramic capacitors can be used to complement the minimum requirement.For most applications only one(1)47-µF ceramic capacitor is required.The ceramic capacitor should be located within0.5in.(1,27cm)of the output pin.Adding a second47-µF nonceramic capacitor allows the module to meet its transient response specification.For applications with load transients(sudden changes in load current), the regulator response benefits from additional external output capacitance.A high-quality computer-grade electrolytic capacitor should be adequate.Electrolytic capacitors should be located close to the load circuit.These capacitors provide decoupling over the frequency range,2kHz to150kHz.Aluminum electrolytic capacitors are suitable for ambient temperatures above0°C.For operation below0°C,tantalum or Os-Con type capacitors are recommended.When using one or more nonceramic capacitors,the calculated equivalent ESR should be no lower than4mΩ(7mΩusing the manufacturer's maximum ESR for a single capacitor).A list of preferred low-ESR type capacitors are identified in Table3,the recommended capacitor table.Above150kHz the performance of aluminum electrolytic capacitors becomes less effective.To further improve the reflected input ripple current,or the output transient response,multilayer ceramic capacitors must be added. Ceramic capacitors have very low ESR and their resonant frequency is higher than the bandwidth of the regulator.When placed at the output their combined ESR is not critical as long as the total value of ceramic capacitance does not exceed200µF.Also,to prevent the formation of local resonances,do not place more than three identical ceramic capacitors with values of10µF or greater in parallel.Additional tantalum type capacitors can be used at both the input and output,and are recommended for applications where the ambient operating temperature can be less than0°C.The AVX TPS,Sprague 593D/594/595and Kemet T495/T510/T520capacitors series are suggested over many other tantalum types due to their rated surge,power dissipation,and ripple current capability.As a caution,many general-purpose tantalum capacitors have considerably higher ESR,reduced power dissipation,and lower ripple current capability.These capacitors are also less reliable as they have lower power dissipation and surge current ratings. Tantalum capacitors that do not have a stated ESR or surge current rating are not recommended for power applications.When specifying Os-Con and polymer tantalum capacitors for the output,the minimum ESR limit is encountered well before the maximum capacitance value is reached.The capacitor table,Table3,identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple current(rms)ratings.The recommended number of capacitors required at both the input and output buses is identified for each capacitor type.This is not an extensive capacitor list.Capacitors from other vendors are available with comparable specifications.Those listed are for guidance.The rms rating and ESR(at100kHz)are critical parameters necessary to insure both optimum regulator performance and long capacitor life.9Designing for Load TransientsPTH04070WSLTS227–SEPTEMBER 2004The transient response of the dc/dc converter has been characterized using a load transient with a di/dt of 1A/µs.The typical voltage deviation for this load transient is given in the data sheet specification table using the optional value of output capacitance.As the di/dt of a transient is increased,the response of a converter's regulation circuit ultimately depends on its output capacitor decoupling network.This is an inherent limitation with any dc/dc converter once the speed of the transient exceeds its bandwidth capability.If the target application specifies a higher di/dt or lower voltage deviation,the requirement can only be met with additional output capacitor decoupling.In these cases,special attention must be paid to the type,value,and ESR of the capacitors selected.If the transient performance requirements exceed those specified in the data sheet,the selection of output capacitors becomes more important.Review the minimum ESR in the characteristic data sheet for details on the capacitance maximum.Table 3.Recommended Input/Output CapacitorsCAPACITOR CHARACTERISTICSQUANTITY 85°C CAPACITOR VENDOR/EQUIVALENT VENDOR MAXIMUM PHYSICAL COMPONENT WORKING VALUE SERIES INPUT OUTPUT NUMBERRIPPLE SIZE SERIESVOLTAGE µF RESISTANCEBUS (1)BUS CURRENT (mm)(ESR)(I rms )Panasonic WA (SMT)10V 1200.035Ω2800mA 8×6.91≤4(1)EEFWA1A121P (2)FC (SMT)25V 470.400Ω230mA 8×6.211(1)EEVFC1E470P (2)Panasonic SL SP-cap(SMT) 6.3V 470.018Ω2500mA 7.3×4.31≤3EEFCD0J470R 6.3V 560.009Ω3000mA 7.3×4.31≤2EEFSL0J560R United Chemi-con PXA (SMT)10V 470.031Ω2250mA 6.3×5.711PXA10VC470MF60TP FS 10V 1000.040Ω2100mA 6.3×9.81≤510FS100MLXZ16V 1000.250Ω290mA 6.3×11.511LXZ16VB101M6X11LL MVZ (SMT)16V1000.440Ω230mA 6.3×5.711MVZ16VC101MF60TP Nichicon UWG (SMT)16V 1000.400Ω230mA 8×6.211UWG1C101MCR1GS F559(Tantalum)10V 1000.055Ω2000mA 7.7×4.31≤5F551A107MN PM10V 1000.550Ω210mA 6×1111UPM1A101MEH Sanyo Os-con\POS-Cap SVP 10V 680.025Ω2400mA 7.3×4.31≤510TPE68M (SMT) 6.3V 470.074Ω1110mA 5×61≤56SVP47M SP10V 560.045Ω1710mA 6.3×5.01≤510SP56MAVX Tantalum TPS (SMD)10V 470.100Ω1100mA 7.3L ×4.3W 1≤5TPSD476M010R010010V 470.060Ω>412mA ×4.1H 1≤5TPSB476M010R0500Kemet T520(SMD)10V 680.060Ω>1200mA 7.3L ×5.7W 1≤5T520V686M010ASE060AO-CAP6.3V 470.028Ω>1100mA ×4.0H 1≤3A700V476M006AT Vishay/Sprague 594D/595D 10V 680.100Ω>1000mA7.3L ×6.0W 1≤5594D686X0010C2T (SMD)10V 680.240Ω680mA ×4.1H1≤5595D686X0010C2T 94SL16V 470.070Ω1550mA 8×51≤594SL476X0016EBP TDK Ceramic X5R 6.3V 220.002Ω>1400mA 1210case ≥2(3)≤3C3225X5R0J226KT/MT Murata Ceramic X5R 6.3V 220.002Ω>1000mA 3225mm ≥2(3)≤3GRM32ER61J223M Kemet6.3V 220.002Ω>1000mA ≥2(3)≤3C1210C226K9PAC TDK Ceramic X5R 6.3V 470.002Ω>1400mA 1210case ≥1≤3C3225X5R0J476KT/MT Murata Ceramic X5R 6.3V 470.002Ω>1000mA 3225mm≥1≤3GRM32ER60J476M/6.3Kemet6.3V470.002Ω>1000mA≥1≤3C1210C476K9PAC(1)A ceramic capacitor is required on both the input and the output.An electrolytic capacitor can be added to the output for improved transient response.(2)An optional through-hole capacitor available.(3)A total capacitance of 44µF is an acceptable replacement for a single 47-µF capacitor.10Power-Up Characteristicst − 10 ms/divCurrent Limit ProtectionThermal ShutdownOutput On/Off InhibitPTH04070W SLTS227–SEPTEMBER2004When configured per the standard application,the PTH04070power module produces a regulated output voltage following the application of a valid input source voltage.During power up,internal soft-start circuitry slows the rate that the output voltage rises,thereby limiting the amount of in-rush current that can be drawn from the input source.The soft-start circuitry introduces a short time delay(typically10ms)into the power-up characteristic. This is from the point that a valid input source is recognized.Figure10shows the power-up waveforms for a PTH04070W,operating from a3-V input and with the output voltage adjusted to1.8V.The waveforms were measured with a2-A resistive load.Figure10.Power-Up WaveformsThe PTH04070modules protect against load faults with a continuous current limit characteristic.Under a load fault condition,the output current cannot exceed the current limit value.Attempting to draw current that exceeds the current limit value causes the output voltage to be progressively reduced.Current is continuously supplied to the fault until it is removed.Upon removal of the fault,the output voltage will promptly recover.Thermal shutdown protects the module internal circuitry against excessively high temperatures.A rise in temperature may be the result of a drop in airflow,a high ambient temperature,or a sustained current limit condition.If the junction temperature of the internal components exceeds150°C,the module shuts down.This reduces the output voltage to zero.The module will start up automatically,by initiating a soft-start power up when the sensed temperature decreases10°C below the thermal shutdown trip point.For applications requiring output voltage on/off control,the PTH04070power module incorporates an output on/off Inhibit control(pin5).The inhibit feature can be used wherever there is a requirement for the output voltage from the regulator to be turned off.The power module functions normally when the Inhibit pin is left open-circuit,providing a regulated output whenever a valid source voltage is connected to Vin with respect to GND.Figure11shows the typical application of the inhibit function.Note the discrete transistor(Q1).The Inhibit control has its own internal pullup to V I potential.An open-collector or open-drain device is recommended to control this input.t − 5 ms/divPTH04070WSLTS227–SEPTEMBER 2004Turning Q1on applies a low voltage to the Inhibit control pin and disables the output of the module.If Q1is then turned off,the module will execute a soft-start power-up sequence.A regulated output voltage is produced within 20msec.Figure 12shows the typical rise in the output voltage,following the turn off of Q1.The turn off of Q1corresponds to the fall in the waveform,Q1Vgs.The waveforms were measured with a 2-A resistive load.Figure 11.On/Off Inhibit Control CircuitFigure 12.Power Up Response From Inhibit ControlIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. 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Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. 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M50FLW040ANB1P中文资料

M50FLW040ANB1P中文资料

1/52PRELIMINARY DATAAugust 2004This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.M50FLW040A M50FLW040B4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors)3V Supply Firmware Hub / Low Pin Count Flash MemoryFEATURES SUMMARYsFLASH MEMORY–Compatible with either the LPC interfaceor the FWH interface (Intel Spec rev1.1) used in PC BIOS applications– 5 Signal Communication Interfacesupporting Read and Write Operations – 5 Additional General Purpose Inputs forplatform design flexibility–Synchronized with 33MHz PCI clock s8 BLOCKS OF 64 KBYTES – 5 blocks of 64 KBytes each– 3 blocks, subdivided into 16 uniformsectors of 4 KBytes eachTwo blocks at the top and one at the bottom (M50FLW040A)One block at the top and two at the bottom (M50FLW040B)sENHANCED SECURITY–Hardware Write Protect Pins for BlockProtection–Register-based Read and WriteProtectionsSUPPLY VOLTAGE–V CC = 3 to 3.6V for Program, Erase andRead Operations–V PP = 12V for Fast Program and Erase sTWO INTERFACES–Auto Detection of Firmware Hub (FWH) orLow Pin Count (LPC) Memory Cycles for Embedded Operation with PC Chipsets –Address/Address Multiplexed (A/A Mux)Interface for programming equipment compatibility.s PROGRAMMING TIME: 10µs typical sPROGRAM/ERASE CONTROLLER–Embedded Program and Erase algorithms –Status Register BitssPROGRAM/ERASE SUSPEND–Read other Blocks/Sectors duringProgram Suspend–Program other Blocks/Sectors duringErase SuspendsELECTRONIC SIGNATURE –Manufacturer Code: 20h–Device Code (M50FLW040A): 08h –Device Code (M50FLW040B): 28hM50FLW040A, M50FLW040BTABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2.Logic Diagram (FWH/LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 3. Logic Diagram (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 1.Signal Names (FWH/LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 2.Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 4.PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 5.TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 6.TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 3.Addresses (M50FLW040A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 4.Addresses (M50FLW040B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . .10 Input/Output Communications (FWH0/LAD0-FWH3/LAD3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Input Communication Frame (FWH4/LFRAME).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1010 CPU Reset (INIT).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Top Block Lock (TBL).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1011 Reserved for Future Use (RFU).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .11 Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Row/Column Address Select (RC).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 V CC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 V PP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 V SS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Table 5.Memory Identification Input Configuration (LPC mode). . . . . . . . . . . . . . . . . . . . . . . . . .12BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122/52M50FLW040A, M50FLW040BBus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 6.FWH Bus Read Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 7.FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 7.FWH Bus Write Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 8.FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 8.LPC Bus Read Field Definitions (1-Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 9.LPC Bus Read Waveforms (1-Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 9.LPC Bus Write Field Definitions (1 Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 10.LPC Bus Write Waveforms (1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 10.A/A Mux Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table mand Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Read Electronic Signature Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 12.Electronic Signature Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Quadruple Byte Program Command (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Double/Quadruple Byte Program Command (FWH Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table mands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Program/Erase Controller Status (Bit SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Erase Suspend Status (Bit SR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Erase Status (Bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Program Status (Bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 V PP Status (Bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Program Suspend Status (Bit SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..22 Block Protection Status (Bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Reserved (Bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233/52M50FLW040A, M50FLW040B4/52Table 14.Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS . . .24Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Read Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 15.Configuration Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 16.Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 17.General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register . . . . . . . . . . . . . .25 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 18.Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 19.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 20.Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 21.FWH/LPC Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 22.A/A Mux Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 11.FWH/LPC Interface AC Measurement I/O Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 12.A/A Mux Interface AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 23.Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 24.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 14.FWH/LPC Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 25.FWH/LPC Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figure 15.FWH/LPC Interface AC Signal Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Table 26.FWH/LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 16.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 27.Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Figure 17.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Table 28.A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Figure 18.A/A Mux Interface Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Table 29.A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Figure 19.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline. . . . . . . .36 Table 30.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data37 Figure 20.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . .38 Table 31.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . .38 Figure 21.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . .39M50FLW040A, M50FLW040B Table 32.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data .39PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 33.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Table 34.M50FLW040A Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 35.M50FLW040B Block and Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only). . . . .45 Figure 24.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . .46 Figure 25.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . .47 Figure 26.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . .48 Figure 27.Sector/Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Figure 28.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . .50REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 36.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .515/52M50FLW040A, M50FLW040B6/52SUMMARY DESCRIPTIONThe M50FLW040 is a 4 Mbit (512Kb x8) non-vola-tile memory that can be read, erased and repro-grammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines, an optional 12V power supply can be used to reduce the erasing and programming time.The memory is divided into 8 Uniform Blocks of 64KBytes each, three of which are divided into 16uniform sectors of 4KBytes each (see APPENDIX A. for details). All blocks and sectors can be erased independently. So, it is possible to pre-serve valid data while old data is erased. Blocks can be protected individually to prevent accidental program or erase commands from modifying their contents.Program and erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re-quired to update the memory contents. The end of a program or erase operation can be detected andany error conditions identified. The command set to control the memory is consistent with the JE-DEC standards.Two different bus interfaces are supported by the memory:s The primary interface, the FWH/LPCInterface, uses Intel ’s proprietary Firmware Hub (FWH) and Low Pin Count (LPC)protocol. This has been designed to remove the need for the ISA bus in current PCChipsets. The M50FLW040 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.s The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers, for production lineprogramming prior to fitting the device in a PC Motherboard.The memory is supplied with all the bits erased (set to ’1’).M50FLW040A, M50FLW040BNote: 1.ID3 is Reserved for Future Use (RFU) in LPC mode.Table 1. Signal Names (FWH/LPC Interface) Table 2. Signal Names (A/A Mux Interface) FWH0/LAD0-FWH3/LAD3Input/Output CommunicationsFWH4/LFRAMEInput Communication FrameID0-ID3Identification InputsGPI0-GPI4General Purpose InputsIC Interface ConfigurationRP Interface ResetINIT CPU ResetCLK ClockTBL Top Block LockWP Write ProtectRFUReserved for Future Use. LeavedisconnectedV CC Supply VoltageV PP Optional Supply Voltage for FastProgram and Erase OperationsV SS GroundNC Not Connected InternallyIC Interface ConfigurationA0-A10Address InputsDQ0-DQ7Data Inputs/OutputsG Output EnableW Write EnableRC Row/Column Address SelectRB Ready/Busy OutputRP Interface ResetV CC Supply VoltageV PPOptional Supply Voltage for FastProgram and Erase OperationsV SS GroundNC Not Connected Internally7/52M50FLW040A, M50FLW040B8/529/52M50FLW040A, M50FLW040BTable 3. Addresses (M50FLW040A)Table 4. Addresses (M50FLW040B)Note:Also see APPENDIX A., Table 34. and Table 35. for a full listing of the Block Addresses.BlockSize (KByte)Address Range Sector Size (KByte)6470000h-7FFFFh 16 x 4KBytes 6460000h-6FFFFh 16 x 4KBytes6450000h- 5FFFFh 5 x 64KBytes 6440000h- 4FFFFh 6430000h-3FFFFh 6420000h-2FFFFh 6410000h-1FFFFh 6400000h-0FFFFh16 x 4KBytes BlockSize (KByte)Address Range Sector Size (KByte)6470000h-7FFFFh 16 x 4KBytes6460000h- 6FFFFh 5 x 64KBytes 6450000h- 5FFFFh 6440000h- 4FFFFh 6430000h-3FFFFh 6420000h-2FFFFh 6410000h-1FFFFh 16 x 4KBytes 6400000h-0FFFFh16 x 4KBytesM50FLW040A, M50FLW040B10/52SIGNAL DESCRIPTIONSThere are two distinct bus interfaces available on this device. The active interface is selected before power-up, or during Reset, using the Interface Configuration Pin, IC.The signals for each interface are discussed in the Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions section and the Address/Address Multiplexed (A/A Mux) Signal Descriptions sec-tion, respectively, while the supply signals are dis-cussed in the Supply Signal Descriptions section.Firmware Hub/Low Pin Count (FWH/LPC) Signal DescriptionsPlease see Figure 2. and Table 1..Input/Output Communications (FWH0/LAD0-FWH3/LAD3).All Input and Output Communica-tions with the memory take place on these pins.Addresses and Data for Bus Read and Bus Write operations are encoded on these pins.Input Communication Frame (FWH4/LFRAME).The Input Communication Frame bus operation. When Input Communication Frame is Low, V IL , on the rising edge of the Clock, a new bus operation is initiated. If Input Communication Frame is Low, V IL , during a bus operation then the operation is aborted. When Input Communication Frame is High, V IH , the current bus operation is ei-ther proceeding or the bus is idle.Identification Inputs (ID0-ID3).Up to 16 memo-ries can be addressed on a bus, in the Firmware Hub (FWH) mode. The Identification Inputs allow each device to be given a unique 4-bit address. A ‘0’ is signified on a pin by driving it Low, V IL , or leaving it floating (since there is an internal pull-down resistor, with a value of R IL ). A ‘1’ is signified on a pin by driving it High, V IH (and there will be a leakage current of I LI2 through the pin).By convention, the boot memory must have ad-dress ‘0000’, and all additional memories are giv-en addresses, allocated sequentially, from ‘0001’.In the Low Pin Count (LPC) mode, the identifica-tion Inputs (ID0-ID2) can address up to 8 memo-ries on a bus. In the LPC mode, the ID3 pin is Reserved for Future Use (RFU). The value on ad-dress A19-A21 is compared to the hardware strap-ping on the ID0-ID2 pins to select the memory that is being addressed. For an address bit to be ‘1’,the corresponding ID pin can be left floating or driven Low, V IL (again, with the internal pull-down resistor, with a value of R IL ). For an address bit to be ‘0’, the corresponding ID pin must be driven High, V IH (and there will be a leakage current of I LI2 through the pin, as specified in Table 24.). For details, see Table 5..General Purpose Inputs (GPI0-GPI4).TheGeneral Purpose Inputs can be used as digital in-puts for the CPU to read, with their contents being available in the General Purpose Inputs Register.The pins must have stable data throughout the en-tire cycle that reads the General Purpose Input Register. These pins should be driven Low, V IL, or High, V IH , and must not be left floating.Interface Configuration (IC).The Interface Con-figuration input selects whether the FWH/LPC in-terface or the Address/Address Multiplexed (A/A Mux) Interface is used. The state of the Interface Configuration, IC, should not be changed during operation of the memory device, except for select-ing the desired interface in the period before pow-er-up or during a Reset.To select the FWH/LPC Interface, the Interface Configuration pin should be left to float or driven Low, V IL . To select the Address/Address Multi-plexed (A/A Mux) Interface, the pin should be driv-en High, V IH . An internal pull-down resistor is included with a value of R IL ; there will be a leakage current of I LI2 through each pin when pulled to V IH .Interface Reset (RP).The Interface Reset (RP)input is used to reset the device. When Interface IL , the memory is in Reset mode (the outputs go to high impedance,and the current consumption is minimized). When IH , the device is in normal op-eration. After exiting Reset mode, the memory en-ters Read mode.is used to Reset the device when the CPU is reset.It behaves identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical AND) of RP and INIT.Clock (CLK).The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0/LAD0-FWH3/LAD3.The Clock conforms to the PCI specification.The Top Block Lock in-put is used to prevent the Top Block (Block 7) from being changed. When Top Block Lock, TBL, is driven Low, V IL , program and erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock,TBL, is driven High, V IH , the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL, does not affect the protec-tion of the Main Blocks (Blocks 0 to 6). For details,see APPENDIX A..Top Block Lock, TBL, must be set prior to a pro-gram or erase operation being initiated, and must not be changed until the operation has completed,otherwise unpredictable results may occur. Simi-larly, unpredictable behavior is possible if WP is。

SUD50P04-09L_08中文资料

SUD50P04-09L_08中文资料

SUD50P04-09L_08中文资料Vishay SiliconixSUD50P04-09LP-Channel 40-V (D-S), 175 °C MOSFETFEATURESTrenchFET ? Power MOSFETS ?175 °C Junction Temperature PRODUCT SUMMARYV DS (V)r DS(on) (Ω)I D (A)d- 400.0094 at V GS = - 10 V - 500.0145 at V GS = - 4.5 V- 50Notes:a. Duty cycle ≤ 1 %.b. When Mounted on 1" square PCB (FR-4 material).c. See SOA curve for voltage derating.d. Package limited.* Pb containing terminations are not RoHS compliant, exemptions may apply. ABSOLUTE MAXIMUM RATINGS T A = 25°C, unless otherwise notedParameterSymbol Limit Unit Drain-Source Voltage V DS - 40VGate-Source VoltageV GS ± 20Continuous Drain Current (T J = 175 °C)T C = 25 °C I D - 50d AT C = 125 °C- 50d Pulsed Drain Current I DM - 100Avalanche Current I AS- 50Single Avalanche Energy a L = 0.1 mH E AS 125mJ Power DissipationT C = 25 °C P D 136c W T A = 25 °C 3b, c Operating Junction and Storage T emperature RangeT J , T stg- 55 to 175°C T HERMAL RESISTANCE RATINGSParameterSymbol Typical MaximumUnitJunction-to-Ambient b t ≤ 10 sec R thJA 1518°C/W Steady State4050Junction-to-CaseR thJC0.821.1Vishay SiliconixSUD50P04-09LNotes:a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.c. Independent of operating temperature.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in theoperational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATION S T J = 25°C, unless otherwise notedParameter Symbol Test Conditions Min T yp Max UnitStaticDrain-Source Breakdown Voltage V (BR)DSS V GS = 0 V , I D = - 250 μA - 40V Gate Threshold Voltage V GS(th) V DS = V GS , I D = - 250 μA - 1- 3Gate-Body LeakageI GSS V DS = 0 V, V GS = ± 20 V ± 100nAZero Gate Voltage Drain Current I DSS V DS = - 32 V , V GS = 0 V - 1μA V DS = - 32 V , V GS = 0 V , T J = 125 °C - 50V DS = - 32 V , V GS = 0 V , T J = 175 °C- 150On-State Drain Current aI D(on)V DS = - 5 V , V GS = - 10 V - 50A Drain-Source On-State Resistance ar DS(on)V GS = - 10 V, I D = - 24 A0.00750.0094ΩV GS = - 10 V, I D = - 50 A, T J = 125 °C 0.014V GS = - 10 V, ID = - 50 A, T J = 175 °C0.017V GS = - 4.5 V , I D = - 18 A0.01150.0145Forward T ransconductance a g fsV DS = - 5 V , I D = - 24 A73S Dynamic bInput Capacitance C iss V GS = 0 V , V DS = - 25 V , f = 1 MHz 4800pFOutput CapacitanceC oss 700Reverse Transfer Capacitance C rss 550Total Gate Charge c Q g V DS = - 20 V , V GS = - 10 V, ID = - 50 A 102150nC Gate-Source Charge c Q gs 18.5Gate-Drain Charge c Q gd 27Turn-On Delay Time c t d(on) V DD = - 20 V , R L = 0.4 ΩI D ? - 50 A, V GEN = - 10 V , R G = 6 Ω1015nsRise Time ct r 6090Turn-Off Delay Time c t d(off)145220Fall Time ct f140220Source-Drain Diode Ratings and Characteristics (T C = 25°C)b Continuous CurrentI S - 50A Pulsed Current I SM - 100Forward Voltage a V SD I F = - 50 A, V GS = 0 V - 1.0- 1.5V Reverse Recovery Timet rrI F = - 50 A, di/dt = 100 A/μs5585nsVishay SiliconixSUD50P04-09LOutput Characteristics TransconductanceTransfer CharacteristicsGate ChargeVishay SiliconixSUD50P04-09LTHERMAL RATINGSVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?72243.Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。

WTH040语音芯片使用资料

WTH040语音芯片使用资料

WTH040语音芯片使用资料V2.11、产品特点可编程一次性烧录（OTP）语音芯片；语音长度可达40秒（6KHz采样率）；PWM和DAC两种音频输出方式；内部集成时钟振荡器；最大可存放700个语音文件；一线最多可加载63段地址的语音，二线最多可以加载255段语音；具有按键控制模式、一线串口控制模式以及两线串口控制模式等；触发防抖时间：50us（串口）和10ms（按键）；7种按键触发方式；支持播放不同采样率的语音文件；支持BUSY状态输出功能；工作电压：DC2.4～5.0V。

(需根据供电电压设定芯片为3V或5V，后续有详解)2、芯片选型选型注意：1.芯片的供电电压、控制方式和输出方式在烧写程序时已经设定好，不可以再次更改，订做芯片时需要和业务员说明应用要求。

2.使用一线串口控制方式时，小于等于32段语音和大于32段语音的芯片IO接口不一样，详细请查看相应的应用电路。

3.WTH040芯片与WTH080芯片的管脚不兼容。

芯片电压的设定决定了内部LDO的打开和关闭。

注意芯片电压设定需和供电电压及电路接线必须匹配，否则会导致芯片损坏或不工作。

下文有相应的参考电路。

芯片控制方式有：按键控制、一线串口、两线串口。

芯片输出方式有：PWM输出(直接推动喇叭)、DAC输出(外接功放使用)。

下文有相应的参考电路。

3、应用范围汽车（防盗报警器、倒车雷达、GPS导航仪、电子狗、中控锁）；智能家居系统；家庭防盗报警器；医疗器械人声提示；家电（电磁炉、电饭煲、微波炉）；娱乐设备（游戏机、游乐机）；学习模型（早教机、儿童有声读物）； 智能交通设备（收费站、停车场）； 通信设备（电话交换机、电话机）； 工业控制领域（电梯、工业设备）；高级玩具。

4、管脚图4.1、WTH040-8S/WTH040-8P4.2、WTH040-16S5、电气参数6、控制模式6.1、按键控制在按键控制模式下，任意控制端均可设置为脉冲可重复、脉冲不可重复、脉冲保持、脉冲不保持、电平保持可循环、电平保持不可循环、下一曲可循环等7种触发方式。