calibre LVS Option
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LVS SOFT SUBSTRATE PINS {NO | YES} LVS Filter Unused Option { B D E O } LVS Filter Unused Option {AB RC RE RG} LVS Filter Unused Bipolar { YES | NO } LVS Globals Are Ports {NO | YES} TEXT PRINT MAXIMUM {ALL | NUMBER} LVS Property Resolution Maximum {number | All}
Correct X V V X V Pin_NAME1 Pin_NAME2 Pin_NAME3 Note VDDA VCI: VDDA: VCI: VCI: VDDA: VCI: VDDA:EFG VCI VCI VDDA:ABC VCI:ABC VCI:ABC
二個都是VDDA，但是是各自獨立 的VDDA
LVS RECOGNIZE GATE
LVS RECOGNIZE GATE 決定是否要從電晶體辨認出邏輯閘
ALL Specifies that all gates are recognized. 全部分辨 SIMPLE Specifies that simple gates are recognized. 分辨簡單的邏輯定義 NONE Specifies that no gates are recognized. 不分辨邏輯閘 (類比電路使用) LVS REDUCE SPLIT GATES YES LVS to reduce split gates. 允許gate可以分開 NO LVS not to reduce split gates. 不允許gate分開
LVS Softchk Pwell_all contact Trace Property C1 C2 C3 trace_val
OPTION {紅色是建議值，底線是預設值}
precision 1000 //預設精密(度)為1000 resolution 10 // layout grid size 0.01um(10/1000) ，如果沒有設這行，預設值 是database unit。 LAYOUT PATH "***" // layout database路徑 LAYOUT PRIMARY "PA6368A1" // layout database top cell SOURCE PRIMARY "PA6368_TOP" // netlist 路徑 SOURCE PATH "**" //與layout database top cell相對等的netlist top cell UNIT LENGTH u // 定義尺寸,距離的單位 u=1e-6 m ，預設值為u (u、mil、 mm、cm、inch、m) UNIT CAPACITANCE fF // 定義電容的單位 f=1e-15，F=法拉，預設值為(aF、 fF、pF、nF、uF、mF、F、kF、megF、gF、tF) UNIT RESISTANCE OHM //定義電阻的單位，預設值為ohm=1 (ohm、aohm、 fohm、pohm、nohm、uohm、mohm、kohm、megohm、gohm、tohm) layout system gdsii // layout database 儲存格式 source system spice // netlsit 格式 erc results database “erc.db” ascii //記錄結果的資料以ascii碼儲存 LVS REPORT “lvs.rep“ //lvs report 的檔名
.when
PORT DEPTH ALL时,lvs有错
Missing port
Lvs. rep
TEXT DEPTH ALL | PRIMARY |number
.when
option set PRIMARY, only text objects from the top-level cell are selected. （只識別top層cell的texts) option set ALL, text objects from throughout the hierarchy are used as top-level text. （識別所有層cell的 texts)
LVS ABORT ON SUPPLY ERROR {YES | NO} NO
Define 為No 在執lvs時即 使有short ,也會等整個驗證完 畢後才會跳出
YES 在執lvs時一有short 馬上停 止後續驗證並寫report告知哪 些電位short(lvs.report.short)
LVS ALL CAPACITOR PINS SWAPPABLE {NO | YES} YES NO 宣告所有電容器的pin腳可互換 宣告所有電容器的pin腳能夠互換
LAYOUT CASE
YES
Layout device type是由 lvs command file決定的
決定device的layer都改 為大寫后，lvs correct
LAYOUT DEPTH ALL | PRIMARY
.when option set , shapes are read from the top-level cell to the bottom of the hierarchy.（可識別底層到頂層的所有圖） .when option set only.（只識別top層的圖）
OPTION {紅色是建議值，底線是預設值}
MASK SVDB DIRECTORY “svdb” QUERY XRC // lvs report格式如 此才可以使用RVE看lvs report ；XRC for rc extraction LVS POWER NAME "VGH" "VCC" "VDDD" "VDDA" //定義layout power name LVS GROUND NAME "VGL" "VSSD" "VSS" "VSSA" //定義layout ground name LVS SPICE PREFER PINS NO //決定subcircuit的pin name 是否凌 駕於global LVS REDUCE PARALLEL BIPOLAR YES //把所有並聯的bipolar加 在一起 LVS REPORT MAXIMUM ALL // show出所有lvs error report
LVS BOX
LVS BOX LAYOUT CELL_NAME LVS BOX SOURCE CELL_NAME 當二個人以以上合作時，在TOP CELL需要MAPPING 另一個還未完 成的CELL時，可讓command file 設定為這個CELL已經OK，忽略這 個CELL的錯誤。
LVS COMPARE CASE NO / YES LVS COMPARE CASE: 設定是否開啓大小寫的比較
Standard Verification Rule Manual
Calibre LVS Option
2007/01
By :python
OPTION目錄
一般設定 LVS CHECK PORT NAMES {YES | NO} LVS RECOGNIZE GATE {ALL | SIMPLE | NONE} LVS REDUCE SPLIT GATES {YES/NO} LVS ABORT ON SUPPLY ERROR {YES | NO} LVS ALL CAPACITOR PINS SWAPPABLE {NO | YES} LVS CHECK PORT NAMES {NO | YES} VIRTUAL CONNECT COLON {NO|YES} LVS BOX LVS COMPARE CASE {NO / YES} LAYOUT DEPTH { ALL | PRIMARY} PORT DEPTH {ALL | PRIMARY |number} TEXT DEPTH {ALL | PRIMARY |number } LVS ABORT ON SOFTCHK {NO |YES} LVS REPORT OPTION V S A AV B C D F G P R RA
均視為VCI 均視為VDDA
VCI:和VCI:ABC視為同一個VCI， 但是和另一個VCI是不同net If pin_name3&pin_name2打在同 一net上，會視為接在VCI
VIRTUAL CONNECT NAME PIN_NAME 當上面表格Incorrect 的選項，在這個功能開啟下會認為Correct。 當有二個以上同名PIN_NAME時會認為接在一起。
ALL
PRIMARY, shapes are read from the top-level cell
當LAYOUT DEPTH 設為PRIMARY時
Lvs.rep Nothing in layout
NOT COMPARED
PORT DEPTH ALL | PRIMARY |number
Used only in Calibre LVS/LVS-H option set PRIMARY, the tool to use freestanding port objects from only the top-level cell. （只識 別top層cell的ports) . when option set ALL, the tool to use free-standing port objects from throughout the hierarchy. （識別所有層 cell的ports) when option set number, from number levels below the top-level cell. Specifying zero is equivalent to PRIMARY. （可識別所設定的層到top層的所有ports,若 number設為0時，即top層）
