![16位音频编解码芯片[ES689]开发手册](https://imgs-1438308264.cos.ap-hongkong.myqcloud.com/62c7872e453610661ed9f4e3.webp)
上海海栎创微电子有限公司CST816S数据手册高性能自电容触控芯片Rev：V1.2 概述CST816S自电容触控芯片，采用高速MCU内核并内嵌DSP电路，结合自身的快速自电容感应技术，可广泛支持三角形在内的多种自电容图案，在其上实现单点手势和真实两点操作，实现极高灵敏度和极低待机功耗。
芯片特点◆内置快速自电容检测电路及高性能DSP模块✧支持在线编程；✧内置看门狗；✧多个按键支持；✧支持待机手势唤醒功能；◆电容屏支持✧最多支持13个感应通道；✧通道悬空/下拉设计支持；✧模组参数自动调校；◆性能指标✧刷新率>100Hz；✧单点手势和真实两点操作；✧动态模式下典型功耗<2.5mA；✧待机模式下典型功耗<10uA；✧休眠模式下典型功耗<5uA;◆通讯接口✧I2C主/从通讯接口，速率10Khz~400Khz可配置；✧兼容1.8V/3.3V接口电平。
◆电源供电✧单电源供电2.7V~3.6V，电源纹波<=50mv；◆封装类型：QFN203mm*3mm*0.4mm；1.CMOD0/CMOD1必须接稳压电容，大小在1nF~5.6nF;功能描述CST816S自电容触控芯片，通过其内置的快速自电容感应模块，可无需任何外接器件(电路旁路电容除外)，即可在三角形等图案上实现单点手势和真实两点功能；在实现快速反应的同时，具有极其优异的抗噪、防水、低功耗表现。
工作模式动态模式当频繁有触摸操作时，处于此模式；在此模式下，触控芯片快速对触摸屏进行自电容扫描，以及时检测触摸并上报给主机。
在没有触摸2S后，自动进入待机模式。
自动进入待机模式的功能可以通过寄存器进行控制。
待机模式在此模式下，触控芯片以较低频率对触摸屏进行扫描，检测到手指触摸后进入动态模式，同时通过IRQ 引脚唤醒主机；也可通过复位引脚切换到动态模式。
休眠模式当接收到睡眠命令后，处于此模式；在此模式下，触控芯片处于深度睡眠状态，以最大限度节省功耗，可通过复位引脚切换到动态模式。
![Intel 16位单片机[87C196_MD]应用手册](https://imgs-1438308264.cos.ap-hongkong.myqcloud.com/3edad027a5e9856a561260e0.webp)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.©INTEL CORPORATION, 2004 August 2004 Order Number:272543-0038XC196MH INDUSTRIAL MOTOR CONTROLCHMOS MICROCONTROLLERThe 8XC196MH is a member of Intel’s family of 16-bit MCS ® 96 microcontrollers. It is designed primarily to control three-phase AC induction and DC brushless motors. It features an enhanced three-phase waveform generator specifically designed for use in “inverter” motor-control applications. This peripheral provides pulse-width modulation and three-phase sine wave generation with minimal CPU intervention. It generates three complementary non-overlapping PWM pulses with resolutions of 0.125 µs (edge triggered) or 0.250 µs (centered).The 8XC196MH has two dedicated serial port peripherals, allowing less software overhead. The watchdog timer can be programmed with one of four time options.The 8XC196MH is available as the 80C196MH, which does not have on-chip ROM, the 87C196MH,which contains 32 Kbytes of on-chip OTPROM* or factory programmed ROM, and the 83C196MH, whichcontains 32 Kbytes of factory programmed MASK ROM. It is available in 84-lead PLCC, 80-lead Shrink EIAJ/QFP,and 64-lead SDIP. The 64-lead package does not contain pins for the P5.1/INST and P6.7/PWM1 signals.Operational characteristics are guaranteed over the temperature range of – 40°C to +85°C .*One-Time Programmable Read-Only Memory (OTPROM) is similar to EPROM but comes in an unwindowed package and cannot be erased. It is user programmable.■High Performance CHMOS 16-bit CPU ■16MHz Operating Frequency ■32Kbytes of On-chip OTPROM/ROM ■744Bytes of On-chip Register RAM ■Register-to-register Architecture ■16Prioritized Interrupt Sources■Peripheral Transaction Server (PTS)with 15Prioritized Sources ■Up to 52I/O Lines■3-phase Complementary Waveform Generator ■8-channel 8-or 10-bit A/D with Sample and Hold ■2-channel UART■Event Processor Array (EPA)with 2 High-speed Capture/Compare Modules and 4 High-speed Compare-only Modules ■Two Programmable 16-bit Timers with Quadrature Counting Inputs ■Two Pulse-width Modulator (PWM)Outputs with High Drive Capability ■Flexible 8- or 16-bit External Bus ■ 1.75µs 16× 16 Multiply ■3µs 32/16Divide■Extended Temperature Available ■Idle and Powerdown Modes ■Watchdog Timer8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER2Figure 1. 8XC196MH Block Diagram8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER3PROCESS INFORMATIONThis device is manufactured on PX29.5, a CHMOS IV process. Additional process and reliability information is available in Intel’s Components Quality and Reliability Handbook (order number 210997).All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions andthe application. The Intel Packaging Handbook (order number 240800) describes Intel’s thermal impedance test methodology.Table 1. Thermal Characteristics Package Type θJA θJC 84-lead PLCC 33°C/W 11°C/W 80-lead QFP 56°C/W 12°C/W 64-lead SDIP56°C/WN/AFigure 2. The 8XC196MH Family NomenclatureTo address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".NOTE:8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER4Table 2. 8XC196MH Memory MapAddress(1)Description Notes0FFFFH0A000HExternal Memory09FFFH02080HInternal ROM/OTPROM or External Memory0207FH0205EHReserved1, 2 0205DH02040HPTS Vectors0203FH02030HInterrupt Vectors (upper)0202FH02020HROM/OTPROM Security Key0201FH0201CHReserved1, 2 0201BH Reserved (must contain 20H)0201AH CCB102019H Reserved (must contain 20H)02018H CCB002017H02014HReserved02013H02000HInterrupt Vectors (lower)01FFFH01F00HInternal SFRs1 1EFFH300HExternal Memory2FFH18HRegister RAM3 17H00HCPU SFRs1 NOTES:1.Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.2.WARNING: The contents and/or function of reserved locations may change with future revisions of thedevice.3.Code executed in locations 0000H to 02FFH will be forced external.8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER5Table 3. Signals Arranged by Functional CategoriesAddress & Data Programming Control Input/Output Input/Output (Cont’d)AD15:0AINC#P0.0/ACH0P2.5/COMP1CPVER P0.1/ACH1P2.6/COMP2Bus Control & Status PACT#P0.2/ACH2P2.7/SCLK1#/BCLK1ALE/ADV#PALE#P0.3/ACH3P3.7:0BHE#/WRH#PBUS15:0P0.4/ACH4P4.7:0BUSWIDTH PMODE.3:0P0.5/ACH5P5.7:0INST PROG#P0.6/ACH6/T1CLK P6.0/WG1#READY PVERP0.7/ACH7/T1DIR P6.1/WG1RD#P1.0/TXD0P6.2/WG2#WR#/WRL#Processor Control P1.1/RXD0P6.3/WG2EA#P1.2/TXD1P6.4/WG3#Power & Ground EXTINT P1.3/RXD1P6.5/WG3ANGND NMI P2.0/EPA0P6.6/PWM0V CC ONCE#P2.1/SCLK0#/BCLK0P6.7/PWM1V PP RESET#P2.2/EPA1V REF XTAL1P2.3/COMP3V SS XTAL2P2.4/COMP0NOTE:The following signals are not available in the 64-pin package: P5.1, P6.7, INST, and PWM1.8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER6Figure 3. 8XC196MH 64-lead Shrink DIP (SDIP) Package8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER 7Table 4. 64-lead Shrink DIP (SDIP) Pin AssignmentPin Name Pin Name Pin Name Pin Name 1V SS17P3.7/AD7/PBUS.733P6.2/WG2#49P0.0/ACH02P5.0/ALE/ADV#18P3.6/AD6/PBUS.634P6.1/WG150P2.0/EPA0/PVER 3V PP19P3.5/AD5/PBUS.535P6.0/WG1#51P2.1/SCLK0#/BCLK0/PALE#4P5.3/RD#20P3.4/AD4/PBUS.436P1.3/RXD152P2.2/EPA1/PROG#5P5.5/BHE#/WRH#21P3.3/AD3/PBUS.337P1.2/TXD153P2.3/COMP36P5.2/WR#/WRL#22P3.2/AD2/PBUS.238P1.1/RXD054P2.4/COMP0/AINC#7P5.7/BUSWIDTH 23P3.1/AD1/PBUS.139P1.0/TXD055P2.5/COMP1/PACT#8P4.6/AD14/PBUS.1424P3.0/AD0/PBUS.040P0.7/ACH7/T1DIR /PMODE.356P2.6/COMP2/CPVER 9P4.5/AD13/PBUS.1325RESET#41P0.6/ACH6/T1CLK/PMODE.257P2.7/SCLK1#/BCLK110P4.7/AD15/PBUS.1526NMI 42ANGND 58P6.6/PWM011V CC27EA#43V REF59XTAL212P4.4/AD12/PBUS.1228V SS 44P0.5/ACH5/PMODE.160XTAL113P4.3/AD11/PBUS.1129V CC45P0.4/ACH4/PMODE.061V SS14P4.2/AD10/PBUS.1030P6.5/WG346P0.3/ACH362 EXTINT 15P4.1/AD9/PBUS.9 31P6.4/WG3#47P0.2/ACH263P5.4/ONCE#16P4.0/AD8/PBUS.832P6.3/WG248P0.1/ACH164P5.6/READY8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER8Figure 4. 8XC196MH 84-lead PLCC Package8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER 9Table 5. 84-lead PLCC Pin AssignmentPin Name Pin Name Pin Name Pin Name 1P5.4/ONCE#22NC 43V SS64P2.0/EPA0/PVER 2P5.6/READY 23NC44P6.2/WG2#65P2.1/SCLK0#/BCLK0/PALE#3P5.1/INST 24P3.7/AD7/PBUS.745P6.1/WG166NC 4V SS25P3.6/AD6/PBUS.646P6.0/WG1#67NC 5P5.0/ALE/ADV#26P3.5/AD5/PBUS.547P1.3/RXD168P2.2/EPA1/PROG#6V PP27P3.4/AD4/PBUS.448P1.2/TXD169P2.3/COMP37P5.3/RD#28P3.3/AD3/PBUS.349NC 70P2.7/SCLK1#/BCLK18P5.5/BHE#/WRH#29P3.2/AD2/PBUS.250NC 71NC 9NC30P3.1/AD1/PBUS.151P1.1/RXD072NC10P5.2/WR#/WRL#31P3.0/AD0/PBUS.052P1.0/TXD073P2.4/COMP0/AINC#11P5.7/BUSWIDTH 32NC 53P0.7/ACH7/T1DIR/PMODE.374P2.5/COMP1/PACT#12P4.7/AD15/PBUS.1533RESET#54P0.6/ACH6/T1CLK/PMODE.275P2.6/COMP2/CPVER 13P4.6/AD14/PBUS.1434NMI 55ANGND 76P6.7/PWM114V CC35NC 56V REF77P6.6/PWM015P4.5/AD13/PBUS.1336EA#57P0.5/ACH5/PMODE.178NC 16NC 37V SS 58P0.4/ACH4/PMODE.079NC 17P4.4/AD12/PBUS.1238NC 59P0.3/ACH380NC 18P4.3/AD11/PBUS.1139V CC60P0.2/ACH281XTAL219P4.2/AD10/PBUS.1040P6.5/WG361P0.1/ACH182XTAL120P4.1/AD9/PBUS.941P6.4/WG3#62P0.0/ACH083V SS 21P4.0/AD8/PBUS.842P6.3/WG263NC84EXTINT8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER10Figure 5. 8XC196MH 80-lead Shrink EIAJ/QFP PackageTable 6. 80-lead Shrink EIAJ/QFP Pin AssignmentPin Name Pin Name Pin Name Pin Name1P5.2/WR#/WRL#21NC41P0.7/ACH7/T1DIR/PMODE.361P2.4/COMP0/AINC#2P5.7/BUSWIDTH22RESET#42P0.6/ACH6/T1CLK/PMODE.262P2.5/COMP1/PACT#3P4.7/AD15/PBUS.1523NMI43ANGND63P2.6/COMP2/CPVER4P4.6/AD14/PBUS.1424EA#44VREF64P6.7/PWM15VCC 25VSS45P0.5/ACH5/PMODE.165P6.6/PWM06P4.5/AD13/PBUS.1326NC46P0.4/ACH4/PMODE.066NC7NC27VCC47P0.3/ACH367NC8P4.4/AD12/PBUS.1228P6.5/WG348P0.2/ACH268NC9P4.3/AD11/PBUS.1129P6.4/WG3#49P0.1/ACH169XTAL210P4.2/AD10/PBUS.1030P6.3/WG250P0.0/ACH070XTAL111P4.1/AD9/PBUS.931VSS 51NC71VSS12P4.0/AD8/PBUS.832P6.2/WG2#52P2.0/EPA0/PVER72EXTINT13P3.7/AD7/PBUS.733P6.1/WG153P2.1/SCLK0#/BCLK0/PALE#73P5.4/ONCE# 14P3.6/AD6/PBUS.634P6.0/WG1#54NC74P5.6/READY 15P3.5/AD5/PBUS.535P1.3/RXD155NC75P5.1/INST16P3.4/AD4/PBUS.436P1.2/TXD156P2.2/EPA1/PROG#76VSS17P3.3/AD3/PBUS.337NC57P2.3/COMP377P5.0/ALE/ADV#18P3.2/AD2/PBUS.238NC58P2.7/SCLK1#/BCLK178VPP19P3.1/AD1/PBUS.139P1.1/RXD059NC79P5.3/RD#20P3.0/AD0/PBUS.040P1.0/TXD060NC80P5.5/BHE#/WRH#PIN DESCRIPTIONSTable 7. Signal DescriptionsSignal Name Type DescriptionMultiplexedWithACH7 ACH6 ACH5 ACH4 ACH3:0I Analog Channels. These pins are analog inputs to the A/Dconverter.These pins are multiplexed with the port 0 pins. While it ispossible for the pins to function simultaneously as analog anddigital inputs, this is not recommended because reading theport while a conversion is in process can produce unreliableconversion results.The ANGND and VREFpins must be connected for the A/Dconverter and the multiplexed port pins to function.P0.7/T1DIR/PMODE.3P0.6/T1CLK/PMODE.2P0.5/PMODE.1P0.4/PMODE.0P0.3:0AD15:8 AD7:0I/O Address/Data Lines. These pins provide a multiplexedaddress and data bus. During the address phase of the buscycle, address bits 0–15 are presented on the bus and canbe latched using ALE or ADV#. During the data phase, 8- or16-bit data is transferred.P4.7:0/PBUS.15:8P3.7:0/PBUS.7:0ADV#O Address Valid. This active-low output signal is asserted onlyduring external memory accesses.ADV# indicates that valid address information is available onthe system address/data bus. The signal remains low while avalid bus cycle is in progress and is returned high as soon asthe bus cycle completes.An external latch can use the ADV# signal to demultiplex theaddress from the address/data bus. Used with a decoder,ADV# can generate chip-selects for external memory.P5.0/ALEAINC#I Auto Increment. In slave programming mode, this active-lowinput signal enables the autoincrement mode. Auto incrementallows reading from or writing to sequential OTPROMlocations without requiring address transactions across theprogramming bus for each read or write.P2.4/COMP0ALE O Address Latch Enable. This active-high output signal isasserted only during external memory cycles.ALE signals the start of an external bus cycle and indicatesthat valid address information is available on the systemaddress/data bus. ALE differs from ADV# in that it is notreturned high until a new bus cycle is to begin.An external latch can use ALE to demultiplex the addressfrom the address/data bus.P5.0/ADV#ANGND GND Analog Ground. Reference ground for the A/D converterand the logic used to read port 0. ANGND must be held atnominally the same potential as VSS .—BCLK1 BCLK0I Serial Communications Baud Clock 0 and 1. BCLK0 and 1are alternate clock sources for the serial ports. The maximuminput frequency is FOSC/4.P2.7/SCLK1#P2.1/SCLK0#/PALE#BHE#O Byte High Enable. During 16-bit bus cycles, this active-lowoutput signal is asserted for word reads and writes and forhigh-byte reads and writes to external memory. BHE#indicates that valid data is being transferred over the upperhalf of the system address/data bus.BHE#, in conjunction with A0, selects the memory byte to beaccessed:BHE#A0Byte(s) Accessed00both bytes01high byte only10low byte onlyP5.5/WRH#BUSWIDTH I Bus Width. When enabled in the chip configuration register,this active-high input signal dynamically selects the bus widthof the bus cycle in progress. When BUSWIDTH is high, a 16-bit bus cycle occurs; when BUSWIDTH is low, an 8-bit buscycle occurs. BUSWIDTH is active during a CCR fetch.P5.7COMP3 COMP2 COMP1 COMP0O Event Processor Array (EPA) Compare Pins. Thesesignals are the output of the EPA compare modules. Thesepins are multiplexed with other signals and may beconfigured as standard I/O.P2.3P2.6/CPVERP2.5/PACT#P2.4/AINC#CPVER O Cumulative Program Verification. This active-high outputsignal indicates whether any verify errors have occurredsince the device entered programming mode. CPVERremains high until a verify error occurs, at which time it isdriven low. Once an error occurs, CPVER remains low untilthe device exits programming mode. When high, CPVERindicates that all locations have programmed correctly sincethe device entered programming mode.P2.6/COMP2EA#I External Access. This active-low input signal directsmemory accesses to on-chip or off-chip memory. If EA# islow, the memory access is off-chip. If EA# is high and thememory address is within 2000H–2FFFH, the access is toon-chip ROM or OTPROM. Otherwise, an access with EA#high is to off-chip memory.EA# is sampled only on the rising edge of RESET#.If EA# = VEA on the rising edge of RESET#, the device entersthe programming mode selected by PMODE.3:0.For devices without ROM, EA# must be tied low.—EPA1 EPA0I/O Event Processor Array (EPA) Input/Output pins. Theseare the high-speed input/output pins for the EPAcapture/compare modules. These pins are multiplexed withother signals and may be configured as standard I/O.P2.2/PROG#P2.0/PVER Table 7. Signal Descriptions (Continued)Signal Name Type DescriptionMultiplexedWithEXTINT I External Interrupt. This programmable interrupt is controlledby the WG_PROTECT register. This register controlswhether the interrupt is edge triggered or sampled andwhether a rising edge/high level or falling edge/low levelactivates the interrupt. This interrupt vectors through memorylocation 203CH. If the chip is in idle mode and if EXTINT isenabled, a valid EXTINT interrupt brings the chip back tonormal operation, where the first action is to execute theEXTINT service routine. After completion of the serviceroutine, execution resumes at the instruction following theone that put the chip into idle mode.In powerdown mode, a valid EXTINT interrupt causes thechip to return to normal operating mode. If EXTINT isenabled, the EXTINT service routine is executed. Otherwise,execution continues at the instruction following the IDLPDinstruction that put the chip into powerdown mode.—INST O Instruction Fetch. This active-high output signal is valid onlyduring external memory bus cycles. When high, INSTindicates that an instruction is being fetched from externalmemory. The signal remains high during the entire bus cycleof an external instruction fetch. INST is low for dataaccesses, including interrupt vector fetches and chip configu-ration byte reads. INST is low during internal memoryfetches.P5.1NMI I Nonmaskable Interrupt. In normal operating mode, a risingedge on NMI causes a vector through the NMI interrupt atlocation 203EH. NMI must be asserted for greater than onestate time to guarantee that it is recognized.In idle mode, a rising edge on NMI brings the chip back tonormal operation, where the first action is to execute the NMIservice routine. After completion of the service routine,execution resumes at the instruction following the one thatput the chip into idle mode.In powerdown mode, NMI causes a return to normaloperating mode only if it is tied to EXTINT.—ONCE#I On-circuit Emulation. Holding this pin low while theRESET# signal transitions from a low to a high places thedevice into on-circuit emulation (ONCE) mode. ONCE modeisolates the device from other components in the system toallow the use of a clip-on emulator for system debugging.This mode puts all pins except XTAL1 and XTAL2 into a high-impedance state. To exit ONCE mode, reset the device bypulling the RESET# signal low. P5.4Table 7. Signal Descriptions (Continued)Signal Name Type DescriptionMultiplexedWithP0.7 P0.6 P0.5 P0.4 P0.3:0I Port 0. This is a high-impedance, input-only port. Port 0 pinsshould not be left floating.These pins may individually be used as analog inputs(ACH x) or digital inputs (P0.x). While it is possible for the pinsto function simultaneously as analog and digital inputs, this isnot recommended because reading port 0 while a conversionis in process can produce unreliable conversion results.ANGND and VREFmust be connected for port 0 and the A/Dconverter to function.ACH7/T1DIR/PMODE.3ACH6/T1CLK/PMODE.2ACH5/PMODE.1ACH4/PMODE.0ACH3:0P1.3 P1.2 P1.1 P1.0I Port 1. This is a 4-bit, bidirectional, standard I/O port that ismultiplexed with individually selectable special-functionsignals. (Used as PBUS.15:12 in Auto-programming Mode.)RXD1TXD1RXD0TXD0P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0I/O Port 2. This is an 8-bit, bidirectional, standard I/O port that ismultiplexed with individually selectable special-functionsignals. P2.6 is multiplexed with a special test mode function.To prevent accidental entry into test modes, always configureP2.6 as an output.SCLK1#/BCLK1COMP2/CPVERCOMP1/PACT#COMP0/AINC#COMP3EPA1/PROG#SCLK0#/BCLK0/PALE#EPA0/PVERP3.7:0I/O Port 3. This is an 8-bit, bidirectional, memory-mapped I/Oport with open-drain outputs. The pins are shared with themultiplexed address/data bus, which has complementarydrivers.In programming modes, port 3 serves as the low byte of theprogramming bus (PBUS).AD7:0/PBUS.7:0P4.7:0I/O Port 4. This is an 8-bit, bidirectional, memory-mapped I/Oport with open-drain outputs. The pins are shared with themultiplexed address/data bus, which has complementarydrivers.In programming modes, port 4 serves as the high byte of theprogramming bus (PBUS).AD15:8/PBUS.15:8P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0I/O Port 5. This is an 8-bit, bidirectional, standard I/O port that ismultiplexed with individually selectable control signals.Because P5.4 is multiplexed with the ONCE# function,always configure it as an output to prevent accidental entryinto ONCE mode.BUSWIDTHREADYBHE#/WRH#ONCE#RD#WR#/WRL#INSTALE/ADV# Table 7. Signal Descriptions (Continued)Signal Name Type DescriptionMultiplexedWithP6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0O Port 6. This is an 8-bit output port that is multiplexed with the special functions of the waveform generator and PWMperipherals. The WG_OUT register configures the pins,establishes the output polarity, and controls whether changesto the outputs are synchronized with an event or take effectimmediately.PWM1PWM0WG3WG3#WG2WG2#WG1WG1#PACT#O Programming Active. In auto-programming mode, PACT#low indicates that programming activity is occurring.P2.5/COMP1PALE#I Programming ALE. In slave programming mode, this active-low input indicates that ports 3 and 4 contain acommand/address. When PALE# is asserted, data andcommands on ports 3 and 4 are read into the device.P2.1/SCLK0#/BCLK0PBUS.15:8 PBUS.7:0I/O Programming Bus. In programming modes, used as abidirectional port with open-drain outputs to pass commands,addresses, and data to or from the device. Used as a regularsystem bus to access external memory during auto-programming mode. When using slave programming mode,the PBUS is used in open-drain I/O port mode (not as asystem bus). In slave programming mode, you must addexternal pull-up resistors to read data from the device duringthe dump word routine.P4.7:0/AD15:8P3.7:0/AD7:0PMODE.3 PMODE.2 PMODE.1 PMODE.0I Programming Mode Select. Determines the OTPROMprogramming algorithm that is to be performed. PMODE issampled after a device reset when EA# = VEAand must bestable while the device is operating.P0.7/ACH7/T1DIRP0.6/ACH6/T1CLKP0.5/ACH5P0.4/ACH4PROG#I Programming Start. This active-low input is valid only inslave programming mode. The rising edge of PROG# latchesdata on the PBUS and begins programming. The falling edgeof PROG# ends programming.P2.2/EPA1PVER O Program Verification. In programming modes, this active-high output signal is asserted to indicate that the word hasprogrammed correctly. (PVER low after the rising edge ofPROG# indicates an error.)P2.0/EPA0PWM1:0O Pulse Width Modulator Outputs. These are PWM outputpins with high-current drive capability. The duty cycle andfrequency-pulse-widths are programmable.P6.7:6RD#O Read. Read-signal output to external memory. RD# isasserted only during external memory reads.P5.3Table 7. Signal Descriptions (Continued)Signal Name Type DescriptionMultiplexedWithREADY I Ready Input. This active-high input signal is used tolengthen external memory cycles for slow memory bygenerating wait states.When READY is high, CPU operation continues in a normalmanner. If READY is low, the memory controller inserts waitstates until the READY signal goes high or until the numberof wait states is equal to the number programmed into thechip configuration register.READY is ignored for all internal memory accesses.P5.6RESET#I/O Reset. Reset input to and open-drain output from the chip. Afalling edge on RESET# initiates the reset process. WhenRESET# is first asserted, the chip turns on a pull-downtransistor connected to the RESET pin for 16 state times.This function can also be activated by execution of the RSTinstruction. In the powerdown and idle modes, assertingRESET# causes the chip to reset and return to normaloperating mode. RESET# is a level-sensitive input.—RXD1 RXD0I/O Receive Serial Data 0 and 1. In modes 1, 2, and 3, RXD0 and 1 are used to receive serial port data. In mode 0, theyfunction as either inputs or open-drain outputs for data.P1.3P1.1SCLK1# SCLK0#I/O Synchronous Clock Pin 0 and 1. In mode 4, these are thebidrectional, shift clock signals that synchronize the serialdata transfer. Data is transferred 8 bits at a time with the LSBfirst. The DIR bit (SP_CON x.7) controls the direction ofSCLK x signal.DIR = 0The internal shift clock is output on SCLK x.DIR = 1An external shift clock is input on SCLK x.P2.7/BCLK1P2.1/BCLK0T1CLK I External Clock. External clock for timer 1. Timer 1increments (or decrements) on both rising and falling edgesof T1CLK. Also used in conjunction with T1DIR forquadrature counting mode.P0.6/ACH6/PMODE.2T1DIR I Timer 1 External Direction. External direction (up/down) fortimer 1. Timer 1 increments when T1DIR is high anddecrements when it is low. Also used in conjunction withT1CLK for quadrature counting mode.P0.7/ACH7/PMODE.3TXD1 TXD0O Transmit Serial Data 0 and 1. In serial I/O modes 1, 2, and 3, TXD0 and 1 are used to transmit serial port data. In mode0, they are used as the serial clock output.P1.2P1.0V CC PWR Digital Supply Voltage. Connect each VCCpin to the digital supply voltage.—V PP PWR Programming Voltage. Set to 12.5 V when programming the on-chip OTPROM. Also the timing pin for the “return frompower-down” circuit.—Table 7. Signal Descriptions (Continued)Signal Name Type DescriptionMultiplexedWithV REF PWR Reference Voltage for the A/D Converter. VREFis also the supply voltage to the analog portion of the A/D converter andthe logic used to read Port 0. VREFmust be connected for the A/D and port 0 to function.—V SS GND Digital Circuit Ground (0 volts). Connect each VSSpin to ground.—WG3 WG2 WG1O Waveform Generator Phase 1–3 Positive Outputs.3-phase output signals used in motion-control applications.P6.5P6.3P6.1WG3# WG2# WG1#O Waveform Generator Phase 1–3 Negative Outputs.Complementary 3-phase output signals used in motion-control applications.P6.4P6.2P6.0WR#O Write. This active-low output indicates that an external writeis occurring. This signal is asserted only during externalmemory writes.P5.2/WRL#WRH#O Write High. During 16-bit bus cycles, this active-low outputsignal is asserted for high-byte writes and word writes toexternal memory.During 8-bit bus cycles, WRH# is asserted for all writeoperations.P5.5/BHE#WRL#O Write Low. During 16-bit bus cycles, this active-low outputsignal is asserted for low-byte writes and word writes.During 8-bit bus cycles, WRL# is asserted for all writeoperations.P5.2/WR#XTAL1I Clock/Oscillator Input. Input to the on-chip oscillatorinverter and the internal clock generator. Also provides theclock input for the serial I/O baud-rate generator, timers, andPWM unit. If an external oscillator is used, connect theexternal clock input signal to XTAL1 and ensure that theXTAL1 VIH specification is met.—XTAL2O Oscillator Output. Output of the on-chip oscillator inverter.When using the on-chip oscillator, connect XTAL2 to anexternal crystal or resonator. When using an external clocksource, let XTAL2 float.—Table 7. Signal Descriptions (Continued)Signal Name Type DescriptionMultiplexedWithELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGS*Storage Temperature ................................ – 65°C to + 150°C Ambient Temperatureunder Bias.............................................. – 40°C to + 85°C Voltage from V PP or EA# toV SS or ANGND (Note 1)...................... – 0.5 V to + 13.0 V Voltage with respect toV SS or ANGND (Note 1)........................ – 0.5 V to + 7.0 V (This includes V PP on ROM and CPU devices.)Power Dissipation.......................................................... 1.5 W(based on package heat transfer limitations, not device power consumption)OPERATING CONDITIONS*T A (Ambient Temperature Under Bias).........– 40°C to + 85°C V CC (Digital Supply Voltage) .......................... 4.50 V to 5.50 V V REF (Analog Supply Voltage) ....................... 4.50 V to 5.50 V F OSC (Oscillator Frequency) (Note 2)........... 8 MHz to 16 MHzNOTES:1.ANGND and V SS should be at nominally the samepotential.2.Testing is performed down to 8 MHz, althoughthe device is static by design and will typically operate below 1 Hz.NOTICE : This data sheet contains preliminary infor-mation on new products in production. It is valid forthe devices indicated in the revision history. The specifications are subject to change without notice.*WARNING : Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reli-ability.。
