介质刻蚀技术发展
- 格式：pdf
- 大小：1.19 MB
- 文档页数：19
Dielectric Etch Challenges for State-of-The-Art Devices
TM
SEMI大半导体产业网 F.cEnOL Dielectric Etch Challenges
FinFET
LWR/LER
Sidewall Transfer
Channel
500
1000
1500
AppAlipepdliedDDCC vVooltlatgaeg[Ve] (V)
83 nm (61 nm)
173 nm (119 nm)
CF4, 100 mT, 5 x 1010 cm–3, Vpp = ∼ 70 V, 60 sec.
Modified layer becomes thicker as DC voltage increases.
BIMS-ASTS – Beijing, November 5th, 2010
12
SEMI大半导体产业网 www.semiB.oarllgis.tcinc Electron Effect 1 – 193 nm Resist
Cross-sectional SEM images of the 193 nm resist blanket wafers processed with various DC voltages
Leakage between capacitors
Sel. to ESL
Bottom CD
Etch Rate
Uniformity
Ref.: M. Wang (M. Kushner), AVS 2008
As scaling down CDs, new plasma control techniques need to be implemented into high aspect ratio dielectric etch.
TM
SEMI大半导体产业网
Outline
• Dielectric Etch Challenges for State-of-The-Art Devices
• Control Parameters of CCP
¾ Basic Components of Dielectric Etch Chamber ¾ Physical Effects of DC Superposition and Etch Applications ¾ DC Superimposed CCP with RF Pulsing
’98 GEC & ICRP: Sekine, et al.
Potential difference between the upper
electrode and plasma varies F/CFx radical ratio, which determines selectivity and
etch profile.
nickel silicide
Sel. to CESL
Sel. to NiSi & SiO2
Defect
Uniformity
Striation vs. GR Residue
As scaling down CDs, RIE needs to compensate the narrow lithography margin, and also needs to deal with new materials and new device structures.
Effect of interaction between Si-electrode and fluorocarbon plasma
Negative DC Voltage
Source RF
Bias RF
F, Si, CF, CF2, and CF3 radical density change as a function of Top Vdc applied to UEL.
As a result, secondary electrons are emitted from the surface, and are accelerated in the sheath on the upper electrode. Consequently, ballistic electron beam is generated.
Multiple zone gas supply for radical distribution control
Source RF power
Option: Frequency selection
Wafer edge ring for electron density uniformity
ESC for wafer clamping
Increase in total film thickness indicates polymer deposition. Thus, modified layer should consist of polymer and actual resist modification.
Without DC
DC = - 500 V
DC = - 1000 V
DC = - 1500 V
Modified layer thickness Modified lay(ernthimc)kness [nm]
0 nm (0 nm)
22 nm (18 nm)
200 160 120
80 40
0 0
Modified layer Deposition subtraction
BIMS-ASTS – Beijing, November 5th, 2010
Source RF power
Option: Frequency selection
Bias RF power
Option: Frequency selection, single or dual
9
SEMI大半导体产业网 DC Superimposed CCP
Negative DC voltage can control potential difference between the upper electrode and plasma.
Superimposed DC voltage controls ion bombardments at the upper electrode, which change F* density and generate ballistic electrons.
BIMS-ASTS – Beijing, November 5th, 2010
6
SEMI大半导体产业网 .HcAn R Dielectric Etch Challenges
Bowing
Sel. to Mask
Distortion/Twisting
Contact area variation
It is important to control potential between plasma and upper electrode for dielectric etch.
BIMS-ASTS – Beijing, November 5th, 2010
11
SEMI大半导体产业网 www.Mseemcih.oarngis.cmn of The Ballistic Electron’s Generation
Sel. to ESL
Common challenges
Defect
Trench Depth, Uniformity
Trench surface roughness
Metal hard mask scheme challenges
Sel. to Ti/TiN
Metalibility
BIMS-ASTS – Beijing, November 5th, 2010
4
SEMI大半导体产业网 Contact Etch Challenges
guard ring
CD Shrink
short line/trench
circle oval
dual stress liner
Superimposed Negative DC
UEL Acc.
Collide
Emitted Secondary e-
Positive +
ions
+
++
Acc.
Ballistic electron beam
Wafer
Positive ions are accelerated towards the upper electrode by superimposed negative DC, and collides with the upper electrode.
Superimposed DC voltage is another plasma process parameter.
BIMS-ASTS – Beijing, November 5th, 2010
10
SEMI大半导体产业网 e of Voltage Control of Upper Electrode
Negative DC Voltage
PPllaassmmaa ggeenneerraattiioonn Source RF
Source RF
Bias RF
Negative DC PPootteennttiiaall ccoonnttrrooll
IIoonn eenneerrggyy ccoonnttrrooll Bias RF
BIMS-ASTS – Beijing, November 5th, 2010
TM
SEMI大半导体产业网 F.cEnOL Dielectric Etch Challenges
FinFET
LWR/LER
Sidewall Transfer
Channel
500
1000
1500
AppAlipepdliedDDCC vVooltlatgaeg[Ve] (V)
83 nm (61 nm)
173 nm (119 nm)
CF4, 100 mT, 5 x 1010 cm–3, Vpp = ∼ 70 V, 60 sec.
Modified layer becomes thicker as DC voltage increases.
BIMS-ASTS – Beijing, November 5th, 2010
12
SEMI大半导体产业网 www.semiB.oarllgis.tcinc Electron Effect 1 – 193 nm Resist
Cross-sectional SEM images of the 193 nm resist blanket wafers processed with various DC voltages
Leakage between capacitors
Sel. to ESL
Bottom CD
Etch Rate
Uniformity
Ref.: M. Wang (M. Kushner), AVS 2008
As scaling down CDs, new plasma control techniques need to be implemented into high aspect ratio dielectric etch.
TM
SEMI大半导体产业网
Outline
• Dielectric Etch Challenges for State-of-The-Art Devices
• Control Parameters of CCP
¾ Basic Components of Dielectric Etch Chamber ¾ Physical Effects of DC Superposition and Etch Applications ¾ DC Superimposed CCP with RF Pulsing
’98 GEC & ICRP: Sekine, et al.
Potential difference between the upper
electrode and plasma varies F/CFx radical ratio, which determines selectivity and
etch profile.
nickel silicide
Sel. to CESL
Sel. to NiSi & SiO2
Defect
Uniformity
Striation vs. GR Residue
As scaling down CDs, RIE needs to compensate the narrow lithography margin, and also needs to deal with new materials and new device structures.
Effect of interaction between Si-electrode and fluorocarbon plasma
Negative DC Voltage
Source RF
Bias RF
F, Si, CF, CF2, and CF3 radical density change as a function of Top Vdc applied to UEL.
As a result, secondary electrons are emitted from the surface, and are accelerated in the sheath on the upper electrode. Consequently, ballistic electron beam is generated.
Multiple zone gas supply for radical distribution control
Source RF power
Option: Frequency selection
Wafer edge ring for electron density uniformity
ESC for wafer clamping
Increase in total film thickness indicates polymer deposition. Thus, modified layer should consist of polymer and actual resist modification.
Without DC
DC = - 500 V
DC = - 1000 V
DC = - 1500 V
Modified layer thickness Modified lay(ernthimc)kness [nm]
0 nm (0 nm)
22 nm (18 nm)
200 160 120
80 40
0 0
Modified layer Deposition subtraction
BIMS-ASTS – Beijing, November 5th, 2010
Source RF power
Option: Frequency selection
Bias RF power
Option: Frequency selection, single or dual
9
SEMI大半导体产业网 DC Superimposed CCP
Negative DC voltage can control potential difference between the upper electrode and plasma.
Superimposed DC voltage controls ion bombardments at the upper electrode, which change F* density and generate ballistic electrons.
BIMS-ASTS – Beijing, November 5th, 2010
6
SEMI大半导体产业网 .HcAn R Dielectric Etch Challenges
Bowing
Sel. to Mask
Distortion/Twisting
Contact area variation
It is important to control potential between plasma and upper electrode for dielectric etch.
BIMS-ASTS – Beijing, November 5th, 2010
11
SEMI大半导体产业网 www.Mseemcih.oarngis.cmn of The Ballistic Electron’s Generation
Sel. to ESL
Common challenges
Defect
Trench Depth, Uniformity
Trench surface roughness
Metal hard mask scheme challenges
Sel. to Ti/TiN
Metalibility
BIMS-ASTS – Beijing, November 5th, 2010
4
SEMI大半导体产业网 Contact Etch Challenges
guard ring
CD Shrink
short line/trench
circle oval
dual stress liner
Superimposed Negative DC
UEL Acc.
Collide
Emitted Secondary e-
Positive +
ions
+
++
Acc.
Ballistic electron beam
Wafer
Positive ions are accelerated towards the upper electrode by superimposed negative DC, and collides with the upper electrode.
Superimposed DC voltage is another plasma process parameter.
BIMS-ASTS – Beijing, November 5th, 2010
10
SEMI大半导体产业网 e of Voltage Control of Upper Electrode
Negative DC Voltage
PPllaassmmaa ggeenneerraattiioonn Source RF
Source RF
Bias RF
Negative DC PPootteennttiiaall ccoonnttrrooll
IIoonn eenneerrggyy ccoonnttrrooll Bias RF
BIMS-ASTS – Beijing, November 5th, 2010
