R6834中文资料

2008年最新注册码大全2008年最新注册码大全木马清除大师2008注册码用户ID:ce1b8d07 注册码:067359f709134db0============================================================== 木马分析专家2008 注册码用户名：2008safe 注册码：2008safe==============================================================瑞星2008序列号、注册码和ID序列号：5ABRV3-QAIVNG-V AWDS7-5SD200 ID: 5A71LG9JEB4Z序列号：080K3M-02050U-G0PVSC-AJE200 ID:6A94GZSK6F4R序列号：9A7UEK-AAHWBL-2IUHS3-SB5200 ID:4AIYCDUGPA4N产品注册码：CSA5V1-S7RJNG-EQV4S6-G8E200 用户ID：U2MZUAJ6QFVR产品序列号：CSA5V1-S7RJNG-EQV4S6-G8E200 用户ID：U2MZUAJ6QFVR序列号：1hb03g-pcap0t-63f8sb-gqe200 用户名：7alqrru4ki4xqq第六感注册码用户ID：LvTx[OCN] 注册码：123456-5E3625AD-B5B53164============================================================== cs1.6序列号注册码：5RP2E-EPH3K-BR3LG-KMGTE-FN8PYCDEKY序列号2847-60746-93835596-92528-27091859-25256-03349875-80220-7768xp序列号软件说明：Windows XP序列号大全注册码：Windows XP序列号大全中文专业版E7G7A-XEM0Q-SD1FW-E15S7-BELMNFCKGW-RHQQ2-YXRKT-8TG6W-2B7Q8BX6HT-MDJKW-H2J4X-BX67W-TVVFGCCC64-69Q48-Y3KWW-8V9GV-TVKRM中文家庭版(HOME Edition）：XJM6Q-BQ8HW-T6DFB-Y934T-YD4YTOEM版FCKGW-RHQQ2-YXRKT-8TG6W-2B7Q8英文版XP8BF-F8HPF-PY6BX-K24PJ-TWT6M============================================================== 卡巴斯基8.0激活码卡巴斯基8.0激活码FOR KIS: T1JVS-NNMBD-K1QTN-SUBP8卡巴斯基8.0激活码ROR KA V: FHJ4S-R1XEX-5BW3T-JYEKB卡巴斯基8.0激活码FOR WKS:W6MYU-MEHAZ-B61T9-2VV AM==============================================================流星蝴蝶剑序列号1.19654494997df42.CH6F7O11YD459B8A3.CHA3627BC28342034.CH95C3864A6EED6E5.CH533AJ55D0FC47D6.ch72636ebe1165g97.f0a03ce05646f48.CHH6253AB101C38E9.TW2596RB4F21998010.CH6WVSB21F502B7411.chu387bd8949cea412.CH0BEEB2F7D128E813.CH4BIC3B9731C85214.CH892D555D58D4A015.CH65674499343A7F16.19654494997df417.CH6F7O11YD459B8A18.CHA3627BC283420319.CH95C3864A6EED6E20.CH533AJ55D0FC47D21.ch72636ebe1165g922.f0a03ce05646f423.CHH6253AB101C38E24.TW2596RB4F21998025.CH6WVSB21F502B7426.chu387bd8949cea4电脑垃圾清理专家专业版V5.67注册码注册用户名：软件授权码：48651293C多媒体文件加密器离线授权版5.0注册码注册码：6a9340d72c8e9413eadd4faaefbb08c5QUICKTIME是苹果公司进军PC领域的一个强劲的媒体播放器！序列号：Registered T Dawn M FredetteKey: 4UJ2-5NLF-HFFA-9JW3-X2KV最新瑞星杀毒软件下载版序列号，注册码SN: DR610M SEHG85 MSVUS2 P9E200ID:6AA1EU9NWG4A电子相册王(Photofamily) V3.0 注册码：用户名：zmw1224[CZG[DFCG]注册码：QUSKJ-HMKAE-FVJFW电子相册王(Photofamily) V3.0 下载：/soft/2777.htmlPowerShadow 影子系统下载：/cn/index.html/coop/26702.html/system/sysenhance/30206.htmlPowerShadow 影子系统最新注册码序列号：用户名werShadow序列号:VVR29E-R4WCK2-K4T111-V1YHTP-4JYJDDPowerShadow 影子系统2008 光盘版序列号：0620219292密码：750916 MOBILedit! 可以让你通过蓝牙技术、红外线和电缆，用电脑来控制你的手机。

元器件交易网Parts Not Suitable for New DesignsFor Additional InformationEnd-Of-Life Product Change NoticeOrder this document by MC68341UMAD/ADThis document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.ADDENDUM TOMC68341 Integrated Processor User's ManualMC68341Microprocessor and Memory Technologies GroupApril 19, 1995This addendum to the initial release of the MC68341UM/AD User’s Manual provides corrections to the original text, plus additional information not included in the original. This document and other information on this product is maintained on the AESOP BBS, which can be reached at (800)843-3451 (from the US and Canada) or (512)891-3650. Configure modem for up to 14.4Kbaud, 8 bits, 1 stop bit, and no parity. Terminal software should support VT100 emulation. Internet access is provided by telneting to [129.38.233.1] or through the World Wide Web at .1. Signal IndexOn page 2-4, Table 2-4, the QSPI serial clock QSCLK should be listed as an I/O signal. At the bottom of Table 2-5, FC3/DTC is an output-only signal.2. Operand AlignmentOn page 3-9, last paragraph, change the first two lines to: “The CPU32 restricts all operands (both data and instructions) to be word-aligned. That is, word and long-word operands must be located on a word boundary.”Long-word operands do not have to be long-word aligned.3. WE on Fast TerminationOn page 3-17, Figure 3-6, UWE and LWE do not assert for fast termination writes.4. Write Cycle Timing WaveformsOn page 3-25, the M68300 write cycle timing diagram (Figure 3-12) shows incorrect timing for DS, UWE, and LWE. On page 3-28, the M68000 write cycle timing diagram (Figure 3-14) shows incorrect timing for AS68K,CSx, UDS/LDS, and UWE/LWE. Replace these figures with the following corrected figures.5. Additional Note on MBAR DecodeAdd to the CPU Space Cycles description on page 3-31: The CPU space decode logic allocates the 256-byte block from $3FF00-3FFFF to the SIM module. An internal 2-clock termination is provided by this initial decode for any access to this range, but selection of specific registers depends on additional decode.Accesses to the MBAR register at long word $3FF00 are internal only, and are only visible by enabling show cycles. Users should directly access only the MBAR register, and use the LPSTOP instruction to generate the LPSTOP broadcast access to $3FFFE. The remaining address range $3FF04-3FFFD is Motorola reserved and should not be accessed.元器件交易网Figure 3-12. M68300 Write Cycle timingFigure 3-14. M68000 Write Cycle Timing元器件交易网6. Additional Notes on CPU Space Address EncodingOn page 3-31, Figure 3-16, the BKPT field for the Breakpoint Acknowledge address encoding is on bits 4-2, and the T bit is on bit 1. The Interrupt Acknowledge LEVEL field is on bits 3-1.7. BreakpointsOn page 3-31, the last paragraph implies that either a software breakpoint (BKPT instruction) or hardware breakpoint can be used to insert an instruction. As noted in the following paragraphs, only a software breakpoint can be used to insert an instruction on the breakpoint acknowledge cycle.8. Interrupt LatencyAdd to the Interrupt Acknowledge Bus Cycles section on page 3-36: Interrupt latency from IRQx assert to prefetch of the first instruction in the interrupt handler is about 37 clocks + worst case instruction length in clocks (using 2-clock memory and autovector termination). From the instruction timing tables, this gives 37+71 (DIVS.L with worst-case <fea>) = 108 clocks worst case interrupt latency time. For applications requiring shorter interrupt response time the latency can be reduced by using simpler addressing modes and/or avoiding use of longer instructions (specifically DIVS.L, DIVU.L, MUL.L).9. Interrupt Hold Time and Spurious InterruptsAdd to the Interrupt Acknowledge Bus Cycles section on page 3-36: Level sensitive interrupts must remain asserted until the corresponding IACK cycle; otherwise, a spurious interrupt exception may result or the inter-rupt may be ignored entirely. This is also true for level sensitive external interrupts which are autovectored us-ing either the AVEC signal or the AVEC register, since the SIM will not respond to an interrupt arbitration cycle on the IMB if the external interrupt at that level has been removed. External interrupts configured as edge sen-sitive only have to be held a minimum of 1.5 clocks - see section 4.3.5.8 PROGRAMMABLE INTERRUPT REGISTER (PIR).Note that the level 7 interrupt is also level sensitive, and must be held until a level 7 IACK begins. The level 7 interrupt is unique in that it cannot be masked - another level 7 interrupt exception can be created after the IACK cycle by negating IRQ7 and reasserting, even though the interrupt mask level in the SR is now set to level 7.10. Typos in IACK Cycle Timing WaveformsOn page 3-38, Figure 3-21, the text “VECTOR FROM 16-BIT PORT” should be on D7-D0, and “VECTOR FROM 8-BIT PORT” should be on D15-D8. The responding device returns the vector number on the least sig-nificant byte of the data port.11. Additional Note on Internal Autovector OperationAdd to the Autovector Interrupt Acknowledge Cycle section on page 3-38: If an external interrupt level is autovectored either by the AVEC register programming or the external AVEC signal, an external IACK will be started and terminated internally. The interrupting device should not respond to this IACK in any way, or the resulting operation is undefined.12. Additional Notes on Retry TerminationOn page 3-42, Table 3-4: When HALT and BERR are asserted together in case #5 to force a retry of the current bus cycle, relative timing of HALT and BERR must be controlled to avoid inadvertently causing bus error ter-元器件交易网mination case #3. This can be done by asserting HALT and BERR either synchronously to the clock to directly control which edge each is recognized on, or asynchronously with HALT asserted for time [spec 47A+spec 47B] ns before BERR to guarantee recognition on or before the same clock edge as BERR.13. Active Negate on Bus ArbitrationThe 68341 actively pulls up all tri-stateable bus pins other than the data bus before tristating them during bus arbitration. This pullup function is not guaranteed to result in spec VOH levels before tristating, but will help reduce rise time on these signals when using weak external bus pullups.14. Additional Note on Bus Arbitration PriorityFor the bus arbitration description beginning on page 3-49: The arbitration priority between possible bus mas-ters for this device is external request via BR (highest priority), DMA, then CPU (lowest). The priority of DMA channels 1 and 2 relative to each other is selected by their respective MAID levels which must be unique.15. Additional Note on Bus Arbitration and Operand CoherencyFor the bus arbitration description beginning on page 3-49: Each bus master maintains operand coherency when a higher priority request is recognized. For example, a CPU write of a long-word operand to a byte port results in a sequence of four bus cycles to complete the operand transfer - the CPU will not release the bus until the completion of the fourth bus cycle. A single address DMA transfer is handled in a similar manner. Fora dual address DMA transfer, the read and write portions are handled as separate operands, allowing arbitra-tion between the read and write bus cycles. Also, if different port sizes are specified in the DMA configuration for the source and destination, arbitration can occur between each of the multiple operand accesses which must be made to the smaller port for each operand access to the larger port. The RMC read/write sequences for a TAS instruction is also indivisible to guarantee data coherency. Arbitration is allowed between each op-erand transfer of a multi-operand operation such as a MOVEM instruction or exception stacking.16. Additional Notes on RESET Interaction with Current Bus CycleAdd to the Reset Operation description beginning page 3-55:Hardware resets are held off until completion of the current operand transfer in order to maintain operand co-herency. The processor resets at the end of the bus cycle in which the last portion of the operand is transferred, or after the bus monitor has timed out. The bus monitor operates for this specific case whether it is enabled or not, for the period of time that the BMT bits are set to.The following reset sources reset all internal registers to their reset state: external, POR, software watchdog, double bus fault, loss of clock. Execution of a RESET instruction resets the peripheral module registers with the exception of the MCR registers. The MCR register in each module, the SIM41 registers, and the CPU state are not affected by execution of a RESET instruction.17. External ResetOn page 3-56, Figure 3-33, the RESET signal negates for two clocks between internal and external assertions, not one. Note that RESET is not actively negated, and its rise time is dependent on the pullup resistor used.18. Power-On ResetOn page 3-57, Figure 3-34. Power-Up Reset Timing Diagram: CLKOUT is not gated by VCO lock or other in-ternal control signals, and can begin toggling as soon as VCC is high enough for the internal logic to begin operating. For crystal mode and external clock with VCO mode, after the VCO frequency has reached an initial元器件交易网stable value, the 328*TCLKIN delay is counted down, and VCO lock is set after completion of the 328 clock delay. For external clock mode without VCO, the 328*TCLKIN delay starts as soon as EXTAL clock transitions are recognized. See note for page11-3 for more POR information.19. Internal IMB ArbitrationOn page 4-6, first paragraph, change the first sentence to read “There are eight arbitration levels for the various bus masters on the MC68341 to access the inter-module bus (IMB).”20. Additional Note for External Clock Mode with PLLOn page 4-9, Table 4-1, External Clock Mode with PLL: the PLL phase locks the CLKOUT falling edge to the falling edge of the EXTCLK input clock. Maximum skew between falling edges of the EXTCLK and CLKOUT signals is specified in the Section 12 Electrical Characteristics.21. External Clock Mode OperationThe next-to-last paragraph on page 4-11 incorrectly states that the SYNCR V, W, X, Y, and Z bits can all affect the system frequency in external clock mode. In external clock mode only the V bit affects the system frequen-cy, by selecting either EXTCLK or EXTCLK/2 as reference input to the phase comparator. The VCO frequency divided by 2 is used both for CLKOUT as well as the feedback input to the phase comparator. A reset forces V=0, resulting in an initial processor operating frequency of 1/2 the EXTCLK frequency.For applications using external clock mode, the 32KHz crystal connected to EXTAL and XTAL is only required if the realtime clock function is needed - ground EXTAL if the RTC is not used. Also, the clock input on EXT-CLK should be very clean when the 32KHz oscillator is used. Excessive undershoot or overshoot, as well as fast edge rates may result in coupling to the adjacent XTAL input, affecting operation of the 32kHz oscillator.22. Recommended XFC Capacitor ValuesOn page 4-12, third paragraph, and page 11-2, last paragraph: The XFC capacitor recommendation of 0.01µF to 0.1µF applies specifically to crystal mode operation. When using external clock with VCO mode, for phase detector refernce frequencies > 1MHz start with a capacitance value of 10000pf/F_MHz. For example at16.0MHz the recommended XFC capacitance is approximately 10000pf/16.0 = 625pf - choose the next higherstandard value available.23. CLKOUT and VCO Frequency ProgrammingOn pages 4-13 and 4-14, the column for W=1:Z=0:X=1 is incorrect - the correct value for each entry in this column is 2x the frequency in the X=0 column immediately to the left. A corrected table is shown on the follow-ing pages. Note that although a complete table is shown for all W:X:Y:Z combinations, both CLKOUT and VCO frequency limits must be observed when programming the SYNCR. For example, a system operating frequen-cy (CLKOUT) of 25.16MHz can be selected with W:X:Y:Z=1:1:23:1, resulting in a VCO frequency of 50.3MHz.However, programming W:X:Y:Z=1:0:47:1 to achieve the same system frequency would result in a VCO fre-quency of greater than 100MHz, which is outside the spec VCO frequency operating range.24. Additional Note for Global Chip SelectOn page 4-16, section 4.2.4.2: When operating as a global chip select, CS0 does not assert for accesses to either the MBAR or to internal peripheral module registers.元器件交易网Table 4-2. System Frequencies from 32.768-kHz Reference元器件交易网Table 4-2. System Frequencies from 32.768-kHz Reference (Continued)1. Some W/X/Y/Z bit combinations shown may select a CLKOUT or VCO frequency higher than spec. Refer to Sec-tion 11 Electrical Characteristics for CLKOUT and VCO frequency limits.2. Any change to W or Y results in a change in the VCO frequency - the VCO should be allowed to relock if necessary.元器件交易网25. Additional Note on PORTA/B Output TimingAdd to the External Bus Interface Operation description on page 4-17: The Port A and Port B output pins tran-sition after the S4 falling edge for the internal write to the respective data register. This places port pin transi-tions at roughly the same time DS negates for the data register write - note this output delay is not currently specified in the Electrical Specifications.26. RTC Memory MapThe RTC register offsets shown on page 4-21 are incorrect - a corrected memory map is shown below. Ad-dresses within the RTC can be accessed as either bytes or words, with the exception of the reserved byte at offset $0CE. Note that RTC registers marked S/U are read/write in supervisor mode, but can only be read in user mode.ADDR FC15 8ADDR FC7 00C0S RTC INTERRUPT CONTROL (RICR)0C2S/U MINUTES (MIN)0C3S/U SECONDS (SEC)0C4S/U DA TE0C5S/U HOUR0C6S/U MONTH0C7S/U YEAR0C8S RTC CONTROL/ST A TUS (RCR)0C9S/U DAY0CA S/U MINUTES ALARM (MINA)0CB S/U SECONDS ALARM (SECA)0CC S/U DA TE ALARM (DA TEA)0CD S/U HOURS ALARM (HOURA)0CE-RESERVED0CF S RTC CALIBRA TION (RCCR)27. MBAR Register Reset ValuesOn page 4-22, the reset values for MBAR bits 31-12 are undefined.28. MBAR AS7 Bit and IACK CyclesOn page 4-23, the second code sequence initializes the MBAR register with AS7 set. This prevents the ad-dress decode for the internal 4K register block from responding to CPU space accesses. In particular, it pre-vents the register block decode of $FFFFFxxx from interfering with IACK cycles (address $FFFFFFFx), and possibly corrupting the vector number returned. Normal interrupt acknowledge operation for the internal mod-ules is not affected by this change.Early versions of the MC68330 User’s Manual (original release) and MC68340 User’s Manual (original and Rev. 1 releases) did not show AS7 set. Code which was developed based on these manual revisions should be checked for this problem when porting to the MC68341 - this change should also be applied back to the MC68330 and/or MC68340.29. Additional Note on VCO OvershootOn page 4-30 place the following note under the Y-bits description:A VCO overshoot can occur when increasing the operating frequency by changing the Y bits in the SYNCR register. The effects of this overshoot can be controlled by following this procedure:1. Write the X bit to zero. This will reduce the previous frequency by one half.2. Write the Y bits to the desired frequency divided by 2.3. After the VCO lock has occurred, write the X bit to one. This changes theclock frequency to the desired frequency.Steps 1 and 2 may be combined.30. RCCR InitializationAdd to the RCCR description on page 4-41: the RCCR register is unaffected by a processor reset, and contains an arbitrary value on initial powerup of the RTC. Calibration software should clear the RCCR register before beginning the calibration process, since RTC operation with an invalid RCDx value is undefined. RCCR[7] is reserved - on current silicon it always reads 0, and should always be written 0.31. RCCR TyposOn page 4-42, delete the first description for RCD4-RCD0 near the top of the page.32. MONTH Register RangeThe valid range for the MONTH register on page 4-43 is 1-12, with “1” corresponding to January and “12” cor-responding to December.33. SIM41 Example CodeOn page 4-49, about mid-page, change “MOVEQ #8-1,D0” to “MOVEQ #16-1,D0” to initialize all 8 chip se-lects.34. Bus Error Stack FrameOn page 5-61, in the next-to-last paragraph, delete “(the internal transfer count register is located at SP+$10 and the SSW is located at SP+12)”. The stack space allocation is the same for both faults - the location of the internal count register and SSW remains the same. The only difference is that the faulted instruction program counter location SP+10 and SP+12 will contain invalid data. To tell the difference between the two stack frames, look at the first nibble of the faulted exception format vector word located at SP+$E - it will be $0 for the four-word frame, and $2 for the six-word frame.35. DSO TimingOn page 5-71, Figure 5-23, DSO transitions one clock later than shown.36. Typo on BDM RSREG CommandOn page 5-77, Section 5.6.2.8.6, RSREG register bit #8 should be a “1”.37. IPIPE TimingOn page 5-88, Figure 5-29 shows the third IPIPE assertion low lasting for 1.5 CLKs - it actually asserts for an additional 0.5 CLKs. IPIPE transitions occur after the falling edge of CLKOUT.38. Additional Notes on DMA FeaturesIn the feature set listed on page 6-1, bullet six is “Operand Packing and Unpacking for Dual-Address Trans-fers”. This packing is for transfers between different port sizes selected in the DMA channel control register, e.g. Byte <> Word transfers. The DMA controller does not do packing for byte > byte transfers, eliminating the problem of residual bytes left in the controller when a channel is stopped after an odd byte transfer count. 39. Additional Note on Internal Request GenerationAdd to the Internal Request Generation section on page 6-5: For internal request operation, DACKx and DON-Ex are not active as outputs during transfers. DONEx is valid as an input though and will terminate channel operation if asserted - pull up if not used.40. Additional Note on DMA Transfer Latency from DREQAdd to the External Request Generation section beginning 6-5: DREQx assertions require two clocks for input synchronization and IMB bus arbitration activity before the resulting DMA bus cycle can start. A DREQx as-sertion will preempt the next CPU bus cycle if it is recognized two or more clocks before the end of the current bus cycle, unless the current cycle is not the last cycle of an operand transfer, or is the read of an RMC cycle. Operand transfers and RMC read/write sequences are indivisible to guarantee data coherency - the bus can-not be arbitrated from the CPU until the complete operand transfer completes, even if operand and memory sizing results in multiple bus cycles.For a DREQx assertion during an idle bus period, bus state S0 of the DMA bus cycle starts 2.5 clocks after the clock falling edge which DREQx is recognized on. The maximum latency from the clock falling edge that DREQx is recognized on to the falling edge that AS for the DMA cycle asserts from is shown in the following table for various memory speeds.DREQ Latency (Clocks) vs. Bus Width and Access Times41. Additional Note on Burst Transfer DREQx Negation and OverheadOn page 6-5, replace the 2nd paragraph of 6.3.2.1 External Burst Mode with the following: DREQx must be negated one clock before the end of the last DMA bus cycle of a burst to prevent another DMA transfer from being generated. Also, DREQx must be negated two clocks before the end of the last DMA bus cycle to prevent an idle clock between that transfer and the following CPU access.42. Additional Note on Cycle steal DMA arbitration overheadAdd to the External Cycle Steal Mode description on page 6-6: In general, DMA arbitration occurs transpar-ently. However, for some 2-clock accesses using cycle steal an idle clock can follow the DMA transfer due to incomplete overlap of the DMA transfer with internal IMB arbitration. Specifically, an idle clock can follow 1) single address 2-clock transfers and 2) dual address transfers from memory to 2-clock devices. Arbitration is completely overlapped for all other cases.43. Additional Note on Cycle StealFor the external cycle steal mode description on page 6-6, the initial DREQx assertion does not have to be held off until after the channel is started. If DREQx is already asserted when the channel is started by setting the channel start bit, an internal DREQx assertion is generated, providing the edge needed for the DMA cycle to start.44. DREQx Negation on BurstOn page 6-8, Figure 6-5, and on page 6-10, Figure 6-7, DREQx should negate before the falling edge of S2 (one clock earlier than shown) to prevent another DMA transfer from occurring. See the note above for page 6-5 on Burst Transfer DREQx Negation.45. DREQ Assert TimeOn page 6-21, Figure 6-13: The second DREQx assertion should be shown held for an additional clock to guar-antee recognition on 2 consecutive clock falling edges. The figure shows it as just being 1 clock period. Note 1 should be deleted.46. Fast Termination and Burst Request ModeOn the last paragraph of page 6-21, delete the reference to Figure 6-14. Figure 6-14 on page 6-22 is labeled incorrectly - it actually shows operation with fast termination, cycle steal, and dual address transfers. Also, the second DREQx signal should be held for 2 consecutive falling edges - the figure shows it being held for only 1 clock edge. Note 1 of Figure 6-14 should be deleted.47. Typo in DAPIOn page 6-26, for DAPI = 1, the DAR is incremented according to the destination size (not the source size).48. Additional note on DMA limited rate operationOn page 6-27, in the BB-Bus Bandwidth Field: The DMA “active” count increments only when the DMA channel is the bus master (each channel has its own counter). If a higher priority bus master forces the channel to relinquish the bus before completion of the active count, the counter stops until the channel regains the bus. Higher priority requests could come from 1) the other DMA channel (if it has a higher MAID level), 2) the CPU32 core (if either the interrupt mask level in the SR or the interrupt request level is higher than the DMA channel's ISM level), or 3) an external bus request. When the active count is exhausted, the DMA channel releases the bus, and the “idle” count increments regardless of bus activity.49. Configuration ErrorThe Configuration Error description paragraph at the top of page 6-29 should be replaced with “A configuration error results when 1) either the SAR or DAR contains an address that does not match the port size specified in the CCR, or 2) the BTC register does not match the larger port size or is zero.”50. Additional Note on DMA Interrupt PrioritizationAdd to the Interrupt Register description on page 6-31: When both DMA channels are programmed to the same interrupt level, channel 1 is higher priority than channel 2.51. Single Address Enable6-33 SE-Single Address Enable: The note “used for intermodule DMA” should be for the SE=1 case. The 68341 does not support intermodule single address transfers, so the SE bit should always be programmed to “0”.52. Code Examples - Immediate Addressing ModeOn pages 6-40 through 6-44 make the following change as shown for each occurrence of SARADD, DARADD, and NUMBYTE (change to immediate addressing mode for source operand):MOVE.L SARADD,DMASAR1(A0) should be MOVE.L #SARADD,DMASAR1(A0).MOVE.L DARADD,DMADAR1(A0) should be MOVE.L #DARADD,DMADAR1(A0).MOVE.L NUMBYTE,DMABTC1(A0) should be MOVE.L #NUMBYTE,DMABTC1(A0).53. Serial Oscillator Problems with DMA activityAdd to the Crystal Input or External Clock (X1) section on page 7-5: A high DREQ1 request rate (greater than 1MHz) with excessive undershoot on DREQ1 can result in internal signal coupling to the serial module oscil-lator X1 pin, damping out oscillation. Avoid routing DREQ1 near the serial oscillator external components, and use termination techniques such as series termination of the DREQ1 driver (start with 33Ω) to limit edge rate of the signal and accompanying undershoot.54. Additional Note on RTSx operation detailsAdd to the RTSA and RTSB descriptions on page 7-6: The RTSx outputs are active low signals - they drive a logic “0” when set, and a logic “1” when cleared.RTSx can be set (output logic level 0) by any of the following:• Writing a “1” to the corresponding bit in the OPSET register $71E• Issuing an “Assert RTS” command using command register CR• If RxRTS=1, set by receiver FIFO transition from FULL to not-FULLRTSx can be cleared (output logic level 1) by any of the following:• Hardware reset of the serial module• Writing a “1” to the corresponding bit in the OPRESET register $71F• Issuing a “Negate RTS” command using command register CR• If RxRTS=1, cleared by receiver FIFO transition from not-FULL to FULL• If TxRTS=1, cleared by completion of last character, including transmission of stop bits55. Serial Frequency RestrictionOn page 7-8, place the following notes at the end of Section 7.3.1 Baud Rate Generator:The current implementation of the serial module restricts the minimum CLKOUT frequency at which the baud rate generators can be used to approximately 8.3MHz. Operation below this frequency results in a synchro-nized internal clock which is at a lower frequency than the X1 input, which then results in incorrect baud rates. One method to extend the minimum CLKOUT frequency is to reduce the X1 frequency by powers of 2 as shown in the table below. The corresponding baud rates selected by the clock select register programming arescaled by the same factor. This method preserves most of the standard baud rates (19200, 9600, 4800, etc.).CLKOUT min = 2.25*XTAL frequencyAlternatively, the baud rate clock can be supplied directly through the SCLK input. Since there is a single SCLK input, both serial channels must use the same baud rate clock, although one could be clocked in the 1x mode and the other in the 16x mode. When using this method, the X1 input can be tied to ground - no crystal is re-quired.56. 68341 Serial Module RTS Difference from 68681Add to the description for receiver-controlled RTS operation in the next-to-last paragraph on page 7-13: Unlike the 68681, the RTSx signal does not have to be manually asserted the first time in the mode to support control-flow capability on the receiver.57. Additional Note on Serial multidrop operationAdd to the Multidrop Mode section beginning on page 7-15: For multidrop mode, it is not necessary to disable the transmitter to manipulate the A/D bit, as generally implied in the manual, nor is it necessary to wait until the previous character completes transmission (i.e. TxEMP). The serial module logic latches this bit and ap-pends it to the data character when the character is transferred from the transmit buffer to the serial output shift register. Once this transfer occurs (as indicated by the TxRDY assertion), the A/D bit in MR1 can be changed without affecting the character in progress. The proper programming sequence to change the A/D bit for the next character would be:1.)poll TxRDY until asserted (or interrupt on TxRDY)2.) set/clear A/D bit in MR1 for new character3.) write character to transmit buffer (TB)4.) A/D bit can be changed only after TxRDY asserts againNo other bits in MR1 should be modified when changing the A/D bit.58. Typo in CPE DescriptionThe CPE bit header on page 8-20 should be "Counter/Prescaler Enable".59. Typo in Status Register ConfigurationOn page 8-26, Section 8.5.1, the Status Register (SR) description should say: "• Clear the TO, TG, and TC bits to reset the interrupts."60. Typos in Timer Initialization ExamplesOn pages 8-27 and 8-29, the Timer register offsets should be from the timer base address, not from the SIM41 base address. The correct equates for the Timer register offsets are:。

内置高压MOSFET电流模式PWM+PFM控制器系列DIP-8-300-2.54产品规格分类产品名称封装类型打印名称材料包装SD6834 DIP-8-300-2.54 SD6834 无铅料管典型输出功率能力190~265V 85~265V产品开放式适配器开放式适配器SD6834 14W 19W 12W 15W内部框图符 号 参 数 范 围参 数Ω）V650 VV±30 V10 A=25°C) 2.5 A2E140 mJ28 V-0.3~7 V 峰值电流采样端电压-0.3~2 V6.3 Wja 77jc 20+150-25~+85-55~+150注：1. 脉冲宽度由最大结温决定；2. L=51mH， T J=25°C(起始)。

电气参数(感应MOSFET部分，除非特殊说明， T=25°C)amb参数符号测试条件最小值典型值最大值单位漏源击穿电压BV DSS V GS=0V，I D=50μA 650 -- -- VV DS=650V，V GS=0V -- -- 50 μA零栅压漏端电流I DSSV DS=480V，V GS=0V T amb=125°C -- -- 200 μAV GS=10V，I D=0.5A 2.3 3.4 4.5 Ω静态漏源导通电阻R DS(ON)V GS=10V，I D=1.25A 2.5 3.6 4.7 Ω输入电容C ISS V GS=0V，V DS=25V，f=1MHz 224 320 416 pF输出电容C OSS V GS=0V，V DS=25V，f=1MHz 28 41 54 pF反向传输电容C RSS V GS=0V，V DS=25V，f=1MHz 0.9 1.3 1.7 pF导通延迟时间T D(ON)V DD=0.5BV DSS，I D=25mA 9.1 13 16.9 ns上升时间T R V DD=0.5BV DSS，I D=25mA 21.731 40.3 ns关断延迟时间T D(OFF)V DD=0.5BV DSS，I D=25mA 12.618 23.4 ns下降时间T F V DD=0.5BV DSS，I D=25mA 14 20 26 ns电气参数(除非特殊说明，V=12V，T amb=25°C)CC参 数 符 号 测 试 条 件 最小值典型值 最大值 单位欠压部分上电启动电压V START 14.515.5V17.0关断电压V STOP 7.59.5V8.3振荡部分振荡频率最大值f OSCMAX V FB73KHz67=3V 61振荡频率最小值f OSCMIN V BURL<V FB<V BURH20 25 30 KHz振荡频率抖动最大值f MOD振荡频率最大±1.5±2.5 ±3.5 KHz振荡频率随温度的变化率-- 25°C≤T amb≤+85°C --%±5±10最大占空比D MAX 72%8277反馈部分反馈源电流最大值I FBMAX V FBmA1.10.9=0V 0.7反馈关断电压(过载保护) V SD 3.8V4.34.8反馈关断延迟时间T SD FB从0V瞬间上升至5V 15 27 40 ms关断延迟电流I DELAY V FBμA8 =5V 35.5CS部分CS最大值V CSMAX 0.7V1.10.9打嗝模式控制打嗝模式高电平V BURH FB电压0.400.50 0.60 V打嗝模式低电平V BURL FB电压0.250.35 0.45 V保护部分过压保护V OVP V CC电压23 24.5 26 V参 数 符 号 测 试 条 件 最小值典型值 最大值 单位过温保护T OTP 125150°C175前沿消隐时间T LEB 250ns450325总待机电流部分启动电流I START V CC从0V上升至12V 1 3 10 μA静态电流I STATIC V FBmA3.01.9=0V 1.0工作电流I OP V FB3.2mA2.2=3V 1.2端接在一起，可以更好地辅助散热。

HT45R34C/R to F Type 8-Bit OTP MCURev.1.201October 15,2007General DescriptionThe HT45R34is an 8-bit high performance,RISC archi-tecture microcontroller device specifically designed for cost-effective multiple I/O control product applications.The advantages of low power consumption,I/O flexibil-ity,timer functions,oscillator options,Power Down andwake-up functions,Watchdog Timer,enhance the ver-satility of these devices to suit a wide range of applica-tion possibilities such as industrial control,consumer products,subsystem controllers,etc.Features·Operating voltage:f SYS =4MHz:2.2V~5.5V f SYS =8MHz:3.3V~5.5V·8bidirectional I/O lines·Two external interrupt inputs shared with I/O lines ·8-bit programmable timer/event counter withoverflow interrupt and 7-stage prescaler·External RC oscillation converter ·On-chip crystal and RC oscillator ·Watchdog Timer·Multi-pin capacitor/resistor sensor input ·1024´14program memory ·88´8data memory RAM·Power Down and Wake-up function reduce powerconsumption·Up to 0.5m s instruction cycle with 8MHz system clockat V DD =5V·All instructions executed in one or two machinecycles·14-bit table read instruction ·Four-level subroutine nesting ·Bit manipulation instruction ·63powerful instructions ·Low voltage reset function ·20-pin DIP/SOP packages24-pin SKDIP/SOPpackagesTechnical Document·Tools Information ·FAQs·Application Note-HA0075E MCU Reset and Oscillator Circuits Application NoteBlock DiagramPin AssignmentRev.1.202October15,2007Pin DescriptionPin Name I/O Options Description PA0/INT0PA1/INT1 PA2/TMR PA3~PA7I/OPull-high*Wake-upBidirectional8-bit I/O port.Each pin can be configured as a wake-up input via con-figuration options.Software instructions determine if the pin is a CMOS output orSchmitt trigger input.Pull-high resistors can be added to the each pin via a configu-ration option.Pins PA0and PA1are pin-shared with external interrupt input pins INT0and INT1,respectively.Configuration options determine the interrupt enable/disable and theinterrupt low/high trigger type.Pins PA2is pin-shared with the external timer inputpins TMR.RC1~RC12I¾Capacitor or resistor connection pinsRCOUT I¾Capacitor or resistor connection pin to RC OSC IN I¾Oscillation input pinRREF O¾Reference resistor connection pinCREF O¾Reference capacitor connection pinRES I¾Schmitt trigger reset input.Active lowVSS¾¾Negative power supply,groundVDD¾¾Positive power supplyOSC1 OSC2IOCrystal or RCOSC1,OSC2are connected to an RC network or Crystal determined by a configu-ration option,for the internal system clock.In the case of the RC oscillator,OSC2can be used to monitor the system clock.Its frequency is1/4system clock.Note:*All pull-high resistors are controlled by an option bit.Absolute Maximum RatingsSupply Voltage...........................V SS-0.3V to V SS+6.0V Storage Temperature............................-50°C to125°C Input Voltage..............................V SS-0.3V to V DD+0.3V Operating Temperature...........................-40°C to85°C I OL Total..............................................................300mA I OH Total............................................................-200mA Total Power Dissipation.....................................500mWNote:These are stress ratings only.Stresses exceeding the range specified under²Absolute Maximum Ratings²may cause substantial damage to the device.Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C.Characteristics Ta=25°CSymbol ParameterTest ConditionsMin.Typ.Max.Unit V DD ConditionsV DD Operating Voltage¾f SYS=4MHz 2.2¾ 5.5V f SYS=8MHz 3.3¾ 5.5VI DD1Operating Current(Crystal OSC,RC OSC)3VNo load,f SYS=4MHz¾12mA 5V¾35mAI DD2Operating Current(Crystal OSC,RC OSC)5V No load,f SYS=8MHz¾48mAI STB1Standby Current(WDT Enabled)3VNo load,system HALT¾¾5m A 5V¾¾10m ARev.1.203October15,2007Symbol ParameterTest ConditionsMin.Typ.Max.Unit V DD ConditionsI STB2Standby Current(WDT Disabled)3VNo load,system HALT¾¾1m A 5V¾¾2m AV IL1Input Low Voltage for I/O Ports,TMR,INT0and INT1¾¾0¾0.3V DD VV IH1Input High Voltage for I/O Ports,TMR,INT0and INT1¾¾0.7V DD¾V DD V V IL2Input Low Voltage(RES)¾¾0¾0.4V DD V V IH2Input High Voltage(RES)¾¾0.9V DD¾V DD V V LVR Low Voltage Reset¾LVRenabled 2.7 3.0 3.3VI OL PA,RREF and CREF Sink Current 3VV OL=0.1V DD48¾mA 5V1020¾mAI OH PA,RREF and CREF Source Current 3VV OH=0.9V DD-2-4¾mA 5V-5-10¾mAR PH Pull-high Resistance3V¾2060100k W5V¾103050k W A.C.Characteristics Ta=25°CSymbol ParameterTest ConditionsMin.Typ.Max.Unit V DD Conditionsf SYS System Clock(Crystal OSC,RC OSC)¾ 2.2V~5.5V400¾4000kHz ¾ 3.3V~5.5V400¾8000kHzf TIMER Timer I/P Frequency ¾ 2.2V~5.5V0¾4000kHz ¾ 3.3V~5.5V0¾8000kHzt WDTOSC Watchdog Oscillator Period3V¾4590180m s5V¾3265130m st WDT1Watchdog Time-out Period(WDT RC OSC)3VWithout WDT prescaler112346ms 5V81733mst WDT2Watchdog Time-out Period(System Clock/4)¾Without WDT prescaler¾1024¾t SYS t RES External Reset Low Pulse Width¾¾1¾¾m st SST System Start-up Timer Period¾Wake-up from HALT¾1024¾t SYSt INT Interrupt Pulse Width¾¾1¾¾m st LVR Low Voltage Reset Time¾¾0.2512ms Note:*t SYS=1/f SYSRev.1.204October15,2007Functional DescriptionExecution FlowThe system clock for the microcontroller is derived from either a crystal or an RC oscillator.The system clock is internally divided into four non-overlapping clocks.One instruction cycle consists of four system clock cycles.Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de-coding and execution takes the next instruction cycle. However,the pipelining scheme causes each instruc-tion to effectively execute in a cycle.If an instruction changes the program counter,two cycles are required to complete the instruction.Program Counter-PCThe program counter,PC controls the sequence in which the instructions stored in program ROM are exe-cuted and its contents specify full range of program memory.After accessing a program memory word to fetch an in-struction code,the contents of the program counter are incremented by one.The program counter then points to the memory word containing the next instruction code.When executing a jump instruction,a conditional skip execution,loading the PCL register,a subroutine call, an initial reset,an internal interrupt,an external interrupt or return from a subroutine,the PC manipulates the pro-gram transfer by loading the address corresponding to each instruction.The conditional skip is activated by instructions.Once the condition is met,the next instruction,fetched during the current instruction execution,is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise the program will proceed with the next in-struction.The lower byte of the program counter,PCL is a read-able and writable register.Moving data into the PCL per-forms a short jump.The destination must be within the current Program Memory Page.When a control transfer takes place,an additional dummy cycle is required.Execution FlowModeProgram Counter*9*8*7*6*5*4*3*2*1*0Initial Reset0000000000 External Interrupt00000000100 External Interrupt10000001000 Timer/Event Counter Overflow0000001100 External RC Oscillation Converter Interrupt0000010000 Skip Program Counter+2Loading PCL*9*8@7@6@5@4@3@2@1@0 Jump,Call Branch#9#8#7#6#5#4#3#2#1#0 Return from Subroutine S9S8S7S6S5S4S3S2S1S0Program CounterNote:*9~*0:Program Counter bits S9~S0:Stack register bits#9~#0:Instruction code bits@7~@0:PCL bitsRev.1.205October15,2007Program MemoryThe program memory is used to store the program in-structions which are to be executed.It also contains data,table,and interrupt entries,and is organized into 1024´14bits,addressed by the program counter and ta-ble pointer.Certain locations in the program memory are reserved for special usage:·Location000HThis area is reserved for program initialisation.After a device reset,the program always begins execution at location000H.·Location004HThis location is reserved for the external interrupt0 service program.If the INT0input pin is activated,the interrupt is enabled and the stack is not full,the pro-gram begins execution at this location.·Location008HThis location is reserved for the external interrupt1 service program.If the INT1input pin is activated,the interrupt is enabled and the stack is not full,the pro-gram begins execution at this location.·Location00CHThis location is reserved for the Timer/Event Counter interrupt service program.If a Timer interrupt results from a Timer/Event Counter overflow,and the inter-rupt is enabled and the stack is not full,the program begins execution at this location.·Location010HThis location is reserved for the external RC oscilla-tion converter interrupt service program.If an interrupt results from an external RC oscillation converter,and if the interrupt is enabled and the stack is not full,the program begins execution at this location.·Table locationAny location in the program memory can be used as a look-up table.The instructions²TABRDC[m]²(the current page,1page=256words)and²TABRDL[m]²transfer the contents of the lower-order byte to the specified data memory,and the higher-order byte to TBLH.Only the destination of the lower-order byte in the table is well-defined,the other bits of the table word are transferred to the lower portion of TBLH,and the remaining2bits are read as²0².The Table Higher-order byte register,TBLH,is read only.The ta-ble pointer,TBLP,is a read/write register,which indi-cates the table location.Before accessing the table, the location must be placed in TBLP.The TBLH regis-ter is read only and cannot be restored.If the main routine and the ISR(Interrupt Service Routine)both employ the table read instruction,the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR and errors may occur.Therefore,using the table read instruction in the main routine and also in the ISR should be avoided.However,if the table read instruction has to be used in both the main routine and in the ISR,the in-terrupt should be disabled prior to the table read in-struction execution.The interrupt should not be re-enabled until TBLH has been backed up.All table related instructions require two cycles to complete the operation.These areas may function as normal pro-gram memory depending upon the requirements.Stack Register-STACKThis is a special part of the memory which is used to save the contents of the program counter only.The stack is organised into4-levels and is neither part of the data nor part of the program space,and is neither readable nor writable.The activated level is indexed by the stack pointer,SP and is neither readable nor writeable.At a subroutine call or interrupt acknowledgment,the con-tents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,signaledProgram MemoryInstructionTable Location*9*8*7*6*5*4*3*2*1*0TABRDC[m]P9P8@7@6@5@4@3@2@1@0 TABRDL[m]11@7@6@5@4@3@2@1@0Table LocationNote:*9~*0:Table location bits P9~P8:Current program counter bits @7~@0:Table pointer bitsRev.1.206October15,2007by a return instruction,RET or RETI,the program counter is restored to its previous value from the stack.After a de-vice reset,the stack pointer will point to the top of the stack.If the stack is full and a non-masked interrupt takes place,the interrupt request flag will be recorded but the acknowledgment will be inhibited.When the stack pointer is decremented,by RET or RETI,the interrupt will be serviced.This feature prevents stack overflow al-lowing the programmer to use the structure more easily. In a similar case,if the stack is full and a²CALL²is sub-sequently executed,stack overflow occurs and the first entry will be lost as only the most recent4return ad-dresses are stored.Data Memory-RAMThe data memory has a capacity of111´8bits.The data memory is divided into two functional groups:special function registers and general purpose data memory (88´8).Most are read/write,but some are read only.The general purpose data memory,addressed from28H to7FH,is used for data and control information under in-struction commands.All of the data memory areas can handle arithmetic, logic,increment,decrement and rotate operations di-rectly.Except for some dedicated bits,each bit in the data memory can be set and reset by the²SET[m].i²and²CLR[m].i²bit manipulation instructions.They are also indirectly accessible through the memory pointer registers(MP0;01H,MP1;02H).Indirect Addressing RegisterThe method of indirect addressing allows data manipu-lation using memory pointers instead of the usual direct memory addressing method where the actual memory address is defined.Any action on the indirect address-ing registers will result in corresponding read/write oper-ations to the memory location specified by the corresponding memory pointers.This device contains two indirect addressing registers known as IAR0and IAR1and two memory pointers MP0and MP1.Note that these indirect addressing registers are not physically implemented and that reading the indirect addressingregisters indirectly will return a result of²00H²and writ-ing to the registers indirectly will result in no operation.The two memory pointers,MP0and MP1,are physically implemented in the data memory and can be manipu-lated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant indirect addressing registers is carried out,the actual address that the microcontroller is directed to is the address specified by the related memory pointer.Bit7of the memory pointers are not implemented.How-ever,it must be noted that when the memory pointers in this device is read,a value of²1²will be read.AccumulatorThe accumulator is closely related to ALU operations.It is also mapped to location²05H²of the data memory and can carry out immediate data operations.The data movement between two data memory locations must pass through the accumulator.RAM MappingRev.1.207October15,2007Arithmetic and Logic Unit-ALUThis circuit performs8-bit arithmetic and logic opera-tions.The ALU provides the following functions:·Arithmetic operations-ADD,ADC,SUB,SBC,DAA ·Logic operations-AND,OR,XOR,CPL ·Rotation-RL,RR,RLC,RRC·Increment and Decrement-INC,DEC·Branch decision-SZ,SNZ,SIZ,SDZ....The ALU not only saves the results of a data operation but also changes the status register.Status Register-STATUSThis8-bit register contains the zero flag(Z),carry flag (C),auxiliary carry flag(AC),overflow flag(OV),power down flag(PDF),and watchdog time-out flag(TO).It also records the status information and controls the op-eration sequence.With the exception of the TO and PDF flags,bits in the status register can be altered by instructions like most other registers.Any data written into the status register will not change the TO or PDF flag.In addition opera-tions related to the status register may give different re-sults from those intended.The TO flag can be affected only by a system power-up,a WDT time-out or execut-ing the²CLR WDT²or²HALT²instruction.The PDF flag can be affected only by executing a ²HALT²or²CLR WDT²instruction or a system power-up.The Z,OV,AC and C flags generally reflect the status of the latest operations.In addition,on entering the interrupt sequence or exe-cuting the subroutine call,the status register will not be pushed onto the stack automatically.If the contents of the status are important and if the subroutine can cor-rupt the status register,precautions must be taken to save it properly.InterruptThe devices provides two external interrupts,one inter-nal8-bit timer/event counter interrupt and one external RC oscillation converter interrupt.The interrupt control register0,INTC0,and interrupt control register1, INTC1,both contain the interrupt control bits that are used to set the enable/disable and interrupt request flags.Once an interrupt subroutine is serviced,all the other in-terrupts will be blocked,as the EMI bit will be cleared au-tomatically.However this scheme may prevent further interrupt nesting.Other interrupt requests may happen during this interval but only the interrupt request flag is recorded.If a certain interrupt requires servicing within the service routine,the EMI bit and the corresponding bit of the INTC0and INTC1registers may be set to allow interrupt nesting.If the stack is full,the interrupt request will not be ac-knowledged,even if the related interrupt is enabled,un-til the Stack Pointer is decremented.If immediate service is desired,the stack must be prevented from be-coming full.All interrupts have a wake-up capability.As an interrupt is serviced,a control transfer occurs by pushing the pro-gram counter onto the stack,followed by a branch to a subroutine at a specified location in the program mem-ory.Only the program counter is pushed onto the stack. If the contents of the accumulator or status register are altered by the interrupt service program,this may cor-rupt the desired control sequence,therefore their con-tents should be saved in advance.External interrupts are triggered by an edge transition on pins INT0or INT1.A configuration option enables these pins as interrupts and selects if they are active on high to low or low to high transitions.If active their re-lated interrupt request flag,EIF0;bit4in INTC0,and EIF1;bit5in INTC0,will be set.After the interrupt is en-Bit bel Function0C C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation;otherwise C is cleared.C is also affected by a rotate through carry instruction.1AC AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction;otherwise AC is cleared.2Z Z is set if the result of an arithmetic or logic operation is zero;otherwise Z is cleared.3OV OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit,or vice versa;otherwise OV is cleared.4PDF PDF is cleared by system power-up or executing the²CLR WDT²instruction. PDF is set by executing the²HALT²instruction.5TO TO is cleared by system power-up or executing the²CLR WDT²or²HALT²instruction. TO is set by a WDT time-out.6~7¾Unused bit,read as²0²Status(0AH)RegisterRev.1.208October15,2007abled,the stack is not full,and the external interrupt is active,a subroutine call to location²04H²or²08H²will occur.The interrupt request flags,EIF0or EIF1,and the EMI bit will all be cleared to disable other interrupts.The internal Timer/Event Counter interrupt is initialised by setting the Timer/Event Counter interrupt request flag,TF;bit6in INTC0.A timer interrupt will be gener-ated when the timer overflows.After the interrupt is en-abled,and the stack is not full,and the TF bit is set,a subroutine call to location²0CH²will occur.The related interrupt request flag,TF,is reset,and the EMI bit is cleared to disable other interrupts.The external RC oscillation converter interrupt is initial-ized by setting the external RC oscillation converter in-terrupt request flag,RCOCF;bit4of INTC1.This is caused by a Timer A or Timer B overflow.When the in-terrupt is enabled,and the stack is not full and the RCOCF bit is set,a subroutine call to location²10H²will occur.The related interrupt request flag,RCOCF,will be reset and the EMI bit cleared to disable further inter-rupts.During the execution of an interrupt subroutine,other in-terrupt acknowledgments are held until the²RETI²in-struction is executed or the EMI bit and the related interrupt control bit are set to1,if the stack is not full.To return from the interrupt subroutine,a²RET²or²RETI²instruction may be invoked.RETI will set the EMI bit to enable an interrupt service,but RET will not.Interrupts,occurring in the interval between the rising edges of two consecutive T2pulses,will be serviced on the latter of the two T2pulses,if the corresponding inter-rupts are enabled.In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit.Interrupt Source Priority Vector External Interrupt0104H External Interrupt1208H Timer/Event Counter Overflow30CH External RC OscillationConverter Interrupt410HInterrupt PriorityThe EMI,EEI0,EEI1,ETI and ERCOCI bits are all used to control the enable/disable status of interrupts.These bits prevent the requested interrupt from being serviced. Once the interrupt request flags,TF,RCOCF,EIF1and EIF0,are all set,they remain in the INTC1or INTC0reg-isters respectively until the interrupts are serviced or cleared by a software instruction.It is recommended that a program does not use the ²CALL subroutine²within the interrupt subroutine.Inter-rupts often occur in an unpredictable manner or need to be serviced immediately in some applications.If only one stack is left and enabling the interrupt is not well con-trolled,the original control sequence may be damaged once the²CALL²is executed in the interrupt subroutine.Bit bel Function0EMI Controls the master(global)interrupt(1=enabled;0=disabled)1EEI0Controls the external interrupt0(1=enabled;0=disabled)2EEI1Controls the external interrupt1(1=enabled;0=disabled)3ETI Controls the Timer/Event Counter interrupt(1=enabled;0=disabled)4EIF0External interrupt0request flag(1=active;0=inactive)5EIF1External interrupt1request flag(1=active;0=inactive)6TF Internal Timer/Event Counter request flag(1=active;0=inactive)7¾Unused bit,read as²0²INTC0(0BH)RegisterBit bel Function0ERCOCI Controls the external RC oscillation converter interrupt(1=enabled;0=disabled)1~3,5~7¾Unused bit,read as²0²4RCOCF External RC oscillation converter request flag(1=active;0=inactive)INTC1(1EH)RegisterRev.1.209October15,2007Oscillator ConfigurationThere are two oscillator circuits in the microcontroller.Both are designed for system clocks,namely the RC os-cillator and the Crystal oscillator,the choice of which is determined by a configuration option.When the device enters the Power-down Mode,the system oscillator will stop running and will ignore external signals to conserve power.If an RC oscillator is used,an external resistor between OSC1and VDD is required to produce oscillation.The resistance must range from24k W to1M W.The system clock,divided by4,is available on OSC2,which can be used to synchronize external logic.The RC oscillator provides the most cost effective solution,however,the frequency of oscillation may vary with VDD,tempera-tures and the device itself due to process variations.It is, therefore,not suitable for timing sensitive operations where an accurate oscillator frequency is desired.If the Crystal oscillator is used,a crystal across OSC1 and OSC2is needed to provide the feedback and phase shift required for the oscillator.No other external compo-nents are required.Instead of a crystal,a resonator can also be connected between OSC1and OSC2to get a frequency reference,but two external capacitors con-nected between OSC1,OSC2and ground are required, if the oscillator frequency is less than1MHz.The WDT oscillator is a free running on-chip RC oscilla-tor which requires no external components.Even if the system enters the Power Down Mode,where the sys-tem clock is stopped,the WDT oscillator will continue to operate with a period of approximately65m s at5V.The WDT oscillator can be disabled by a configuration option to conserve power.Watchdog Timer-WDTThe WDT clock can be sourced from its own dedicated internal oscillator(WDT oscillator),or from the or in-struction clock,which is the system clock divided by4. The choice is determined via a configuration option.The WDT timer is designed to prevent a software malfunc-tion or sequence from jumping to an unknown location with unpredictable results.The Watchdog Timer can be disabled by a configuration option.If the Watchdog Timer is disabled,any executions related to the WDT re-sult in no operation.The WDT clock source is first divided by256.If the inter-nal WDT oscillator is used,this gives a nominal time-out period of approximately17ms at5V.This time-out pe-riod may vary with temperatures,VDD and process vari-ations.By using the WDT prescaler,longer time-out periods can be realised.Writing data to the WS2,WS1, WS0bits in the WDTS register,can give different time-out periods.If WS2,WS1and WS0are all equal to 1,the division ratio will be1:128,and the maximum time-out period will be2.1s at5V.If the internal WDT os-cillator is disabled,the WDT clock may still come from the instruction clock and operate in the same manner except that in the Power Down state the WDT will stop counting and lose its protecting purpose.The high nib-ble and bit3of the WDTS can be used for user defined flags.If the device operates in a noisy environment,using the internal WDT oscillator is the recommended choice, since the HALT instruction will stop the system clock.WS2WS1WS0Division Ratio0001:10011:20101:40111:81001:161011:321101:641111:128WDTS(09H)RegisterThe WDT overflow under normal operation will generate a²chip reset²and set the status bit²TO².But in the Power Down mode,the overflow will generate a²warm reset²,where only the Program Counter and Stack Pointer are reset to zero.To clear the contents of the WDT,including the WDT prescaler,three methods can be used;an external reset(a low level to RES),a soft-ware instruction and a²HALT²instruction.The software instruction includes²CLR WDT²instruction and the in-struction pair-²CLR WDT1²and²CLR WDT2².Of these two types of instruction,only one can be active de-pending on the configuration option-²CLR WDT times selection option².If the²CLR WDT²is selected,i.e. CLRWDT times equal one,any execution of the²CLR WDT²instruction will clear the WDT.In the case that ²CLR WDT1²and²CLR WDT2²are chosen,i.e. CLRWDT times equal two,these two instructions must be executed to clear the WDT;otherwise,the WDT may reset the chip as a result of a time-out.System OscillatorRev.1.2010October15,2007。