AD5726YRWZ-REEL7中文资料

READ OperationREAD bursts are initiated with a READ command. The starting column and bank ad-dresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled,the row will be left open after the completion of the burst.During READ bursts, the valid data-out element from the starting column address is available READ latency (RL) clocks later. RL is defined as the sum of posted CAS additive latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma-ble in the mode register via the MRS command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK#). Figure 69 shows an example of RL based on a CL setting of 8 and an AL setting of 0.Figure 69: READ LatencyCKCK#CommandAddressDQDQS, DQS#Don’t CareTransitioning Data Indicates break in time scaleNotes:1.DO n = data-out from column n .2.Subsequent elements of data-out appear in the programmed order following DO n .DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on DQS and HIGH state on DQS# is known as the READ preamble (t RPRE). The LOW state on DQS and the HIGH state on DQS#, coincident with the last data-out element, isknown as the READ postamble (t RPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ goes High-Z. A detailed explanation of t DQSQ (valid data-out skew), t QH (data-out window hold), and the valid data window are de-picted in Figure 80 (page 171). A detailed explanation of t DQSCK (DQS transition skew to CK) is also depicted in Figure 80 (page 171).Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued t CCD cycles after the first READ command. This is shown for BL8 in Figure 70(page 165). If BC4 is enabled, t CCD must still be met, which will cause a gap in the data output, as shown in Figure 71 (page 165). Nonconsecutive READ data is reflected in Figure 72 (page 166). DDR3 SDRAM does not allow interrupting or truncating any READ burst.Figure 100: Precharge Power-Down (Slow-Exit Mode) Entry and ExitCKCK#CommandCKEEnter power-downmode Exit power-downmodeDon’t CareIndicates break in time scaleNotes:1.Any valid command not requiring a locked DLL.2.Any valid command requiring a locked DLL.Figure 101: Power-Down Entry After READ or READ with Auto Precharge (RDAP)Don’t CareTransitioning Data CKCK#Command DQ BL8DQ BC4DQS, DQS#Address CKEPower-down or self refresh entryIndicates break in time scaleFigure 102: Power-Down Entry After WRITECKCK#Command DQ BL8DQ BC4DQS, DQS#AddressCKEself refresh entry1Don’t CareTransitioning Data Indicates break in time scaleNote:1.CKE can go LOW 2t CK earlier if BC4MRS.Figure 103: Power-Down Entry After WRITE with Auto Precharge (WRAP)Don’t CareTransitioning Data CKCK#CommandDQ BL8DQ BC4DQS, DQS#Address A10CKEPower-down or self refresh entry 2Start internal precharge Indicates break in time scaleNotes:1.t WR is programmed through MR0[11:9] and represents t WRmin (ns)/t CK rounded up tothe next integer t CK.2.CKE can go LOW 2t CK earlier if BC4MRS.Figure 104: REFRESH to Power-Down EntryCKCK#CommandCKET0T1T2T3Ta0Ta1Ta2Tb0Don’t CareIndicates break in time scaleNote:1.After CKE goes HIGH during t RFC, CKE must remain HIGH until t RFC is satisfied.Figure 105: ACTIVATE to Power-Down EntryCKCK#Command Address CKET0T1T2T3T4T5T6T7Figure 108: Power-Down Exit to Refresh to Power-Down EntryCKCK#CKET0T1T2T3T4Ta0Ta1Tb0Command。

Complete Quad, 16-Bit, High Accuracy,Serial Input, Bipolar Voltage Output DACAD5764R Rev. PrAInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.FEATURESComplete quad, 16-bit digital-to-analog converters (DACs)Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V±1 LSB max INL error, ±1 LSB max DNL error Low noise: 60 nV/√HzSettling time: 10 μs maxIntegrated reference buffersInternal reference: 10 ppm/°COn-chip die temperature sensorOutput control during power-up/brownout Programmable short-circuit protection Simultaneous updating via LDACDigital offset and gain adjustLogic output control pinsDSP-/microcontroller-compatible serial interface Temperature range: −40°C to +85°Ci CMOS™ process technology1 APPLICATIONSIndustrial automationOpen-/closed-loop servo controlProcess controlData acquisition systemsAutomatic test equipmentAutomotive test and measurementHigh accuracy instrumentation GENERAL DESCRIPTIONThe AD5764R is a quad, 16-bit, serial input, bipolar voltage output digital-to-analog converter that operates from supply voltages of ±11.4 V up to ±16.5 V. Nominal full-scale output range is ±10 V. The AD5764R provides integrated output amplifiers, reference buffers and proprietary power-up/power-down control circuitry. The parts also feature a digital I/O port, which is programmed via the serial interface and an analog temperature sensor. The part incorporates digital offset and gain adjust registers per channel.The AD5764R is a high performance converter that offers guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB, low noise, and 10 μs settling time. The AD5764R includes an on-chip 5 V reference with a reference tempco of 10 ppm/°C maximum. During power-up (when the supply voltages are changing), VOUT is clamped to 0 V via a low impedance path. The AD5764R uses a serial interface that operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears all DAC registers to either bipolar zero or zero scale depending on the coding used. The AD5764R is ideal for both closed-loop servo control and open-loop control applications. The AD5764R is available in a 32-lead TQFP, and offers guaranteed specifications over the −40°C to +85°C industrial temperature range. See Figure 1, the functional block diagram.1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, i CMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, and increased AC and DC performance.AD5764RRev. PrA | Page 2 of 32TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Revision History...............................................................................2 Functional Block Diagram..............................................................3 Specifications.....................................................................................4 AC Performance Characteristic......................................................6 Timing Characteristics.....................................................................7 Absolute Maximum Ratings..........................................................10 ESD Caution................................................................................10 Pin Configuration and Function Descriptions...........................11 Terminology....................................................................................13 Typical Performance Characteristics...........................................15 Theory of Operation......................................................................20 DAC Architecture.......................................................................20 Reference Buffers........................................................................20 Serial Interface............................................................................20 Simultaneous Updating via LDAC ...........................................21 Transfer Function.......................................................................22 Asynchronous Clear (CLR ).......................................................22 Function Register.......................................................................23 Data Register...............................................................................24 Coarse Gain Register.................................................................24 Fine Gain Register......................................................................24 Offset Register............................................................................24 Offset and Gain Adjustment Worked Example......................26 AD5764R Features..........................................................................27 Analog Output Control.............................................................27 Digital Offset and Gain Control...............................................27 Programmable Short-Circuit Protection................................27 Digital I/O Port...........................................................................27 Die Temperature Sensor............................................................27 Local Ground Offset Adjust......................................................27 Applications Information..............................................................28 Typical Operating Circuit.........................................................28 Layout Guidelines...........................................................................29 Galvanically Isolated Interface.................................................29 Microprocessor Interfacing.......................................................29 Evaluation Board........................................................................31 Outline Dimensions.......................................................................32 Ordering Guide.. (32)REVISION HISTORY3/06—Revision PrAAD5764RRev. PrA | Page 3 of 32FUNCTIONAL BLOCK DIAGRAMAGNDDVOUTDAGNDCVOUTCAGNDBVOUTBAGNDAVOUTAISCC06064-001Figure 1. Functional Block DiagramAD5764RRev. PrA | Page 4 of 32SPECIFICATIONSAV DD = 11.4 V to 16.5 V , AV SS = −11.4 V to −16.5 V , AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external; DV CC = 2.7 V to 5.25 V , R LOAD = 10 kΩ, C L = 200 pF. All specifications T MIN to T MAX , unless otherwise noted. Table 1.Parameter A Grade 2 B Grade 2 C Grade 2UnitTest Conditions/Comments ACCURACY Outputs unloaded Resolution 16 16 16 Bits Relative Accuracy (INL) ±4 ±2 ±1 LSB maxDifferential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic Bipolar Zero Error ±2 ±2 ±2 mV maxAt 25°C; error at othertemperatures obtained using bipolar zero TCBipolar Zero TC 3±2 ±2 ±2 ppm FSR/°C max Zero-Scale Error±2 ±2 ±2mV max At 25°C; error at othertemperatures obtained using zero scale TCZero-Scale TC 3±2 ±2 ±2 ppm FSR/°C max Gain Error ±0.02 ±0.02 ±0.02% FSR max At 25°C; error at othertemperatures obtained using gain TCGain TC 3 ±2 ±2 ±2 ppm FSR/°C max DC Crosstalk 30.5 0.5 0.5 LSB max REFERENCE INPUT/OUTPUTReference Input 3Reference Input Voltage 5 5 5 V nominal ±1% for specified performance DC Input Impedance 1 1 1 MΩ min Typically 100 MΩ Input Current ±10 ±10 ±10 μA max Typically ±30 nA Reference Range 1/7 1/7 1/7 V min/V max Reference Output Output Voltage 4.997/5.003 4.997/5.003 4.997/5.003 V min/V max At 25°C Reference TC ±10 ±10 ±10 ppm/°C maxLoad 3 1 1 1M Ω minOutput Noise 3(0.1 Hz to 10 Hz) 18 18 18 μV p-p typ Noise Spectral Density 375 75 75 nV/√Hz typ At 10 kHz OUTPUT CHARACTERISTICS 3Output Voltage Range 4±10.5263 ±10.5263 ±10.5263 V min/V max AV DD /AV SS = ±11.4 V, REFIN = 5V ±14 ±14 ±14 V min/V maxAV DD /AV SS = ±16.5 V, REFIN = 7V Output Voltage Drift vs. Time ±13 ±13 ±13 ppm FSR/500 hours typ±15 ±15 ±15 ppm FSR/1000 hours typShort Circuit Current 10 10 10 mA typ RI SCC = 6 kΩ, see Figure 31Load Current±1 ±1 ±1 mA max For specified performance Capacitive Load StabilityR L = ∞ 200 200 200 pF max R L = 10 kΩ1000 1000 1000 pF max DC Output Impedance0.30.30.3Ω maxAD5764RRev. PrA | Page 5 of 32Parameter A Grade 2 B Grade 2 C Grade 2Unit Test Conditions/Comments DIGITAL INPUTS 3 DV CC = 2.7 V to 5.25 V, JEDEC compliant V IH , Input High Voltage 22 2 V min V IL , Input Low Voltage 0.8 0.8 0.8 V maxInput Current ±1 ±1 ±1 μA max Per pin Pin Capacitance10 10 10 pF max Per pin DIGITAL OUTPUTS (D0, D1, SDO)3Output Low Voltage 0.40.40.4V max DV CC = 5 V ± 5%, sinking 200 μA Output High Voltage DV CC − 1 DV CC − 1 DV CC − 1 V min DV CC = 5 V ± 5%, sourcing 200 μA Output Low Voltage 0.4 0.4 0.4 V max DV CC = 2.7 V to 3.6 V, sinking 200 μA Output High VoltageDV CC − 0.5DV CC − 0.5DV CC − 0.5V min DV CC = 2.7 V to 3.6 V, sourcing 200 μA High Impedance LeakageCurrent±1 ±1 ±1 μA max SDO only High Impedance OutputCapacitance5 5 5 pF typSDO onlyDIE TEMPERATURE SENSOR 3Output Voltage at 25°C 1.4 1.4 1.4 V typDie temperature Output Voltage Scale Factor 5 5 5 mV/°C typOutput Voltage Range 1.175/1.9 1.175/1.9 1.175/1.9 V min/V max −40°C to 105°C Output Load Current 200 200 200 μA max Current source only Power-On Time 80 80 80 ms typPOWER REQU I REMENTS AV DD /AV SS 11.4/16.5 11.4/16.5 11.4/16.5 V min/V max DV CC 2.7/5.25 2.7/5.25 2.7/5.25 V min/V max Power Supply Sensitivity 3∆V OUT /∆ΑV DD −85 −85 −85 dB typAI DD 3.5 3.5 3.5 mA/channel max Outputs unloaded AI SS 2.75 2.75 2.75 mA/channel max Outputs unloadedDI CC 1.2 1.2 1.2 mA max V IH = DV CC , V IL = DGND, 750 μA typ Power Dissipation 275 275 275mW typ±12 V operation output unloaded2 Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance. 3Guaranteed by design and characterization; not production tested. 4Output amplifier headroom requirement is 1.4 V minimum.AD5764RAC PERFORMANCE CHARACTERISTICAV DD = 11.4 V to 16.5 V, AV SS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external; DV CC = 2.7 V to 5.25 V, R LOAD = 10 kΩ, C L = 200 pF. All specifications T MIN to T MAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.1 Guaranteed by design and characterization; not production tested.2 Includes noise contributions from integrated reference buffers, 14-, 16-bit DAC and output amplifier.Rev. PrA | Page 6 of 32AD5764RTIMING CHARACTERISTICSAV DD = 11.4 V to 16.5 V, AV SS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;DV CC = 2.7 V to 5.25 V, R LOAD = 10 kΩ, C L = 200 pF. All specifications T MIN to T MAX, unless otherwise noted.1 Guaranteed by design and characterization; not production tested.2 All input signals are specified with t r = t f = 5 ns (10% to 90% of DV CC) and timed from a voltage level of 1.2 V.3 See Figure 2, Figure 3, and Figure 4.4 Standalone mode only.5 Measured with the load circuit of Figure 5.6 Daisy-chain mode only.Rev. PrA | Page 7 of 32AD5764RRev. PrA | Page 8 of 3206064-002Figure 2. Serial Interface Timing DiagramLDACSDOSDINSYNCSCLK06064-003Figure 3. Daisy Chain Timing DiagramAD5764RRev. PrA | Page 9 of 32SDOSDINSYNCSCLK2448DB23DB0DB23DB0DB23UNDEFINEDNOP CONDITIONDB0INPUT WORD SPECIFIES REGISTER TO BE READSELECTED REGISTER DATACLOCKED OUT06064-004Figure 4. Readback Timing DiagramV OH (MIN) OR V OL (MAX)06064-005Figure 5. Load Circuit for SDO Timing DiagramAD5764RRev. PrA | Page 10 of 32ABSOLUTE MAXIMUM RATINGST A = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.Table 4.Parameter RatingAV DD to AGND, DGND −0.3 V to +17 VAV SS to AGND, DGND +0.3 V to −17 VDV CC to DGND−0.3 V to +7 VDigital Inputs to DGND−0.3 V to DV CC + 0.3 V or 7 V (whichever is less)Digital Outputs to DGND −0.3 V to DV CC + 0.3 V REFIN to AGND, PGND −0.3 V to AV DD + 0.3V REFOUT to AGND AV SS to AV DD TEMP AV SS to AV DDVOUTA, VOUTB, VOUTC, VOUTD toAGNDAV SS to AV DD AGND to DGND −0.3 V to +0.3 V Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (T Jmax) 150°C 32-Lead TQFP θJA Thermal Impedance 65°C/W θJC Thermal Impedance 12°C/W Reflow Soldering Peak Temperature 220°C Time at Peak Temperature 10 sec to 40 secStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sectionsof this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affectdevice reliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.AD5764RPIN CONFIGURATION AND FUNCTION DESCRIPTIONSAGNDA VOUTA VOUTB AGNDB AGNDC VOUTC VOUTD AGNDD06064-006Figure 6. Pin ConfigurationIAD5764R1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.AD5764R TERMINOLOGYRelative Accuracy or Integral nonlinearity (INL)For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 7. Differential Nonlinearity (DNL)Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic. A typical DNL vs. code plot can be seen in Figure 9. MonotonicityA DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5764R is monotonic over its full operating temperature range.Bipolar Zero ErrorBipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (offset binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Figure 22.Bipolar Zero TCBipolar zero TC is the measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C.Full-Scale ErrorFull-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally the output voltage should be 2 × V REF − 1 LSB. Full-scale error is expressed in percentage of full-scale range.Negative Full-Scale Error/Zero Scale ErrorNegative full-scale error is the error in the DAC output voltage when 0x0000 (offset binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be −2 × V REF. A plot of zero-scale error vs. temperature can be seen in Figure 21.Output Voltage Settling TimeOutput voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change.Slew RateThe slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage-output D/A converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/μs. Gain ErrorGain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. A plot of gain error vs. temperature can be seen in Figure 23.Total Unadjusted ErrorTotal unadjusted error (TUE) is a measure of the output error considering all the various errors. A plot of total unadjusted error vs. reference can be seen in Figure 19.Zero-Scale Error TCZero-scale error TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C.Gain Error TCGain error TC is a measure of the change in gain error with changes in temperature. Gain Error TC is expressed in(ppm of FSR)/°C.Digital-to-Analog Glitch EnergyDigital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 28).Digital FeedthroughDigital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.Power Supply SensitivityPower supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage.DC CrosstalkDC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC, and is expressed in LSBs.DAC-to-DAC CrosstalkDAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s.AD5764RChannel-to-Channel IsolationChannel-to-channel isolation is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dB.Reference TCReference TC is a measure of the change in the reference output voltage with a change in temperature. It is expressed in ppm/°C. Digital CrosstalkDigital crosstalk is a measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.AD5764RTYPICAL PERFORMANCE CHARACTERISTICS1.0–1.0–0.8–0.6–0.4–0.200.20.40.60.80100002000030000400005000060000I N L E R R O R (L S B )DAC CODE06064-007Figure 7. Integral Nonlinearity Error vs. Code,V DD /V SS = ±15 V1.0–1.0–0.8–0.6–0.4–0.200.20.40.60.80100002000030000400005000060000I N L E R RO R (L S B )DAC CODE06064-008Figure 8. Integral Nonlinearity Error vs. Code,V DD /V SS = ±12 V1.0–1.0–0.8–0.6–0.4–0.200.20.40.60.80100002000030000400005000060000D N LE R RO R (L S B )DAC CODE06064-011Figure 9. Differential Nonlinearity Error vs. Code,V DD /V SS = ±15 V 1.0–1.0–0.8–0.6–0.4–0.200.20.40.60.80100002000030000400005000060000D N LE RR O R (L S B )DAC CODE06064-012Figure 10. Differential Nonlinearity Error vs. Code,V DD /V SS = ±12 V0.50.40.30.20.1–0.2–0.10–40100–20020406080I N L E RR O R (L S B )TEMPERATURE (°C)06064-015Figure 11. Integral Nonlinearity Error vs. Temperature,V DD /V SS = ±15 V0.50.40.30.20.1–0.1–40100–20020406080I N L E R RO R (L S B )TEMPERATURE (°C)06064-016Figure 12. Integral Nonlinearity Error vs. Temperature,V DD /V SS = ±12 VAD5764R0.150.100.05–0.25–0.20–0.15–0.10–0.050–40100–20020406080D N L E R R OR (L S B )TEMPERATURE (°C)06064-019Figure 13. Differential Nonlinearity Error vs. Temperature,V DD /V SS = ±15 V0.150.100.05–0.25–0.20–0.15–0.10–0.050–40100–20020406080D N L E R R O R (L S B )TEMPERATURE (°C)06064-020Figure 14. Differential Nonlinearity Error vs. Temperature,V DD /V SS = ±12 V0.50.40.30.20.10–0.2–0.111.416.415.414.413.412.4I N L E R R O R(L S B )SUPPLY VOLTAGE (V)06064-023Figure 15. Integral Nonlinearity Error vs. Supply Voltage0.15–0.25–0.20–0.15–0.10–0.0500.050.1011.416.415.414.413.412.4D N L E R R O R (L S B )SUPPLY VOLTAGE (V)06064-025Figure 16. Differential Nonlinearity Error vs. Supply Voltage0.8–1.0–0.8–0.6–0.4–0.200.20.40.61756432I N L E R R O R(L S B )REFERENCE VOLTAGE (V)06064-027Figure 17. Integral Nonlinearity Error vs. Reference Voltage, V DD /V SS =±16.5 V0.40.30.20.1–0.4–0.3–0.2–0.101756432D N LE R R O R(L S B )REFERENCE VOLTAGE (V)06064-031Figure 18. Differential Nonlinearity Error vs. Reference Voltage, V DD /V SS =±16.5 VAD5764R0.80.60.4–0.4–0.200.2–40100806040200–20B I P O L A R Z E R O E R R O R (m V )TEMPERATURE (°C)06064-039Figure 19. Total Unadjusted Error vs. Reference Voltage,V DD /V SS = ±16.5 V14131211109811.416.415.414.413.412.4C U RR E N T (m A )V DD /V SS (V)06064-037Figure 20. I DD /I SS vs. V DD /V SS0.25–0.25–0.20–0.15–0.10–0.0500.050.100.150.20–40100806040200–20Z E R O -S C A L E E R R O R (m V )TEMPERATURE (°C)06064-038Figure 21. Zero-Scale Error vs. Temperature 0.80.60.4–0.4–0.20.2–40100806040200–20B I P O L A R Z E R O E R R O R (m V )TEMPERATURE (°C)06064-039Figure 22. Bipolar Zero Error vs. Temperature1.40.60.81.01.20.4–0.200.2–40100806040200–20G A I N E R R O R (m V )TEMPERATURE (°C)06064-040Figure 23. Gain Error vs. Temperature0.00140.00130.00120.00110.00100.00090.00080.00070.000654.54.03.53.02.52.01.51.00.5D IC C (m A )V LOGIC.006064-041Figure 24. DI CC vs. Logic Input VoltageAD5764R700030004000500060002000–100001000–10105–5O U T P U T V O L T A G E (µV )SOURCE/SINK CURRENT (mA)06064-042Figure 25. Source and Sink Capability of Output Amplifier with PositiveFull Scale Loaded1000070008000900030004000500060002000–10001000–1283–2–7O U T P U T V O L T A GE (µV )SOURCE/SINK CURRENT (mA)06064-043Figure 26. Source and Sink Capability of Output Amplifier with NegativeFull Scale LoadedCH1 3.00VM1.00µsCH1 –120mV06064-044Figure 27. Full-Scale Settling Time –4–6–8–10–12–14–16–18–20–22–24–26–2.0–1.5–1.0–0.500.51.01.52.02.53.03.54.04.55.05.56.0V O U T (m V )TIME (µs)06064-047Figure 28. Major Code Transition Glitch Energy, V DD /V SS = ±12 VCH4 50.0µV M1.00s CH4 26µV06064-048Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth)CH1 10.0V B W CH3 10.0mV B WT 29.60%CH2 10.0VM100µs A CH1 7.80mV06064-055Figure 30. VOUT vs. V DD /V SS on Power-UpAD5764R10987654321012010080604020S H O R T -C I R C U I T C U R R E N T(m A )RI SCC (k Ω)06064-050Figure 31. Short-Circuit Current vs. RI SCCCH1 10.0V B W CH3 5.00V B WT 29.60%CH2 10.0V M400µs A CH1 7.80mV06064-054Figure 32. REFOUT Turn-On Transient CH1 50.0µV M1.00s A CH1 15µV06064-052Figure 33. REFOUT Output Noise 100 kHz BandwidthM1.00s A CH1 18mV06064-053Figure 34. REFOUT Output Noise 0.1 Hz to 10 HzAD5764RTHEORY OF OPERATIONThe AD5764R is a quad, 16-bit, serial input, bipolar voltage output DAC and operates from supply voltages of ±11.4 V to ±16.5 V and has a buffered output voltage of up to ±10.5263 V . Data is written to the AD5764R in a 24-bit word format, via a 3-wire serial interface. The AD5764R also offers an SDO pin, which is available for daisy chaining or readback.The AD5764R incorporates a power-on reset circuit, which ensures that the DAC registers power up loaded with 0x0000. The AD5764R features a digital I/O port that can beprogrammed via the serial interface, an analog die temperature sensor, on-chip 10 ppm/°C voltage reference, on-chip reference buffers and per channel digital gain and offset registers.DAC ARCHITECTUREThe DAC architecture of the AD5764R consists of a 16-bit current mode segmented R-2R DAC. The simplified circuit diagram for the DAC section is shown in Figure 35.The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of the 15 matched resistors to either AGND or IOUT. The remaining 12 bits of the data word drive switches S0 to S11 of the 12-bit R-2R ladder network.V REF12-BIT, R-2R LADDER4 MSBs DECODED INTO 15 EQUAL SEGMENTS06064-060Figure 35. DAC Ladder StructureREFERENCE BUFFERSThe AD5764R can operate with either an external or an internal reference. The reference inputs (REFAB and REFCD) have an input range up to 7 V . This input voltage is then used to provide a buffered positive and negative reference for the DAC cores. The positive reference is given by+ V REF = 2 × V REFWhile the negative reference to the DAC cores is given by−V REF = −2 × V REFThese positive and negative reference voltages (along with the gain register values) define the output ranges of the DACs.SERIAL INTERFACEThe AD5764R is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI®, QSPI™, MICROWIRE™, and DSP standards.Input Shift RegisterThe input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits and 16 data bits as shown in Table 7. The timing diagram for this operation is shown in Figure 2.Upon power-up, the DAC registers are loaded with zero code (0x0000) and the outputs are clamped to 0 V via a lowimpedance path. The outputs can be updated with the zero code value by asserting either LDAC or CLR . The corresponding output voltage depends on the state of the BIN/2sCOMP pin. If the BIN/2sCOMP pin is tied to DGND, then the data coding is twos complement and the outputs update to 0 V . If theBIN/2sCOMP pin is tied to DV CC , then the data coding is offset binary and the outputs update to negative full scale. To have the outputs power-up with zero code loaded to the outputs, the CLR pin should be held low during power-up.Standalone OperationThe serial interface works with both a continuous and noncon-tinuous serial clock. A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought back high again. If SYNC is brought high before the 24th falling SCLK edge, then the data written is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, then the input data is also invalid. The input register addressed is updated on the rising edge of SYNC . In order for another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register.When the data has been transferred into the chosen register of the addressed DAC, all DAC registers and outputs can be updated by taking LDAC low.。

Wide Supply Range, Rail-to-RailRev. PrAInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.FEATURESGain set with 1 external resistor Gain range: 1 to 1000Input voltage goes to ground Input overdrive protection Very wide power supply range Dual supply: ±1.3 V to ±18 V Single supply: 2.6 V to 36 V Bandwidth (G = 1): 800 kHz CMRR (G = 1): 78 dB minimum Input noise: 22 nV/rt(Hz) Typical supply current: 350 µA SOIC-8 and MSOP-8 packages APPLICATIONSIndustrial process controls Bridge amplifiersMedical instrumentation Portable data acquisition Multichannel systemsTOP VIEW(Not to Scale)736-1–INR GR G+IN+V SV OUTREF–V SFigure 1.GENERAL DESCRIPTIONThe AD8226 is a low cost instrumentation amplifier that requiresonly one external resistor to set any gain between 1 and 1000. The AD8226 is designed to work with a very wide range of voltages. It can operate on supplies ranging from ±1.2 V to±18 V (2.4 V to 36 V single supply). The AD8226 comes with rail-to-rail output and a wide input range that includes the ability to go slightly below the negative supply. In addition, the AD8226 inputs can withstand voltages beyond the rail.The AD8226 is perfect for multichannel, space-constrained applications. Being a low power and low cost amplifier allows multiple channels to be used.The AD8226 has three grades. The A grade is the lower cost version and is specified for temperatures from −40°C to +85°C. The B grade is the higher performance version and is specified from −40°C to +85°C. The C grade version is the higher temperature version and is specified from −40°C to +105°C. All models are operational from −40°C to +125°C; behavior at these temperatures is shown in the typical performance curves. The AD8226 is available in MSOP and SOIC packages.1Rail-to-rail output.Rev. PrA | Page 2 of 16TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Pin Configuration ............................................................................. 1 General Description ......................................................................... 1 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Theory of Operation ........................................................................ 9 Architecture ...................................................................................9 Gain Selection ................................................................................9 Input Protection ............................................................................9 Reference Terminal .................................................................... 10 Input Voltage Range ................................................................... 10 Layout .......................................................................................... 10 Input Bias Current Return Path ............................................... 11 Radio Frequency Interference (RFI) ........................................ 11 Outline Dimensions ....................................................................... 12 Ordering Guide .. (13)SPECIFICATIONS+V S = +15 V, −V S = −15 V, V REF = 0 V, T A = 25°C, G = 1, R L = 10 kΩ, unless otherwise noted.Rev. PrA | Page 3 of 16Rev. PrA | Page 4 of 161 Does not include the effects of external resistor R G2Input voltage range of the AD8226 input stage. Input range depends on common mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section in the Theory of Operation for more information.+V S = 2.7 V, –V S = 0 V, V REF = 0 V, T A = 25°C, G = 1, R L = 10 kΩ, unless otherwise noted.Rev. PrA | Page 5 of 16Rev. PrA | Page 6 of 161 Does not include the effects of external resistor R G2Input voltage range of the AD8226 input stage. Input range depends on common mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section in the Theory of Operation for more information.Rev. PrA | Page 7 of 16ABSOLUTE MAXIMUM RATINGS1Temperature range for specified performance is either −40°C to +85°C or −40°C to +105°C, depending on grade.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCEθJA is specified for a device in free air.Rev. PrA | Page 8 of 16PIN CONFIGURATION AND FUNCTION DESCRIPTIONSTOP VIEW (Not to Scale)07036-002–INR G R G +IN+V S V OUT REF –V SFigure 2. Pin ConfigurationRev. PrA | Page 9 of 16THEORY OF OPERATION07036-003AMPLIFIER STAGEGAIN STAGEFigure 3. Simplified SchematicARCHITECTUREThe AD8226 is based on the classic three op amp topology. This topology has two stages: a preamplifier to provide differential amplification, followed by a difference amplifier to remove the common-mode voltage. Figure 3 shows a simplified schematic of the AD8226.The first stage works as follows: in order to maintain a constant voltage across the Bias Resistor R B , Amplifier A1 must keep Node 3 a constant diode drop above the positive input voltage. Similarly, Amplifier A2 keeps Node 4 at a constant diode drop above the negative input voltage. Therefore a replica of the differential input voltage is placed across the gain setting resistor, R G . The current that flows across this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. Note that, in addition to a gained differential signal, the original common-mode signal, shifted a diode drop down, is also still present. The second stage is a difference amplifier, composed of A3 and four 50 kΩ resistors. The purpose of this stage is to remove the common-mode signal from the amplified differential signal. Because the input amplifiers employ a current feedback architecture, the gain-bandwidth product of the AD8226 increases with gain, resulting in a system that does not suffer from the expected bandwidth loss of voltage feedback architectures at higher gains.The transfer function of the AD8226 isV OUT = G (V IN+ − V IN−) + V REF whereGR G kΩ49.41+=GAIN SELECTIONPlacing a resistor across the R G terminals sets the gain of the AD8226, which can be calculated by referring to Table 7 or by using the following gain equation:1kΩ49.4−=G R GThe AD8226 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the R G resistor should be added to the AD8226’s specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal.INPUT PROTECTIONThe input terminals of the AD8226 have input protection that allows the input voltage to go beyond the rails without damaging the part. Maximum voltage is –Vs+40 V and minimum voltage is +Vs-40 V . For example: with ±15 Vsupplies, the part can withstand input voltages of ±25 V; with a 5 V single supply, maximum input voltage is 40 V and minimum input voltage is 35 V .Rev. PrA | Page 10 of 16REFERENCE TERMINALThe output voltage of the AD8226 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to level-shift the output so that the AD8226 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +V S or −V S by more than 0.3 V .For the best performance, source impedance to the REFterminal should be kept below 2 Ω. As shown in Figure 3, the reference terminal, REF, is at one end of a 50 kΩ resistor. Additional impedance at the REF terminal adds to this 50 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional R REF can be computed by 2(50 kΩ + R REF )/100 kΩ + R REF . Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR.INCORRECTCORRECTFigure 4. Driving the Reference PinINPUT VOLTAGE RANGEThe three op amp architecture of the AD8226 applies gain in the first stage before removing common-mode voltage in the difference amplifier stage. In addition, the input transistors in the first stage shift the common mode voltage up one diode drop (about 650 mV .) Therefore, internal nodes between the first and second stages (nodes 1 and 2 in Figure 3) experience a combination of gained signal, common-mode signal, and 650 mV . This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure XX through Figure XX show the allowablecommon-mode input voltage ranges for various output voltages and supply voltages.The following formulas can also be used to understand how the reference voltage (V REF ), common mode input voltage (V CM ), and differential input voltage (V DIFF ) interact. These twoformulas, along with the input range specifications in Table 1 and Table 3, set the boundaries where the part operates with best performance.V 9.02))((V 4.0−+<+<−−S CM DIFF S V V GAIN V VVV V V GAIN V S REFCM DIFF .6122))((−+<++The common-mode input range shifts upwards with temper-ature. At cold temperatures, the part requires an extra 200 mV of headroom from the positive supply, and operation near the negative supply has more margin. Conversely, hot temperatures require less headroom from the positive supply, but are the worst-case conditions for input voltages near the negative supply.LAYOUTTo ensure optimum performance of the AD8226 at the PCB level, care must be taken in the design of the board layout. The AD8226 pins are arranged in a logical manner to aid in this task.–IN R G R G S OUT S+IN (Not to Scale)07036-005Figure 5. Pinout DiagramCommon-Mode Rejection Ratio over FrequencyPoor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR across frequency high, input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the PCB traces.Parasitic capacitance at the gain setting pins can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), the part should be chosen so that the parasitic capacitance is as small as possible.Power SuppliesA stable dc voltage should be used to power the instrumenta-tion amplifier. Noise on the supply pins can adversely affect performance.A 0.1 µF capacitor should be placed as close as possible to each supply pin. As shown in Figure 6, a 10 µF tantalum capacitor can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits.+VFigure 6. Supply Decoupling, REF, and Output Referred to Local GroundReferencesThe output voltage of the AD8226 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground.INPUT BIAS CURRENT RETURN PATHThe input bias current of the AD8226 must have a return path to ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 7.THERMOCOUPLE–VSCAPACITIVELY COUPLED +V SREFCC–V S AD8226TRANSFORMER+V SREF–VSAD8226INCORRECTCAPACITIVELY COUPLEDf HIGH-PASSTHERMOCOUPLETRANSFORMER–V SCORRECT07036-007Figure 7. Creating an I BIAS PathRADIO FREQUENCY INTERFERENCE (RFI)RF rectification is often a problem when amplifiers are used in applications having strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instru-mentation amplifier, as shown in Figure 8. The filter limits the input signal bandwidth, according to the following relationship:FilterFrequency DIFF =)2(π21C D C C R +FilterFrequency CM = CRC π21where C D ≥ 10 C C .+V 07036-008Figure 8. RFI SuppressionC D affects the difference signal, and C C affects the common-mode signal. Values of R and C C should be chosen to minimize RFI. Mismatch between the R × C C at the positive input and the R × C C at the negative input degrades the CMRR of the AD8226. By using a value of C D one magnitude larger than C C , the effect of the mismatch is reduced, and performance is improved.OUTLINE DIMENSIONSCOMPLIANT TO JEDEC STANDARDS MO-187-AA0.800.600.40PLANE0.10Figure 9. 8-Lead Mini Small Outline Package [MSOP](RM-8)Dimensions shown in millimetersCONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.COMPLIANT TO JEDEC STANDARDS MS-012-AA012407-A0.17 (0.0067)0.25 (0.0098)0.10 (0.0040)COPLANARITY0.10Figure 10. 8-Lead Standard Small Outline Package [SOIC_N]Narrow Body(R-8)Dimensions shown in millimeters and (inches)1 Z = RoHS Compliant Part.NOTESNOTES元器件交易网AD8226 Preliminary Technical Data NOTES©2008 An alog Devices, In c. All rights reserved. Trademarks an dregistered trademarks are the property of their respective own ers.PR07036-0-10/08(PrA)。

–40°C < TA < +85°C –40°C < TA < +125°C
–40°C < TA < +85°C –40°C < TA < +125°C
0 V < VCM < 5 V –40°C < TA < +125°C RL = 10 kΩ, 0.5 V <VO < 4.5 V
AD8607/AD8609
These amplifiers use a patented trimming technique that achieves superior precision without laser trimming. The parts are fully specified to operate from 1.8 V to 5.0 V single supply or from ±0.9 V to ±2.5 V dual supply. The combination of low offsets, low noise, very low input bias currents, and low power consumption make the AD8603/AD8607/AD8609 especially useful in portable and loop-powered instrumentation.
元器件交易网
AD8603/AD8607/AD8609
TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Typical Performance Characteristics ............................................. 6 Applications..................................................................................... 12