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[ . î &026 )ODVK ((3520)HDWXUHV•Organization: 512Kx8/256Kx16•Sector architecture-One 16K; two 8K; one 32K; and seven 64K byte sectors -One 8K; two 4K; one 16K; and seven 32K word sectors -Boot code sector architecture—T (top) or B (bottom)-Erase any combination of sectors or full chip•Single 2.7-3.6V power supply for read/write operations •Sector protection•High speed 70/80/90/120 ns address access time •Automated on-chip programming algorithm-Automatically programs/verifies data at specified address •Automated on-chip erase algorithm-Automatically preprograms/erases chip or specifiedsectors•Hardware RESET pin-Resets internal state machine to read mode •Low power consumption-200 nA typical automatic sleep mode current-200 nA typical standby current-10 mA typical read current•JEDEC standard software, packages and pinouts -48-pin TSOP-44-pin SO; availability TBD•Detection of program/erase cycle completion-DQ7 DATA polling-DQ6 toggle bit-DQ2 toggle bit-RY/BY output•Erase suspend/resume-Supports reading data from or programming data to a sector not being erased•Low V CC write lock-out below 1.5V•10 year data retention at 150C•100,000 write/erase cycle endurance/RJLF EORFN GLDJUDP6HOHFWLRQ JXLGH29LV400-7029LV400-8029LV400-9029LV400-120Unit Maximum access time t AA708090120ns Maximum chip enable access time t CE708090120ns Maximum output enable access time t OE30303550ns48-pin TSOP44-pin SO (availability TBD)A8A9A10A11A12A13A14A15A16BYTE V SS DQ15/A-1DQ7DQ14NC NC WE NCNC RY/BY NC DQ2DQ10DQ3DQ11V CC DQ4DQ12DQ5DQ6DQ131234567891011121314484746454443424140393837363515163433A17A7A6A5A4A3A2A1A0V SS DQ0DQ8DQ1DQ917181920212232313029282723242625AS29LV400RESETCE OE 567891011121314151617181920A14A15A16V SSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4V CCA6A5A4A3A2A1A0CE V SS OE DQ0DQ8DQ1DQ9DQ2DQ102122DQ3DQ11A10A11A12A132NC 3A174A71BY /RY 40393837363534333231302928272625242343424144WE A8A9RESET A S 29L V 400BYTE3LQ DVVLJQPHQWV)XQFWLRQDO GHVFULSWLRQThe AS29LV400 is an 4 megabit, 3.0 volt Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For flexible Erase and Program capability, the 4 megabits of data is divided into eleven sectors: one 16K, two 8K, one 32K, and seven 64k byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16 data appears on DQ0–DQ15. The AS29LV400 is offered in JEDEC standard 48-pin TSOP and 44-pin SO. This device is designed to be programmed and erased with a single 3.0V V CC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29LV400 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word mode (×16 output) is selected by BYTE = high. Byte mode (×8 output) is selected by BYTE = low.The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. The device uses standard microprocessor write timings to send Write commands to the register. An internal state-machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the Programming and Erase operations. Data is read in the same manner as other Flash or EPROM devices. Use the Program command sequence to invoke the on-chip programming algorithm that automatically times the program pulse widths, and verifies proper cell margin. Use the Erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector when it is not already programmed before executing the erase operation. The Erase command also times the erase pulse widths and verifies the proper cell margins.Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both the Program and the Erase operations in all, or any combination of the eleven sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The Chip Erase command will automatically erase all unprotected sectors.When shipped from the factory, AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors.The device features a single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated voltages are provided for the Program and Erase operations. A low V CC detector automatically inhibits write operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect the end of the program or to erase operations. The device automatically resets to the Read mode after the Program or Erase operations are completed. DQ2 indicates which sectors are being erased.The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. The Control register architecture permits alteration of memory contents only when successful completion of specific command sequences has occured. During power up, the device is set to Read mode with all Program/Erase commands disabled if V CC is less than V LKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate Write commands, CE and WE must be a logical zero and OE a logical 1.When the device’s hardware RESET pin is driven low, any Program/Erase operation in progress is terminated and the internal state machine is reset to Read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated on-chip Program/Erase algorithm, the operating data in the address locations may become corrupted and require rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programmed one at a time using the EPROM programming mechanism of hot electron injection.2SHUDWLQJ PRGHVL = Low (<V IL ) = logic 0; H = High (>V IH ) = logic 1; V ID = 10.0 ± 1.0V; X = don’t care.In ×16 mode, BYTE = V IH . In ×8 mode, BYTE = V IL with DQ8-DQ14 in high Z and DQ15 = A-1.†Verification of sector protect/unprotect during A9 = V ID .ModeCEOEWEA0A1A6A9RESETDQ ID read MFR code L L H L L L V ID H Code ID read device code L L H H L L V ID H Code Read L L H A0A1A6A9H D OUT StandbyH X X X X X X H HighZ Output disable L H H X X X X H High Z WriteL H L A0A1A6A9H D IN Enable sector protect L V ID Pulse/L L H L V ID H X Sector unprotect L V ID Pulse/L L H H V ID H X Temporary sector unprotectX X X X X X X V ID X Verify sector protect †L L H L H L V ID H Code Verify sector unprotect †L L H L H H V ID H Code Hardware ResetXXXXXXXLHighZ0RGH GHILQLWLRQVItem DescriptionID MFR code, device code Selected by A9 = V ID(9.5V–10.5V), CE = OE = A1 = A6 = L, enabling outputs.When A0 is low (V IL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (V IH), D OUT represents the device code for the AS29LV400.Read mode Selected with CE = OE = L, WE = H. Data is valid in t ACC time after addresses are stable, t CE after CE is low and t OE after OE is low.Standby Selected with CE = H. Part is powered down, and I CC reduced to <1.0 µA when CE = V CC ± 0.3V = RESET. If activated during an automated on-chip algorithm, the device completes the operation before entering standby.Output disable Part remains powered up; but outputs disabled with OE pulled high.Write Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.Enable sector protect disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector protect algorithm on page12.Sector unprotect protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect algorithm on page12.Verify sector protect/ unprotect Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A12–17 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.Temporary sector unprotect Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to RESET to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal of +10V from RESET.RESET Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data may be corrupted.power downHold RESET low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is 50ns.Automatic sleep mode Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new data is returned within standard access times.)OH[LEOH VHFWRU DUFKLWHFWXUHIn word mode, there are one 8K word, two 4K word, one 16K word, and seven 32K word sectors. Address range is A17–A-1 if BYTE = V IL ; address range isA17–A0 if BYTE = V IH .,' 6HFWRU DGGUHVV WDEOH5($' FRGHVKey: L =Low (<V IL ); H = High (>V IH ); X =Don’t careSector Bottom boot sector architecture (AS29LV400B)Top boot sector architecture (AS29LV400T)×8×16Size (Kbytes)×8×16Size (Kbytes)00000h–03FFFh 00000h–01FFFh 1600000h–0FFFFh 00000h–07FFFh 6404000h–05FFFh 02000h–02FFFh 810000h–1FFFFh 08000h–0FFFFh 64206000h–07FFFh 03000h–03FFFh 820000h–2FFFFh 10000h–17FFFh 64308000h–0FFFFh 04000h–07FFFh 3230000h–3FFFFh 18000h–1FFFFh 6410000h–1FFFFh 08000h–0FFFFh 6440000h–4FFFFh 20000h–27FFFh 6420000h–2FFFFh 10000h–17FFFh 6450000h–5FFFFh 28000h–2FFFFh 64630000h–3FFFFh 18000h–1FFFFh 6460000h–6FFFFh 30000h–37FFFh 64740000h–4FFFFh 20000h–27FFFh 6470000h–77FFFh 38000h–3BFFFh 3250000h–5FFFFh 28000h–2FFFFh 6478000h–79FFFh 3C000h–3CFFFh 860000h–6FFFFh 30000h–37FFFh 647A000h–7BFFFh 3D000h–3DFFFh 81070000h–7FFFFh 38000h–3FFFFh 647C000h–7FFFFh 3E000h–3FFFFh 16Sector Bottom boot sector address(AS29LV400B)Top boot sector address(AS29LV400T)A17A16A15A14A13A12A17A16A15A14A13A12000000X 000X X X 1000010001X X X 2000011010X X X 30001X X 011X X X 4001X X X 100X X X 5010X X X 101X X X 6011X X X 110X X X 7100X X X 1110X X 8101X X X 1111009110X X X 11110110111X X X11111XModeA17–A12A6A1A0CodeMFR code (Alliance Semiconductor)X L L L 52h Device code×8 T bootX L L H B9h ×8 B boot X L L H BAh ×16 T boot X L L H 22B9h ×16 B bootX L L H 22BAhSector protectionSector addressLHL01h protected 00h unprotected&RPPDQG IRUPDW1Bus operations defined in "Mode definitions," on page 3.2Reading from and programming to non-erasing sectors allowed in Erase Suspend mode.3Address bits A11-A17 = X = Don’t Care for all address commands except where Program Address and Sector Address are required.4Data bits DQ15-DQ8 are don’t care for unlock and command cycles.5The Unlock Bypass command must be initiated before the Unlock Bypass Program command.6The Unlock Bypass Reset command returns the device to reading array data when it is in the unlock bypass mode.Command sequenceRequired bus writecycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycleAddress Data Address DataAddress DataAddressDataAddress Data Address DataReset/Read 1XXXh F0h Read Address Read Data Reset/Read×163555h AAh2AAh 55h555h F0h Read Address Read Data ×8AAAh 555h AAAh AutoselectID Read×163555hAAh2AAh55h 555h90h01h Device code 22B9h (T) 22BAh (B)×8AAAh 555h AAAh 02h Device code B9h(T) BAh(B)×16555hAAh2AAh 55h555h 90h00h MFR code 0052h ×8AAAh 555h AAAh 52h×16555hAAh 2AAh55h555h90hXXX02h Sector protection 0001h = protected 0000h = unprotected ×8AAAh 555h AAAh XXX04h Sector protection 0001h=protected 0000h=unprotected Program ×164555h AAh 2AAh 55h 555h A0h Program AddressProgram Data×8AAAh 555h AAAh Unlock bypass ×163555AAh 2AA 55h 55520h×8AAA 555AAAUnlock bypass program 2XXX A0h Program address Program data Unlock bypass reset 2XXX 90h XXX 00h Chip Erase ×166555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h ×8AAAh 555h AAAh AAAh 555h AAAh Sector Erase×166555h AAh 2AAh 55h555h 80h555h AAh2AAh 55hSector Address30h×8AAAh 555hAAAhAAAh555hSector Erase Suspend 1XXXh B0h Sector Erase Resume1XXXh30h&RPPDQG GHILQLWLRQVItem DescriptionReset/Read Initiate read or reset operations by writing the Read/Reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered.Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up.ID Read AS29LV400 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +10V on A9. AS29LV400 also contains an ID Read command to read the device code with only +3V, since multiplexing +10V on address lines is generally undesirable.Initiate device ID read by writing the ID Read command sequence into the command register. Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command sequence with a read sequence from address XXX01h to return device code.To verify write protect status on sectors, read address XXX02h. Sector addresses A17–A12 produce a 1 on DQ0 for protected sector and a 0 for unprotected sector.Exit from ID read mode with Read/Reset command sequence.Hardware Reset Holding RESET low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven low. RY/BY remains low until internal state machine resets. After RESET is set high, there is a delay of 50 ns for the device to permit read operations.Byte/word Programming Programming the AS29LV400 is a four bus cycle operation performed on a byte-by-byte or word-by-word basis. Two unlock write cycles precede the Program Setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or WE, whichever is first. The AS29LV400’s automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin.Check programming status by sampling data on the RY/BY pin, or either the DATA polling (DQ7) or toggle bit (DQ6) at the program address location. The programming operation is complete if DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/BY pin = high.The AS29LV400 ignores commands written during programming. A hardware reset occurring during programming may corrupt the data at the programmed location.AS29LV400 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a Reset command returns the device to read mode.Unlock Bypass Command Sequence The unlock bypass feature increases the speed at which the system programs bytes or words to the device because it bypasses the first two unlock cycles of the standard program command sequence. To initiate the unlock bypass command sequence, two unlock cycles must be written, then followed by a third cycle which has the unlock bypass command, 20h.The device then begins the unlock bypass mode. In order to program in this mode, a two cycle unlock bypass program sequence is required. The first cycle has the unlock bypass program command, A0h. It is followed by a second cycle which has the program address and data. To program additional data, the same sequence must be followed.The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.Chip Erase Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip Erase command.Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip Erase command sequence, AS29LV400 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV400 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit.Sector Erase Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by addressing any location in the sector. The address is latched on the falling edge of WE; the command, 30h is latched on the rising edge of WE. The sector erase operation begins after a sector erase time-out.To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be less than the erase time-out period, or the AS29LV400 ignores the command and erasure begins. During the time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV400 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on the ignored sectors.The entire array need not be written with 0s prior to erasure. AS29LV400 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29LV400 requires no CPU control or timing signals during sector erase operations.Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address must be performed on addresses that fall within the sectors being erased. AS29LV400 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit.Item DescriptionErase Suspend Erase Suspend allows interruption of sector erase operations to read data from or program data to a sector not being erased. Erase suspend applies only during sector erase operations, including the time-out period. Writing an Erase Suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation.AS29LV400 ignores any commands during erase suspend other than Read/Reset, Program or Erase Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are Don’t Care when writing Erase Suspend or Erase Resume commands.AS29LV400 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command. To determine completion of erase suspend, either check DQ6 after selecting an address of a sector not being erased, or poll RY/BY. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29LV400 ignores redundant writes of Erase Suspend.While in erase-suspend mode, AS29LV400 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase; these operations are treated as standard read or standard programming mode. AS29LV400 defaults to erase-suspend-read mode while an erase operation has been suspended.Write the Resume command 30h to continue operation of sector erase. AS29LV400 ignores redundant writes of the Resume command. AS29LV400 permits multiple suspend/resume operations during sector erase.Sector Protect When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <1 µs. When attempting to erase a protected sector, DATA polling andToggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode without altering the specified sectors.Ready/Busy RY/BY indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or completed (RY/BY = high). The device does not accept Program/Erase commands whenRY/BY = low. RY/BY= high when device is in erase suspend mode. RY/BY = high when device exceeds time limit, indicating that a program or erase operation has failed. RY/BY is an open drain output, enabling multiple RY/BY pins to be tied in parallel with a pull up resistor to V CC.Item Description6HFWRU SURWHFW DOJRULWKP 6HFWRU XQSURWHFW DOJRULWKPSTART PLSCNT = 1RESET# = V ID Wait 1 µsFirst Write Cycle=60h?Temporary sector unprotect modeNoSet up sector Sector protect:addresswrite 60h to sector address with A6=0, A1=1,A0=0Wait 150 µs Verify sector protect; write 40h to sector address with A6=0,A1=1, A0=0Read from sector address with A6=0,A1=1, A0=0Data=01h?Protect sector?PLSCNT=25?NoIncrement PLSCNTNoDevice failedYesYes YesNoSTART PLSCNT = 1RESET# = V ID Wait 1 µsFirst Write Cycle=60h?Temporary sector unprotect modeNoYesAll sectors protected?Set up first Sector unprotect:sector address write 60h to sector address with A6=1, A1=1,A0=0Wait 15 ms Verify sector unprotect; write 40h to sector address with A6=1,A1=1, A0=0Read from sector address with A6=1,A1=1, A0=0Data=00h?Last sector verified?NoYesYesRemove V ID from RESET#Write reset command Sector unprotectcompleteRemove V ID from RESET#Write reset command Sector protect completePLSCNT Increment PLSCNTNoDevice failedYes=1000?Set up next sector addressNoProtect all sectors:The shaded portion of the sector protct initiated for all unprotected sectors before calling the sector unprotectNoYesYesalgorithm must be another6WDWXV RSHUDWLRQV:ULWH RSHUDWLRQ VWDWXVDQ2 toggles when an erase-suspended sector is read repeatedly . DQ6 toggles when any address is read repeatedly .DQ2 = 1 if byte address being programmed is read during erase-suspend program mode.†DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase.DATA polling (DQ7)Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflectscomplement of data last written when read during the automated on-chip program algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip program algorithm (1 after completion of erase agorithm).Toggle bit 1 (DQ6)Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE or OE toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 µs during program mode writes, and <5 µs during erase (if all selected sectors are protected).Exceeding time limit (DQ5)Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming or sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors). Attempting to program 0 to 1 will set DQ5 = 1.Sector erase timer (DQ3)Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and after each Sector Erase command to verify that the command was accepted.Toggle bit 2 (DQ2)During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode.StatusDQ7DQ6DQ5DQ3DQ2RY/BY Standard modeAuto programmingDQ7Toggle 0N/A No toggle 0Program/erase in auto erase 0Toggle 01Toggle †0Erase suspend modeRead erasing sector 1No toggle 0N/A Toggle 1Read non-erasing sector Data Data Data Data Data 1Program in erase suspend DQ7Toggle 0N/A Toggle †0Exceeded time limitsAuto programming (byte)DQ7Toggle 1N/A No toggle 1Program/erase in auto erase 0Toggle 1N/A Toggle †1Program in erase suspend (non-erase suspended sector)DQ7Toggle1N/ANo toggle1$XWRPDWHG RQ FKLS SURJUDPPLQJ DOJRULWKP$XWRPDWHG RQ FKLS HUDVH DOJRULWKP†The system software should check the status of DQ3 prior to and following eachsubsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check.START555h/AAh2AAh/55h555h/A0hProgram address/program dataProgram command sequence ×16 mode (address/data):Write program command sequence(see below)DATA polling or toggle bit successfully completedLast address?Programming completedYESIncrement addressNO555h/AAh2AAh/55h555h/80herase command sequence 555h/AAh2AAh/55hSector address/30hErase complet e×16 mode (address/data):DATA polling or toggle bit successfully completedWrite erase command sequence(see below)555h/AAh2AAh/55h 555h/80h Chip erase command sequence 555h/AAh 2AAh/55h 555h/10h×16 mode (address/data):Individual sector/multiple sectorSector address/30hSector address/30hoptional sector erase commandsSTART。

*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
s PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
(BGA-48P-M11)
(WLP-48P-M02)
2
元器件交易网
MBM29LV400TC-55/70/90/MBM29LV400BC-55/70/90
s GENERAL DESCRIPTION
The MBM29LV400TC/BC are a 4M-bit, 3.0 V-only Flash memory organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The MBM29LV400TC/BC are offered in a 48-pin TSOP(1), 44-pin SOP , 48-pin CSOP , and 48-ball FBGA packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. The standard MBM29LV400TC/BC offer access times 70 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29LV400TC/BC are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29LV400TC/BC are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV400TC/BC are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV400TC/BC memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.

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高性能
- 存取时间快55纳秒
低功耗（在5个典型值 MHz) - 6 mA典型有效读电流 - 24 mA典型编程/擦除电流
- 1 µA 典型待机电流（标准访问
时间到主动模式）
灵活部门架构：
- 一个16字节,两个8字节,一个32字节, 十五64K字节扇区（字节模式）
RY/BY#
DQ0 – DQ15 (A-1)
芯片中文手册,看全文,戳
EN29LV800B
扇形
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
表 2A.顶 部 引 导 块 扇 区 架 构
地址范围
(X16)
(X8)
行业
SIZE （千字节/ A18 A17 A16 A15 A14 A13 A12
K字）
7E000h-7FFFFh FC000h-FFFFFh
16/8
111111X
7D000h-7DFFFh FA000h-FBFFFh
8/4
1111101
7C000h-7CFFFh F8000h-F9FFFh
8/4
1111100
78000h-7BFFFh F0000h – F7FFFh
32/16
11 1 1 0XX
44
DQ7
43
DQ14
42
DQ6
41
DQ13
40
DQ5
39
DQ12
38
DQ4
37
Vcc
36
DQ11
35

FEATURES• Single power supply operation- Full voltage range: 2.7 to 3.6 volts for read, erase and program operations• Low power cons umption (typical values at 5 MHz)- 9 mA typical active read current- 20 mA typical program/erase current- Less than 1 μA current in standby or automatic sleep mode.• JEDEC standards compatible- Pinout and software compatible with single-power supply Flash standard• Manufactured on 0.18μm process technology• Flexible Sector Architecture:- One hundred and twenty-eight 32K-Word /64K-byte sectors.• Minimum 100K program/erase endurance cycles.• High performance for program and erase - Word program time: 8µs typical - Sector Erase time: 500ms typical - Chip Erase time: 64s typical • Package Options - 48-pin TSOP - 48-ball FBGASoftware features: • Sector Group Protection- Provide locking of sectors to prevent program or erase operations within individual sectors - Additionally, temporary Sector GroupUnprotect allows code changes in previously protected sectors. • Standard DATA# polling and toggle bits feature• Unlock Bypass Program command supported • Sector Erase Suspend / Resume modes: Read and program another Sector during Sector Erase Suspend Mode• Support JEDEC Common Flash Interface (CFI).Hardware features:• Pin compatible to lower density, easy replacement for code expansion. • RESET# hardware reset pin- Hardware method to reset the device to read mode. • WP#/ACC input pin- Write Protect (WP#) function allowsprotection of first or last 32K-word sector, regardless of previous sector protect status - Acceleration (ACC) function provides accelerated program timesGENERAL DESCRIPTIONThe EN29LV640H/L / EN29LV640U is a 64-Megabit ( 4Mx16 ), electrically erasable, read/write non-volatile flash memory. Any word can be programmed typically in 8µs. This device is entirely command set compatible with the JEDEC single-power-supply Flash standard.The EN29LV640H/L / EN29LV640U is designed to allow either single Sector or full Chip erase operation, where each Sector Group can be protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.EN29LV640 64 Megabit (4M x 16-bit ) CMOS 3.0 Volt-only, Uniform Sector Flash MemoryPRODUCT SELECTOR GUIDEProduct Number EN29LV640H/LEN29LV640USpeed OptionFull Voltage Range: V CC =2.7 – 3.6 V90 90 Max Access Time (ns) 90 90 Max CE# Access Time (ns) 90 90 Max OE# Access Time (ns) 3535BLOCK DIAGRAMWE# CE# OE#State ControlCommand RegisterErase Voltage GeneratorInput/Output BuffersProgram Voltage GeneratorChip Enable Output EnableLogicData LatchY-Decoder X-Decoder Y-GatingCell MatrixTimerV CC DetectorA21-A0V CC V SS DQ15-DQ0Address LatchSector Protect SwitchesSTBSTBWP#/ ACC RY/BY#RESET#CONNECTION DIAGRAMSTABLE 1. PIN DESCRIPTIONLOGIC DIAGRAMDQ15 – DQ0A21 – A0WE#CE#RY/BY#OE#RESET#WP# / ACCPin Name Function A21-A0 22 Address inputs DQ15-DQ0 16 Data Inputs/Outputs CE# Chip Enable Input OE# Output Enable Input WE#Write Enable InputWP#/ACC Write Protect / Acceleration Pin RY/BY# Ready/Busy status output RESET# Hardware Reset Input Pin V cc Supply Voltage (2.7-3.6V) V ss GroundNCNot Connected to anythingORDERING INFORMATIONEN29LV640 H ─90 T C PPACKAGING CONTENT(Blank) = ConventionalP = Pb FreeTEMPERATURE RANGEI = Industrial (-40°C to +85°C)C = Commercial (0°C to +70°C)PACKAGET = 48-pin TSOPB = 48-Ball Fine Pitch Ball Grid Array (FBGA)0.80mm pitchSPEED OPTIONSee Product Selector Guide and Valid CombinationsSECTOR for WRITE PROTECT (WP#/ACC=0)H=highestaddresssectorprotectedL=lowestaddresssectorprotectedBASE PART NUMBEREN29LV640 / EN29LV640U64 Megabit(4M x 16-Bit) Uniform Sector Flash3V Read, Erase and ProgramPRODUCT SELECTOR GUIDEValid Combinations VccEN29LV640H–90 EN29LV640L–90 TI, TCBI,BCV cc = 2.7V-3.6VTable 2. Sector (Group) Address Tables Sector GroupProtect/UnprotectSector Address Range for Sector EraseSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA0 0 0 0 0 0 0 0 000000–007FFFSA1 0 0 0 0 0 0 1 008000–00FFFFSA2 0 0 0 0 0 1 0 010000–017FFFSG0 00000SA3 0 0 0 0 0 1 1 018000–01FFFFSA4 0 0 0 0 1 0 0 020000–027FFFSA5 0 0 0 0 1 0 1 028000–02FFFFSA6 0 0 0 0 1 1 0 030000–037FFF SG100001SA7 0 0 0 0 1 1 1 038000–03FFFFSA8 0 0 0 1 0 0 0 040000–047FFFSA9 0 0 0 1 0 0 1 048000–04FFFFSA10 0 0 0 1 0 1 0 050000–057FFF SG200010SA11 0 0 0 1 0 1 1 058000–05FFFFSA12 0 0 0 1 1 0 0 060000–067FFFSA13 0 0 0 1 1 0 1 068000–06FFFFSA14 0 0 0 1 1 1 0 070000–077FFF SG300011SA15 0 0 0 1 1 1 1 078000–07FFFFSA16 0 0 1 0 0 0 0 080000–087FFFSA17 0 0 1 0 0 0 1 088000–08FFFFSA18 0 0 1 0 0 1 0 090000–097FFF SG4 00100SA19 0 0 1 0 0 1 1 098000–09FFFFSA20 0 0 1 0 1 0 0 0A0000–0A7FFFSA21 0 0 1 0 1 0 1 0A8000–0AFFFFSA22 0 0 1 0 1 1 0 0B0000–0B7FFF SG5 00101SA23 0 0 1 0 1 1 1 0B8000–0BFFFFSA24 0 0 1 1 0 0 0 0C0000–0C7FFFSA25 0 0 1 1 0 0 1 0C8000–0CFFFFSA26 0 0 1 1 0 1 0 0D0000–0D7FFF SG6 00110SA27 0 0 1 1 0 1 1 0D8000–0DFFFFSA28 0 0 1 1 1 0 0 0E0000–0E7FFFSA29 0 0 1 1 1 0 1 0E8000–0EFFFFSA30 0 0 1 1 1 1 0 0F0000–0F7FFF SG700111SA31 0 0 1 1 1 1 1 0F8000–0FFFFFSector Group A21-A17 Sector A21 A20A19A18A17A16A15Address Range(hexadecimal) SA32 0 1 0 0 0 0 0 100000–107FFFSA33 0 1 0 0 0 0 1 108000–10FFFFSA34 0 1 0 0 0 1 0 110000–117FFFSG8 01000SA35 0 1 0 0 0 1 1 118000–11FFFFSA36 0 1 0 0 1 0 0 120000–127FFFSA37 0 1 0 0 1 0 1 128000–12FFFFSA38 0 1 0 0 1 1 0 130000–137FFF SG9 01001SA39 0 1 0 0 1 1 1 138000–13FFFFSA40 0 1 0 1 0 0 0 140000–147FFFSA41 0 1 0 1 0 0 1 148000–14FFFFSA42 0 1 0 1 0 1 0 150000–157FFF SG10 01010SA43 0 1 0 1 0 1 1 158000–15FFFFSA44 0 1 0 1 1 0 0 160000–167FFFSA45 0 1 0 1 1 0 1 168000–16FFFFSA46 0 1 0 1 1 1 0 170000–177FFF SG11 01011SA47 0 1 0 1 1 1 1 178000–17FFFFSA48 0 1 1 0 0 0 0 180000–187FFFSA49 0 1 1 0 0 0 1 188000–18FFFFSA50 0 1 1 0 0 1 0 190000–197FFF SG12 01100SA51 0 1 1 0 0 1 1 198000–19FFFFSA52 0 1 1 0 1 0 0 1A0000–1A7FFFSA53 0 1 1 0 1 0 1 1A8000–1AFFFFSA54 0 1 1 0 1 1 0 1B0000–1B7FFF SG13 01101SA55 0 1 1 0 1 1 1 1B8000–1BFFFFSA56 0 1 1 1 0 0 0 1C0000–1C7FFFSA57 0 1 1 1 0 0 1 1C8000–1CFFFFSA58 0 1 1 1 0 1 0 1D0000–1D7FFF SG14 01110SA59 0 1 1 1 0 1 1 1D8000–1DFFFFSA60 0 1 1 1 1 0 0 1E0000–1E7FFFSA61 0 1 1 1 1 0 1 1E8000–1EFFFFSA62 0 1 1 1 1 1 0 1F0000–1F7FFF SG15 01111SA63 0 1 1 1 1 1 1 1F8000–1FFFFFSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA64 1 0 0 0 0 0 0 200000–207FFFSA65 1 0 0 0 0 0 1 208000–20FFFFSA66 1 0 0 0 0 1 0 210000–217FFFSG16 10000SA67 1 0 0 0 0 1 1 218000–21FFFFSA68 1 0 0 0 1 0 0 220000–227FFFSA69 1 0 0 0 1 0 1 228000–22FFFFSA70 1 0 0 0 1 1 0 230000–237FFF SG1710001SA71 1 0 0 0 1 1 1 238000–23FFFFSA72 1 0 0 1 0 0 0 240000–247FFFSA73 1 0 0 1 0 0 1 248000–24FFFFSA74 1 0 0 1 0 1 0 250000–257FFF SG1810010SA75 1 0 0 1 0 1 1 258000–25FFFFSA76 1 0 0 1 1 0 0 260000–267FFFSA77 1 0 0 1 1 0 1 268000–26FFFFSA78 1 0 0 1 1 1 0 270000–277FFF SG1910011SA79 1 0 0 1 1 1 1 278000–27FFFFSA80 1 0 1 0 0 0 0 280000–287FFFSA81 1 0 1 0 0 0 1 288000–28FFFFSA82 1 0 1 0 0 1 0 290000–297FFF SG2010100SA83 1 0 1 0 0 1 1 298000–29FFFFSA84 1 0 1 0 1 0 0 2A0000–2A7FFFSA85 1 0 1 0 1 0 1 2A8000–2AFFFFSA86 1 0 1 0 1 1 0 2B0000–2B7FFF SG2110101SA87 1 0 1 0 1 1 1 2B8000–2BFFFFSA88 1 0 1 1 0 0 0 2C0000–2C7FFFSA89 1 0 1 1 0 0 1 2C8000–2CFFFFSA90 1 0 1 1 0 1 0 2D0000–2D7FFF SG2210110SA91 1 0 1 1 0 1 1 2D8000–2DFFFFSA92 1 0 1 1 1 0 0 2E0000–2E7FFFSA93 1 0 1 1 1 0 1 2E8000–2EFFFFSA94 1 0 1 1 1 1 0 2F0000–2F7FFF SG2310111SA95 1 0 1 1 1 1 1 2F8000–2FFFFFSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA96 1 1 0 0 0 0 0 300000–307FFFSA97 1 1 0 0 0 0 1 308000–30FFFFSA98 1 1 0 0 0 1 0 310000–317FFFSG24 11000SA99 1 1 0 0 0 1 1 318000–31FFFFSA100 1 1 0 0 1 0 0 320000–327FFFSA101 1 1 0 0 1 0 1 328000–32FFFFSA102 1 1 0 0 1 1 0 330000–337FFF SG25 11001SA103 1 1 0 0 1 1 1 338000–33FFFFSA104 1 1 0 1 0 0 0 340000–347FFFSA105 1 1 0 1 0 0 1 348000–34FFFFSA106 1 1 0 1 0 1 0 350000–357FFF SG26 11010SA107 1 1 0 1 0 1 1 358000–35FFFFSA108 1 1 0 1 1 0 0 360000–367FFFSA109 1 1 0 1 1 0 1 368000–36FFFFSA110 1 1 0 1 1 1 0 370000–377FFF SG27 11011SA111 1 1 0 1 1 1 1 378000–37FFFFSA112 1 1 1 0 0 0 0 380000–387FFFSA113 1 1 1 0 0 0 1 388000–38FFFFSA114 1 1 1 0 0 1 0 390000–397FFF SG28 11100SA115 1 1 1 0 0 1 1 398000–39FFFFSA116 1 1 1 0 1 0 0 3A0000–3A7FFFSA117 1 1 1 0 1 0 1 3A8000–3AFFFFSA118 1 1 1 0 1 1 0 3B0000–3B7FFF SG29 11101SA119 1 1 1 0 1 1 1 3B8000–3BFFFFSA120 1 1 1 1 0 0 0 3C0000–3C7FFFSA121 1 1 1 1 0 0 1 3C8000–3CFFFFSA122 1 1 1 1 0 1 0 3D0000–3D7FFF SG30 11110SA123 1 1 1 1 0 1 1 3D8000–3DFFFFSA124 1 1 1 1 1 0 0 3E0000–3E7FFFSA125 1 1 1 1 1 0 1 3E8000–3EFFFFSA126 1 1 1 1 1 1 0 3F0000–3F7FFF SG31 11111SA127 1 1 1 1 1 1 1 3F8000–3FFFFF Note: The sizes of all sectors are 32K-word.USER MODE DEFINITIONSTABLE 3. BUS OPERATIONSOperation CE#OE#WE#RESET#WP#/ACC A21-A0DQ15-DQ0 Read LLHHL/HA IN D OUTWrite LHLH(Note1)A IN(Note 3)AcceleratedProgramL H L H V HH A IN(Note 3)CMOS Standby V cc±0.3V X X V cc±0.3VH XHigh-ZTTL Standby H X X H L / H X High-Z Output Disable L H H H L / H X High-Z Hardware Reset X X X L L / H X High-ZSector Group Protect (Note 2) L H L V ID HSA,A6=L,A1=H,A0=L(Note 3)Sector GroupUnprotect (Note 2) L H L V ID HSA,A6=H,A1=H,A0=L(Note 3)TemporarySector GroupUnprotectX X X V ID H A IN(Note 3)L=logic low= V IL, H=Logic High= V IH, V ID= V HH = 11 ± 0.5V = 10.5 ─ 11.5V, X=Don’t Care (eitherL or H, but not floating!), SA=Sector Addresses (A21-A15), D IN=Data In, D OUT=Data Out,A IN=Address InNotes:1. If the system asserts V IL on the WP# / ACC pin, the device disables program and erasefunctions in the first or last sector independent of whether those sectors were protected orunprotected; if the system asserts V IH on the WP# /ACC pin, the device reverts to whether thefirst or last sector was previously protected or unprotected. If WP# / ACC = V HH, all sectors willbe unprotected.2. Please refer to “Sector Group Protection & Unprotection”, Flowchart 6a and Flowchart 6b.3. D IN or D OUT as required by command sequence, data polling, or sector protect algorithm.Read ModeThe device is automatically set to reading array data after device power-up or hardware reset. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithmAfter the device accepts an Sector Erase Suspend command, the device enters the Sector Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing aprogramming operation in the Sector Erase Suspend mode, the system may once again read array data with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional information.The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high or while in the autoselect mode. See the “Reset Command” for additional details.Output Disable ModeWhen the OE# pin is at a logic high level (V IH), the output from the device is disabled. The output pins are placed in a high impedance state.Standby ModeThe device has a CMOS-compatible standby mode, which reduces the c urrent to < 1µA (typical). It is placed in CMOS-compatible standby when the CE# pin is at V CC± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum V CC c urrent to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input.Automatic Sleep ModeThe device has an automatic sleep mode, which minimizes power consumption. The devices will enter this mode automatically when the states of address bus remain stable for t acc + 30ns. ICC4 in the DC Characteristics table shows the current specification. With standard access times, the device will output new data when addresses change.Writing Command SequencesTo write a command or command sequence to program data to the device or erase data, the system has to drive WE# and CE# to V IL, and OE# to V IH.The device has an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four.The system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. Please refer to the “Command Definitions” for all the available commands.Autoselect Identification ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID(10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector group protection, the sector group address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The “Command Definitions” table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See“Command Definitions” for details on using the autoselect mode. Note that a Reset command is required to return to read mode when the device is in the autoselect mode.TABLE 4. Autoselect Codes (Using High Voltage, V ID )L=logic low= V IL , H=Logic High= V IH , V ID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector AddressesNote:1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh.2. A9 = V ID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command AutoselectMode.RESET#: Hardware ResetWhen RESET# is driven low for t RP , all output pins are tristates. All commands written in the internal state machine are reset to reading array data.Please refer to timing diagram for RESET# pin in “AC Characteristics”.Sector Group Protection & UnprotectionThe hardware sector group protection feature disables both program and erase operations in any sector group. The hardware chip unprotection feature re-enables both program and erase operations in previously protected sector group. A sector group consists of four adjacent sectors that would be protected at the same time. Please see Table 2 which show the organization of sector groups.There are two methods to enable this hardware protection circuitry. The first one requires only that the RESET# pin be at V ID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 6a and 6b for the algorithm and Figure 11 for the timings.When doing Sector Group Unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle.The second method is for programming equipment. This method requires V ID to be applied to both OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a separate document, the Datasheet Supplement of EN29LV640H/L ; EN29LV640U, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.Description CE# OE# WE# A21toA15 A14 to A10A92A8A7A6A5 to A2A1 A0 DQ15 to DQ0H1XX1Ch Manufacturer ID: Eon L L H X X V IDLX L XL LXX7FhAutoselect Device ID L L H X X V IDX X L X L H 227Eh Sector Protection VerificationL L H SA X V IDX X L X H LXX01h(Protected)XX00h(Unprotected)Write Protect / Accelerated Program (WP# / ACC)The Write Protect function provides a hardware method to protect the first or last sector against erase and program without using V ID.When WP# is Low, the device protects the first or last sector regardless of whether these sectors were previously protected or unprotected using the method described in “Sector Group Protection & Unprotection”, Program and Erase operations in these sectors are ignored.When WP# is High, the device reverts to the previous protection status of the first or last sector. Program and Erase operations can now modify the data in those sectors unless the sector is protected using Sector Group Protection.Note that the WP# pin must not be left floating or unconnected.When WP#/ACC is raised to V HH the memory automatically enters the Unlock Bypass mode(please refer to “Command Definitions”), temporarily unprotects every protected sectors, and reduces the time required for program operation. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. When WP#/ACC returns to V IH or V IL, normal operation resumes. The transitions from V IH or V IL to V HH and from V HH to V IH or V IL must be slower than t V HH, see Figure 5. Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin mustnot be at V HH for operations other than accelerated programming. It could cause the device to be damaged.Never raise this pin to V HH from any mode except Read mode, otherwise the memory may be left in an indeterminate state.A 0.1µF capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program.Temporary Sector Group UnprotectThis feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Temporary Sector Group Unprotect mode is activated by setting the RESET# pin to V I D. During this mode, formerly protected sector groups can be programmed or erased by simply selecting the sector group addresses. Once V I D is removed from the RESET# pin, all the previously protected sector groups are protected again. See accompanying flowchart and timing diagrams in Figure 10 for more details.StartReset#=V ID(note 1) Perform Erase or ProgramOperationsRESET#=V IH Temporary Sector Group Unprotect Completed (note 2)Notes:1. All protected sector groups are unprotected. (If WP#/ACC=V IL, the first or last sector will remain protected.)2. Previously protected sector groups are protected again.COMMON FLASH INTERFACE (CFI)The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data.The system can read CFI information at the addresses given in Tables 5-8.The upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode.Table 5. CFI Query Identification StringAddresses Data Description10h 11h 12h 0051h0052h0059hQuery Unique ASCII string “QRY”13h 14h 0002h0000hPrimary OEM Command Set15h 16h 0040h0000hAddress for Primary Extended Table17h 18h 0000h0000hAlternate OEM Command set (00h = none exists)19h 1Ah 0000h0000hAddress for Alternate OEM Extended Table (00h = none exists)Table 6. System Interface StringAddresses Data Description1Bh 0027h Vcc Min (write/erase)DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt1Ch 0036h Vcc Max (write/erase)DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt1Dh 0000h Vpp Min. voltage (00h = no Vpp pin present)1Eh 0000h Vpp Max. voltage (00h = no Vpp pin present)1Fh 0003h Typical timeout per single byte/word write 2NμS20h 0000h Typical timeout for Min, size buffer write 2NμS (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)23h 0005h Max. timeout for byte/word write 2N times typical24h 0000h Max. timeout for buffer write 2N times typical25h 0002h Max. timeout per individual block erase 2N times typical26h 0000h Max timeout for full chip erase 2N times typical (00h = not supported)Table 7. Device Geometry DefinitionAddresses Data Description27h 0017h Device Size = 2Nbytes 28h 29h 0001h0000h Flash Device Interface description (refer to CFI publication 100)2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0001h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 007Fh 0000h 0000h 0001h Erase Block Region 1 Information (refer to the CFI specification of CFI publication 100) 31h 32h 33h 34h 0000h 0000h0000h 0000h Erase Block Region 2 Information35h 36h 37h 38h 0000h 0000h0000h 0000h Erase Block Region 3 Information39h 3Ah 3Bh 3Ch 0000h 0000h0000h 0000hErase Block Region 4 InformationTable 8. Primary Vendor-specific Extended QueryAddresses Data Description40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII45h 0004hAddress Sensitive Unlock0 = Required, 1 = Not Required 46h 0002hErase Suspend0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0004hSector Protect0 = Not Supported, X = Number of sectors in per group 48h 0001hSector Temporary Unprotect00 = Not Supported, 01 = Supported 49h 0004h Sector Protect/Unprotect scheme01 = 29F040 mode, 02 = 29F016 mode,03 = 29F400 mode, 04 = 29LV800A mode 4Ah 0000hSimultaneous Operation00 = Not Supported, 01 = Supported 4Bh 0000hBurst Mode Type00 = Not Supported, 01 = Supported 4Ch 0000hPage Mode Type00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 00A5hMinimum WP#/ACC (Acceleration) Supply Voltage00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV 4Eh 00B5hMaximum WP#/ACC (Acceleration) Supply Voltage00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV4Fh 00XXh 00h = Uniform Sector DevicesHardware Data protectionThe command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.Low V CC Write InhibitWhen V CC is less than V LKO, the device does not accept any write cycles. This protects data during V CC power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than V LKO.Write Pulse “Glitch” protectionNoise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE# = V IL, CE# = V IH, or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.Power-up Write InhibitDuring power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = V IL, WE#= V IL and OE# = V IH, the device will not accept commands on the rising edge of WE#.COMMAND DEFINITIONSThe operations of the device are selected by one or more commands written into the commandregister. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.Table 9. EN29LV640H/L / EN29LV640U Command DefinitionsBus Cycles (Note 1-2)1stCycle 2ndCycle3rdCycle4thCycle5thCycle6thCycleCommand Sequence C y c l e sAddr DataAddr DataAddr DataAddr DataAddr DataAddr DataRead (Note 3)1RA RD Reset 1xxx F0 Manufacturer ID 4555 AA 2AA 55 55590000 1007F 1CDevice ID 4555 AA 2AA 55 55590 X01 227E A u t o s e l e c tSector Protect Verify (Note 4)4555 AA 2AA 55 55590(SA)X02XX00 XX01Program 4555 AA 2AA 55 555A0 PA PD Unlock Bypass 3555 AA 2AA 55 55520 Unlock Bypass Program2XXX A0 PA PD Unlock Bypass Reset 2XXX90XXX00Chip Erase 6555 AA 2AA 55 55580 555 AA 2AA 55 55510Sector Erase 6555 AA 2AA 55 55580 555 AA 2AA 55 SA 30 Sector Erase Suspend 1BA B0 Sector Erase Resume 1BA 30 CFI Query 15598Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PASA = Sector Address: address of the Sector to be erased or verified (in Autoselect mode).Address bits A21-A15 uniquely select any Sector.Notes:1. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD.2. Unless otherwise noted, address bits A21-A15 are don’t cares.3. No unlock or command cycles required when device is in read mode.4. The data is 00h for an unprotected sector group and 01h for a protected sector group.。