74HC573 中文说明书

Rev. 5 — 15 August 2012
© NXP B.V. 2012. All rights reserved.
2 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
D0
D1
D2
D3
Q0 19 Q1 18 Q2 17 3-STATE Q3 16 OUTPUTS Q4 15 Q5 14 Q6 13 Q7 12
mna809
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
3 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input
Fig 6. Pin configuration DHVQFN20
Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Multiple package options ESD protection:

八D锁存器74HC573中文资料
74HC573特点：
·三态总线驱动输出
·置数全并行存取
·缓冲控制输入
·使能输入有改善抗扰度的滞后作用
原理说明：
M54HC563/74HC563/M54HC573/74HC573的八个锁存器都是透明的D型锁存器，当使能（G）为高时，Q 输出将随数据（D）输入而变。

当使能为低时，输出将锁存在已建立的数据电平上。

输出控制不影响锁存器的内部工作，即老数据可以保持，甚至当输出被关闭时，新的数据也可以置入。

这种电路可以驱动大电容或低阻抗负载，可以直接与系统总线接口并驱动总线，而不需要外接口。

特别适用于缓冲寄存器，I/O 通道，双向总线驱动器和工作寄存器。

1/12July 2001sHIGH SPEED:t PD = 13ns (TYP .) at V CC = 6V sLOW POWER DISSIPATION:I CC = 4µA(MAX.) at T A =25°C sHIGH NOISE IMMUNITY:V NIH = V NIL = 28 % V CC (MIN.)sSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 6mA (MIN)sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsWIDE OPERATING VOLTAGE RANGE:V CC (OPR) = 2V to 6VsPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573DESCRIPTIONThe M74HC573 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C 2MOS technology.This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE).While the LE input is held at a high level, the Q outputs will follow the data input precisely. When LE is taken low, the Q outputs will be latched precisely at the logic level of D input data.While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while is at high level the outputs will be in a high impedance state.The 3-State output configuration and the wide choice of outline make bus organized system simple.All inputs are equipped with protection circuits against static discharge and transient excess voltage.M74HC573OCTAL D-TYPE LATCHWITH 3 STATE OUTPUT NON INVERTINGPIN CONNECTION AND IEC LOGIC SYMBOLSORDER CODESPACKAGE TUBE T & RDIP M74HC573B1R SOP M74HC573M1RM74HC573RM13TR TSSOPM74HC573TTRM74HC5732/12INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLEX: Don’t CareZ: High Impedance(*): Q Outputs are latched at the time when the LE input is taken low logic level.LOGIC DIAGRAMPIN No SYMBOL NAME AND FUNCTION 1OE 3 State Output Enable Input (Active LOW)2, 3, 4, 5, 6, 7, 8, 9D0 to D7Data Inputs12, 13, 14, 15, 16, 17, 18, 19Q0 to Q73 State Latch Outputs11LE Latch Enable Input 10GND Ground (0V)20V CCPositive Supply VoltageINPUTSOUTPUTSOE LE D QH X X ZL L X NO CHANGE (*)L H L L LHHHM74HC5733/12ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°CRECOMMENDED OPERATING CONDITIONSSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7V V I DC Input Voltage -0.5 to V CC + 0.5V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current ± 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 35mA I CC or I GND DC V CC or Ground Current± 70mA P D Power Dissipation 500(*)mW T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue Unit V CC Supply Voltage 2 to 6V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature -55 to 125°C t r , t fInput Rise and Fall TimeV CC = 2.0V 0 to 1000ns V CC = 4.5V 0 to 500ns V CC = 6.0V0 to 400nsM74HC5734/12DC SPECIFICATIONSSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage2.0 1.5 1.5 1.5V 4.53.15 3.15 3.156.04.24.24.2V ILLow Level Input Voltage2.00.50.50.5V4.5 1.35 1.35 1.356.0 1.81.81.8V OHHigh Level Output Voltage2.0I O =-20 µA 1.9 2.0 1.9 1.9V4.5I O =-20 µA 4.4 4.5 4.4 4.46.0I O =-20 µA5.96.0 5.9 5.94.5I O =-6.0 mA 4.18 4.31 4.13 4.106.0I O =-7.8 mA 5.685.8 5.635.60V OLLow Level Output Voltage2.0I O =20 µA 0.00.10.10.1V 4.5I O =20 µA 0.00.10.10.16.0I O =20 µA 0.00.10.10.14.5I O =6.0 mA 0.170.260.330.406.0I O =7.8 mA 0.180.260.330.40I I Input Leakage Current6.0V I = V CC or GND ± 0.1± 1± 1µA I OZHigh Impedance Output Leakage Current6.0V I = V IH or V IL V O = V CC or GND ± 0.5± 5± 10µA I CCQuiescent Supply Current6.0V I = V CC or GND44080µAM74HC5735/12AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6ns)SymbolParameterTest ConditionValue UnitV CC (V)C L (pF)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t TLH t THL Output TransitionTime 2.05025607590ns 4.571215186.06101315t PLH t PHL Propagation DelayTime(LE - Q)2.05050115145175ns4.5152329356.0132025302.015060155195235ns4.5203139476.017263340t PLH t PHL Propagation DelayTime(D - Q)2.05042110140165ns4.5142228336.0121924282.015057150190225ns4.5193038456.016263238t PZL t PZH High ImpedanceOutput Enable Time2.050R L = 1 K Ω55140175210ns4.5172835426.0142430362.0150R L = 1 K Ω66180225270ns4.5223645546.019313846t PLZ t PHZ High ImpedanceOutput Disable Time 2.050R L = 1 K Ω40125155190ns4.5172531386.015212632t W(L) t W(H)Minimum Pulse Width2.050407595110ns4.581519226.07131619t sMinimum Set-up Time2.05016506575ns4.551013156.0391113t hMinimum Hold Time2.050555ns4.55556.0555M74HC5736/12CAPACITIVE CHARACTERISTICS1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /8 (per Flip Flop) and the C PD when n pcs of Flip Flop operate, can be gained by the following equation: C PD(TOTAL) = 33 + 18 x n (pF)TEST CIRCUITC L = 50pF/150pF or equivalent (includes jig and probe capacitance)R 1 = 1K Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance 5101010pF C OUT OutputCapacitance10pF C PDPower Dissipation Capacitance (note 1)51pF TESTSWITCH t PLH , t PHL Open t PZL , t PLZ V CC t PZH , t PHZGNDM74HC5737/12WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES(f=1MHz; 50% duty cycle)M74HC5738/12WAVEFORM 3: PROPAGATION DELAY TIMES(f=1MHz; 50% duty cycle)M74HC573Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2000 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom© 12/12。

TTL电路的输入端是遵循TTL标准的，其需要的输入电流很小，74HC573的输入电流在电源电压为6V，输入电压为6V的情况下，其所需要的驱动电流仅仅为0.1uA。

你给的图是说明74HC573的输出驱动能力，573的每个输出引脚都有20mA的灌入电流，因此可以直接驱动LED，而扇出电流可以达到35mA.芯片有一个极限功耗，根据封装不同其功耗也不同，所以在设计驱动的时候，在任一时间要保证芯片的功耗不要超过此参数。

比如：573的每个引脚可能灌入20mA的电流，8个引脚，总电流是160mA，乘以工作电压5V，其值为800mW,这样就超出了芯片的极限，芯片容易损坏或者寿命缩短。

另外上拉电阻的问题。

是否需要上拉电阻，对于TTL电路输入端来说并不是关键，加与不加是要看你的单片机IO口的属性。

如果单片机的输出端口是推挽输出的，那么这个上拉电阻根本没有必要，但如果单片机的IO口是开漏输出或者是内部弱上拉输出的，那这个时候就需要接一个上拉电阻。

上拉电阻的大小一般参照后级电路所需要驱动电流的5～10倍来选取，可大不可小，一般现在用10K或者4K7的比较多，但如果对功耗要求比较严格，这个电阻就需要去计算，阻值太大那么容易受干扰，太小功耗不能满足，这需要去权衡.经过试验证明：以前在开发板上(比如天祥的板子)就是利用74HC573来驱动数码管的，该板是这样的，通过位选来导通哪个数码管并通过段选来使被选中的那个数码管显示什么数字。

这里面具体接法是：数码管是共阴极的，它的公共端(如数码管的3、8脚)接到位选的74HC573的输出端Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,其中的一个如Q0(当然这里说的是一个数码管的接法，多个就接Q1，Q2,Q3,Q4一直可以接到Q7，共可以接8个数码管)对应573的管脚号是19，18，17，16，15，14，13，12。

数码管的a,b,c,d,e,f,g,h段分别接到另外一个74HC573的输出Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,对应573的管脚号是19，18，17，16，15，14，13，12。