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AD5254BRU50-RL7中文资料

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Quad 64-/256-Position I2C NonvolatileMemory Digital PotentiometersAD5253/AD5254 Rev.0Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESAD5253: Quad 64-position resolutionAD5254: Quad 256-position resolution1 kΩ, 10 kΩ, 50 kΩ, 100 kΩNonvolatile memory1 stores wiper settings with write protectionPower-on refreshed to EEMEM settings in 300 µs typ EEMEM rewrite time = 540 µs typResistance tolerance stored in nonvolatile memory12 extra bytes in EEMEM for user-defined informationI2C® compatible serial interfaceDirect read/write accesses of RDAC2 and EEMEM registers Predefined linear increment/decrement commands Predefined ±6 dB step change commandsSynchronous or asynchronous quad channel updateWiper setting readback4 MHz bandwidth—1 kΩ versionSingle supply 2.7 V to 5.5 VDual supply ±2.25 V to ±2.75 V2 slave address decoding bits allow operation of 4 devices 100-year typical data retention, T A = 55°COperating temperature: –40°C to +85°C APPLICATIONSMechanical potentiometer replacementLow resolution DAC replacementRGB LED backlight controlWhite LED brightness adjustmentRF base station power amp bias controlProgrammable gain and offset controlProgrammable attenuatorsProgrammable voltage-to-current conversion Programmable power supplyProgrammable filtersSensor calibrationsGENERAL DESCRIPTIONThe AD5253/AD5254 are quad channel, I2C, nonvolatile mem-ory, digitally controlled potentiometers with 64/256 positions, respectively. These devices perform the same electronic adjust-ment functions as mechanical potentiometers, trimmers, and variable resistors.The AD5253/AD5254’s versatile programmability allows multi-ple modes of operation, including read/write accesses in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in ±6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined informa-tion, such as memory data for other components, look-up table, or system identification information.FUNCTIONAL BLOCK DIAGRAM3824--1Figure 1.The AD5253/AD5254 allow the host I2C controllers to write any of the 64-/256-step wiper settings in the RDAC registers and store them in the EEMEM. Once the settings are stored, they are restored automatically to the RDAC registers at system power-on; the settings can also be restored dynamically.The AD5253/AD5254 provide additional increment, decrement, +6 dB step change, and –6 dB step change in synchronous or asynchronous channel update modes. The increment and decrement functions allow stepwise linear adjustments, while ±6 dB step changes are equivalent to doubling or halving the RDAC wiper setting. These functions are useful for steep-slope nonlinear adjustment applications such as white LED brightness and audio volume control.The AD5253/AD5254 have a patented resistance tolerance storing function that allows the user to access the EEMEM and obtain the absolute end-to-end resistance values of the RDACs for precision applications.The AD5253/AD5254 are available in TSSOP-20 packages in1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are guaranteed to operate over the –40°C to +85°C extended industrial temperature range.1The terms nonvolatile memory and EEMEM are used interchangeably.2The terms digital potentiometer and RDAC are used interchangeably.AD5253/AD5254Rev. 0 | Page 2 of 28TABLE OF CONTENTSElectrical Characteristics.................................................................3 1 kΩ Version..................................................................................3 10 kΩ, 50 kΩ, 100 kΩ Versions...................................................5 Interface Timing Characteristics (All Parts).............................7 Absolute Maximum Ratings............................................................8 ESD Caution..................................................................................8 Pin Configuration and Functional Descriptions..........................9 Typical Performance Characteristics...........................................10 I 2C Interface.....................................................................................14 I 2C Interface General Description............................................14 I 2C Interface Detail Description...............................................15 I 2C Compatible 2-Wire Serial Bus............................................19 Theory of Operation......................................................................20 Linear Increment and Decrement Commands......................20 ±6 dB Adjustments (Doubling/Halving Wiper Setting)........20 Digital Input/Output Configuration........................................21 Multiple Devices On One Bus..................................................21 Terminal Voltage Operation Range.........................................22 Power-Up and Power-Down Sequences..................................22 Layout and Power Supply Biasing............................................22 Digital Potentiometer Operation.............................................23 Programmable Rheostat Operation.........................................23 Programmable Potentiometer Operation...............................24 Applications.....................................................................................25 RGB LED LCD Backlight Controller.......................................25 Outline Dimensions.......................................................................27 Ordering Guide.. (27)REVISION HISTORYRevision 0: Initial VersionAD5253/AD5254ELECTRICAL CHARACTERISTICS1 kΩ VERSIONV DD = +3 V ± 10% or +5 V ± 10%, V SS = 0 V or V DD/V SS = ±2.5 V ± 10%, V A = +V DD, V B = 0 V, –40°C < T A < +85°C, unless otherwise noted.Rev. 0 | Page 3 of 28AD5253/AD5254Rev. 0 | Page 4 of 28AD5253/AD525410 kΩ, 50 kΩ, 100 kΩ VERSIONSV DD = +3 V± 10% or +5 V± 10%, V SS = 0 V or V DD/V SS = ±2.5 V ± 10%, V A = +V DD, V B = 0 V, –40°C < T A < +85°C, unless otherwise noted.Rev. 0 | Page 5 of 28AD5253/AD5254Rev. 0 | Page 6 of 28AD5253/AD5254Rev. 0 | Page 7 of 28INTERFACE TIMING CHARACTERISTICS (ALL PARTS)Guaranteed by design, not subject to production test. See Figure 23 for location of measured values. All input control voltages are specified with t R = t F = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V . Switching characteristics are measured using both V DD = 3 V and 5 V . When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I 2C interface at these pins conducts current of about 0.8 mA at V DD = 5.5 V and 0.2 mA at V DD = 2.7 V . Table 3.Parameter Symbol Conditions Min Typ 1 Max Unit SCL Clock Frequency f SCL 400 kHz t BUF Bus Free Time between STOP and START t 1 1.3 µst HD;STA Hold Time (Repeated START) t 2After this period, the first clock pulse isgenerated0.6 µs t LOW Low Period of SCL Clock t 3 1.3 µs t HIGH High Period of SCL Clock t 4 0.6 µs t SU;STA Setup Time for START Condition t 5 0.6 µs t HD;DAT Data Hold Time t 6 0 0.9 µs t SU;DAT Data Setup Time t 7 100 ns t F Fall Time of Both SDA and SCL Signals t 8 300 ns t R Rise Time of Both SDA and SCL Signals t 9 300 ns t SU;STO Setup Time for STOP Condition t 10 0.6 µs EEMEM Data Storing Time t EEMEM_STORE 26 msEEMEM Data Restoring Time at Power On 9t EEMEM_RESTORE1V DD rise time dependent. Measure without decoupling capacitors at V DD and V SS .300 µsEEMEM Data Restoring Time upon RestoreCommand or RESET Operation 9t EEMEM_RESTORE2V DD = 5 V 300 µs EEMEM Data Rewritable Time 10 t EEMEM_REWRITE 540 µs FLASH/EE MEMORY RELIABILITYEndurance 11100 kCycles Data Retention 12 100 Years1 Typical values represent average readings at 25°C and V DD = 5 V.2Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at V DD = 2.7V, I W = V DD /R for both V DD = 3 V or V DD = 5 V. 3INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V B = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 4Resistor terminals A, B, and W have no limitations on polarity with respect to each other. 5Guaranteed by design and not subject to production test. 6cmd 0 NOP should be activated after cmd 1 in order to minimize I DD_RESTORE current consumption. 7P DISS is calculated from (I DD × V DD = 5 V). 8All dynamic characteristics use V DD = 5 V. 9During power-up, all outputs preset to midscale before restoring EEMEM contents. RDAC0 has the shortest whereas RDAC3 has the longest EEMEM restore time. 10Delay time after power-on or RESET before new EEMEM data to be written. 11Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles. 12Retention lifetime equivalent at junction temperature (T J ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates with junction temperature.AD5253/AD5254Rev. 0 | Page 8 of 28ABSOLUTE MAXIMUM RATINGSTable 4. T A = 25°C, unless otherwise notedParameter Rating V DD to GND −0.3 V, +7 V V SS to GND +0.3 V, −7 V V DD to V SS 7 V V A , V B , V W to GND V SS , V DD Maximum Current I WB , I WA Pulsed ±20 mAI WB Continuous (R WB ≤ 1 kΩ, A Open)1±5 mA I WA Continuous (R WA ≤ 1 kΩ, B Open)1 ±5 mAI AB Continuous (R AB = 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1±5 mA/±500 µA/±100 µA/±50 µA Digital Inputs and Output Voltage to GND 0 V, 7 V Operating Temperature Range −40°C to +85°CMaximum Junction Temperature (T J MAX ) 150°C Storage Temperature−65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C TSSOP-20 Thermal Resistance 2 θJA 143°C/WStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.1Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. V DD = 5V. 2Package power dissipation = (T JMAX − T A )/θJA .ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.AD5253/AD5254Rev. 0 | Page 9 of 28PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONSAD5253/AD5254TOP VIEW(Not to Scale)W01B02A03AD045W11B12A13SDA 4V SS 5V DD W3B3A3AD1109876DGND SCL W2B2A210987603842-0-002WPFigure 2. AD5253/AD5254 Pin ConfigurationAD5253/AD5254Rev. 0 | Page 10 of 28TYPICAL PERFORMANCE CHARACTERISTICSR -I N L (L S B )CODE (Decimal)03824-0-015–1.0–0.8–0.6–0.4–0.200.20.40.60.81.00326496128160192224256Figure 3. R-INL vs. CodeR D N L (L S B )CODE (Decimal)03824-0-016–1.0–0.8–0.6–0.4–0.200.20.40.60.81.00326496128160192224256Figure 4. R-DNL vs. CodeI N L (L S B )CODE (Decimal)03824-0-017–1.0–0.8–0.6–0.4–0.200.20.40.60.81.00326496128160192224256Figure 5. INL vs. Code I N L (L S B )CODE (Decimal)03824-0-018–1.0–0.8–0.6–0.4–0.200.20.40.60.81.00326496128160192224256Figure 6. DNL vs. CodeS U P P L Y C U R R E N T (µA )TEMPERATURE (°C)03824-0-019–10–8–6–4–20246810–40–20020406080100120Figure 7. Supply Current vs. TemperatureDIGITAL INPUT VOLTAGE (V)03824-0-0200.00010.010.0010.11100123456I D D (m A )Figure 8. Supply Current vs. Digital Input Voltage. T A = 25°CR W B (Ω)V BIAS (V)03824-0-021204060801001201401602002401802201023456Figure 9. Wiper Resistance vs. V BIASTEMPERATURE (°C)03824-0-022–6–4–2246–40–20020406080100120∆R W B (%)Figure 10. Change of R AB vs. TemperatureCODE (Decimal)03824-0-023050607020103040809006496128160192224256R H E O S T A T MO D E T E M P C O (p p m /°C )Figure 11. Rheostat Mode Tempco (∆R WB /R WB )/∆T × 106 vs. CodeCODE (Decimal)03824-0-02420251051530P O T E N T I O M E T E R M O D E T E M P C O (p p m /°C )Figure 12. Potentiometer Mode Tempco (∆V WB /V WB )/∆T × 106 vs. Code–60–48–24–120–36–54–30–18–6–42G A I N(d B )1k10k10100100k1M10MFREQUENCY (Hz)03824-0-025Figure 13. Gain vs. Frequency vs. Code, R AB = 1 kΩ, T A = 25°C–60–48–24–120–36–54–30–18–6–42G A I N (d B )1k 10k 10100100k 1M 10MFREQUENCY (Hz)03824-0-026Figure 14. Gain vs. Frequency vs. Code, R AB = 10 kΩ, T A = 25°C–60–48–24–120–36–54–30–18–6–42G A I N (d B )1k10k 10100100k 1M 10M FREQUENCY (Hz)03824-0-027Figure 15. Gain vs. Frequency vs. Code, R AB = 50 kΩ, T A = 25°C–60–48–24–120–36–54–30–18–6–42G A I N (d B )1k10k 10100100k 1M 10MFREQUENCY (Hz)03824-0-028Figure 16. Gain vs. Frequency vs. Code, R AB = 100 kΩ, T A = 25°C∆R A B (Ω)CODE (Decimal)03824-0-029–100–80–60–40–200204060801000326496128160192224256Figure 17. ∆R AB vs. Code, T A = 25°CCLOCK FREQUENCY (Hz)03824-0-0300.60.40.20.81.01.21100101k 10k 100k 1M 10MI D D (m A )Figure 18. Supply Current vs. Digital Input Clock Frequency03824-0-031DIGITAL FEEDTHROUGHCLK VDD = 5VV WMID-SCALE TRANSITION7FH ≥ 80HFigure 19. Clock Feedthrough and Midscale Transition Glitch03824-0-046VWB0(0xFF STORED IN EEMEM)VWB3(0xFF STORED IN EEMEM)VDD = VA0 = VA3 = 3.3V GND = VB0 = VB3MIDSCALE PRESETRESTORE RDAC0SETTING TO 0xFFRESTORE RDAC3SETTING TO 0xFFVDD (NO DE-COUPLING CAPS)MIDSCALE PRESETFigure 20. t EEMEM_RESTORE of RDAC0 and RDAC3CODE (Decimal)03824-0-0330321456816243240485664T H E O R E T I C A L I W B _M A X (m A )Figure 21. I WB_MAX vs. Code (AD5253) CODE (Decimal)03824-0-034321456326496128160192224256T H E O R E T I C A L I W B _M A X (m A)Figure 22. I WB_MAX vs. Code (AD5254)I 2C INTERFACESCLSDA03Figure 23. I 2C Interface Timing DiagramI 2C INTERFACE GENERAL DESCRIPTIONFrom Master to SlaveFrom Slave to MasterS = Start Condition. P = Stop Condition.A = Acknowledge (SDA Low).A = Not Acknowledge (SDA High).R/W = Read Enable at High; Write Enable at Low.0 WRITE(N BYTES + ACKNOWLEDGE)038Figure 24. I 2C—Master Writing Data to Slave1 READ(N BYTES + ACKNOWLEDGE)038Figure 25. I 2C—Master Reading Data From SlaveDIRECTION OF TRANSFER MAYCHANGE AT THIS POINTFigure 26. I 2C—Combined Write/ReadI 2C INTERFACE DETAIL DESCRIPTIONFrom Master to SlaveFrom Slave to MasterS = Start Condition. P = Stop Condition.A = Acknowledge (SDA Low).AD1, AD0 = I 2C Device Address Bits. Must match with the logic states at Pins AD1, AD0. R/W = Read Enable Bit, Logic High/Write Enable Bit, Logic Low.CMD/REG = Command Enable Bit, Logic High/Register Access Bit, Logic Low. EE/RDAC = EEMEM Register, Logic High/RDAC Register, Logic Low. A4, A3, A2, A1, A0 = RDAC/EEMEM Register Addresses.03842-0-007(1 BYTE +ACKNOWLEDGE)0 REGFigure 27. Single Write Mode03842-0-008(N BYTE +ACKNOWLEDGE)0 REGFigure 28. Consecutive Write ModeTable 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)A4 A3 A2 A1 A0 RDAC Data Byte Description0 0 0 0 0 RDAC0 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 0 0 0 0 1 RDAC1 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 0 0 0 1 0 RDAC2 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 0 0 0 1 1 RDAC3 6-/8-bit wiper setting (2 MSBs of AD5253 are X) 0 0 1 0 0 Reserved : : : : :0 1 1 1 1 ReservedRDAC/EEMEM WriteSetting the wiper position requires an RDAC write operation. The single write operation is shown in Figure 27, and the consecutive write operation is shown in Figure 28. In consecutive write operation, if the RDAC is selected and the address starts at 0, the first data byte goes to RDAC0, the second data byte goes to RDAC1, the third data byte goes to RDAC2, and the fourth data byte goes to RDAC3. This operation can be continued up to eight addresses with four unused addresses; it then loops back to RDAC0. If the address starts at any of the eight valid addresses, N, the data first goes to RDAC_N, RDAC_N + 1, and so on; it loops back to RDAC0 after the eighth address. The RDAC address is shown in Table 6.While the RDAC wiper setting is controlled by a specific RDAC register, each RDAC register corresponds to a specific EEMEM memory location, which provides nonvolatile wiper storage functionality. The addresses are shown in Table 7. The single and consecutive write operations also apply to EEMEM write operations.There are 12 nonvolatile memory locations, EEMEM4 to EEMEM15, where users can store 12 bytes of information such as memory data for other components, look-up table, or system identification information.In a write operation to the EEMEM registers, the device disables the I2C interface during the internal write cycle. Acknowledge polling, which is discussed later in the data sheet, is required to determine the completion of the write cycle.RDAC/EEMEM ReadThe AD5253/AD5254 provide two different RDAC or EEMEM read operations. For example, Figure 29 shows the method of reading the RDAC0 to RDAC3 contents without specifying the address, assuming address RDAC0 was already selected from the previous operation. If RDAC_N, other than address 0, is selected previously, readback starts with address N, followed by N + 1, and so on.Figure 30 illustrates the random RDAC or EEMEM read opera-tion. This operation allows users to specify which RDAC or EEMEM register is read by first issuing a dummy write command to change the RDAC address pointer, and then proceeding with the RDAC read operation at the new address location. Table 7. Addresses for Writing (Storing) RDAC Settings and User-Defined Data to EEMEM Registers (R/W = 0,CMD/REG = 0, EE/RDAC = 1)A4 A3 A2 A1 A0 DataByteDescription0 0 0 0 0 Store RDAC0 Setting to EEMEM01 0 0 0 0 1 Store RDAC1 Setting to EEMEM11 0 0 0 1 0 Store RDAC2 Setting to EEMEM21 0 0 0 1 1 Store RDAC3 Setting to EEMEM31 0 0 1 0 0 Store User Data to EEMEM40 0 1 0 1 Store User Data to EEMEM50 0 1 1 0 Store User Data to EEMEM60 0 1 1 1 Store User Data to EEMEM70 1 0 0 0 Store User Data to EEMEM80 1 0 0 1 Store User Data to EEMEM90 1 0 1 0 Store User Data to EEMEM100 1 0 1 1 Store User Data to EEMEM110 1 1 0 0 Store User Data to EEMEM120 1 1 0 1 Store User Data to EEMEM130 1 1 1 0 Store User Data to EEMEM140 1 1 1 1 Store User Data to EEMEM15Table 8. Addresses for Reading (Restoring) RDAC Settings and User Data from EEMEM (R/W = 1, CMD/REG = 0,EE/RDAC = 1)A4 A3 A2 A1 A0 Data Byte Description0 0 0 0 0 Read RDAC0 setting from EEMEM0 0 0 0 0 1 Read RDAC1 setting from EEMEM1 0 0 0 1 0 Read RDAC2 setting from EEMEM2 0 0 0 1 1 Read RDAC3 setting from EEMEM3 0 0 1 0 0 Read User Data from EEMEM40 0 1 0 1 Read User Data from EEMEM50 0 1 1 0 Read User Data from EEMEM60 0 1 1 1 Read User Data from EEMEM70 1 0 0 0 Read User Data from EEMEM80 1 0 0 1 Read User Data from EEMEM90 1 0 1 0 Read User Data from EEMEM100 1 0 1 1 Read User Data from EEMEM110 1 1 0 0 Read User Data from EEMEM120 1 1 0 1 Read User Data from EEMEM130 1 1 1 0 Read User Data from EEMEM140 1 1 1 1 Read User Data from EEMEM151 User can store any 64 RDAC settings for AD5253 or 256 RDAC settings for AD5254, not limited to current RDAC wiper setting, directly to EEMEM.1 READ03842-0-009Figure 29. RDAC Current Read. Restricted to Previously Selected Address Stored in the Register.0 WRITE038REPEATED START 1 READFigure 30. RDAC or EEMEM Random Read0 WRITE 03842-0-0111 CMDRDAC SLAVE ADDRESSFigure 31. RDAC Quick Command Write (Dummy Write)From Master to SlaveFrom Slave to MasterS = Start Condition P = Stop ConditionA = Acknowledge (SDA Low)A = Not Acknowledge (SDA High)AD1, AD0 = I 2C Device Address Bits. Must match with the logic states at Pins AD1, AD0. R/W = Read Enable Bit, Logic High/Write Enable Bit, Logic LowCMD/REG = Command Enable Bit, Logic High/Register Access Bit, Logic Low C3, C2, C1, C0 = Command BitsA2, A1, A0 = RDAC/EEMEM Register AddressesTable 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0)C3 C2 C1 C0 Command Description 0 0 0 0 NOP 0 0 0 1 Restore EEMEM (A1, A0) to RDAC (A1, A0)10 0 1 0 Store RDAC (A1, A0) to EEMEM (A1, A0) 0 0 1 1 Decrement RDAC (A1, A0) 6 dB 0 1 0 0 Decrement All RDACs 6 dB 0 1 0 1 Decrement RDAC (A1, A0) One Step 0 1 1 0 Decrement All RDACs One Step 0 1 1 1 Reset: Restore EEMEMs to All RDACs 1 0 0 0 Increment RDACs (A1, A0) 6 dB 1 0 0 1 Increment All RDACs 6 dB 1 0 1 0 Increment RDACs (A1, A0) One Step 1 0 1 1 Increment All RDACs One Step 1 1 0 0 Reserved : : : :1 1 1 1 ReservedRDAC/EEMEM Quick CommandsAD5253/AD5254 feature 12 quick commands that facilitate easy manipulation of RDAC wiper settings as well as provide RDAC-to-EEMEM storing and restoring functions. The command format is shown in Figure 31, and the command descriptions are shown in Table 9.When using a quick command, issuing a third byte is not needed but is allowed. The quick commands Reset and Store RDAC to EEMEM require acknowledge polling to determine whether the command has finished executing.1This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to the idle state.Table 10. Address Table for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1)A4 A3 A2 A1 A0 Data Byte Description 1 1 0 0 0 Sign and 7-Bit Integer Values of RDAC0 Tolerance (Read Only) 1 1 0 0 1 8-Bit Decimal Value of RDAC0 Tolerance (Read Only) 1 1 0 1 0 Sign and 7-Bit Integer Values of RDAC1 Tolerance (Read Only) 1 1 0 1 1 8-Bit Decimal Value of RDAC1 Tolerance (Read Only) 1 1 1 0 0 Sign and 7-Bit Integer Values of RDAC2 Tolerance (Read Only) 1 1 1 0 1 8-Bit Decimal Value of RDAC2 Tolerance (Read Only) 1 1 1 1 0 Sign and 7-Bit Integer Values of RDAC3 Tolerance (Read Only) 1 1 1 1 1 8-Bit Decimal Value of RDAC3 Tolerance (Read Only)03842-0-012AAAD7D6D5D4D3D2D1D0SIGNSIGN7 BITS FOR INTEGER NUMBER 26252423222120D7D6D5D4D3D2D1D08 BITS FOR DECIMAL NUMBER2–82–12–22–32–42–52–62–7Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. Unit is %. Only Data Bytes Are Shown.R AB Tolerance Stored in Read-Only MemoryAD5253/AD5254 feature patented R AB tolerances storage in the nonvolatile memory. The tolerance of each channel is stored in the memory during the factory production and can be read by users at any time. The knowledge of the stored tolerance, which is the average of R AB overall codes (Figure 29), allows users to predict R AB accurately. This feature is valuable for precision, rheostat mode, or open-loop applications where knowledge of absolute resistance is critical.The stored tolerances reside in the read-only memory, and are expressed in percent. The tolerance is coded in sign magnitude binary, 16 bits long, and is stored in two memory locations (see Table 10). The data format of the tolerance is the sign magni-tude binary format; an example is shown in Figure 32. In the first memory location of the eight data bits, the MSB is designated for the sign (0 = + and 1= –) and the 7 LSBs are designated for the integer portion of the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. As shown in Table 8 and Figure 32, for example, if the rated R AB = 10 kΩ and the data readback from address 11000 shows 0001 1100 and address 11001 shows 0000 1111, then RDAC0 tolerance can be calculated as:MSB: 0 = +Next 7 MSB: 001 1100 = 288 LSB: 0000 1111 = 15 × 2–8 = 0.06 Tolerance = +28.06% and therefore R AB_ACTUAL = 12.806 kΩ EEMEM Write-Acknowledge PollingAfter each write operation to the EEMEM registers, an internal write cycle begins. The I 2C interface of the device is disabled. In order to determine if the internal write cycle is complete and the I 2C interface is enabled, interface polling can be executed. I 2C interface polling can be conducted by sending a start condi-tion followed by the slave address + the write bit. If the I 2Cinterface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. Other-wise, I 2C interface polling can be repeated until it succeeds. Commands 2 and 7 also require acknowledge polling.EEMEM Write ProtectionSetting the WP pin to a logic LOW after EEMEM programming protects the memory and RDAC registers from future write operations. In this mode, the EEMEM and RDAC readoperations operate as normal. When write protection is enabled, commands 1 (restore from EEMEM to RDAC) and 7 (reset) function normally to allow RDAC settings to be refreshed from the EEMEM to the RDAC registers.。

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AD9854中文数据手册

AD9854中文数据手册

AD9854特征·300M内部时钟频率·可进行频移键控（FSK），二元相移键控（BPSK），相移键控（PSK），脉冲调频（CHIRP），振幅调制（AM）操作·正交的双通道12位D/A转换器·超高速比较器，3皮秒有效抖动偏差·外部动态特性：80 dB无杂散动态范围（SFDR）@ 100 MHz (±1 MHz) A OUT·4倍到20倍可编程基准时钟乘法器·两个48位可编程频率寄存器·两个14位可编程相位补偿寄存器·12位振幅调制和可编程的通断整形键控功能·单引脚FSK和BPSK数据输入接口·PSK功能可由I/O接口实现·具有线性和非线性的脉冲调频（FM CHIRP）功能，带有引脚可控暂停功能·具有过渡FSK功能·在时钟发生器模式下，有小于25 ps RMS抖动偏差·可自动进行双向频率扫描·能够对信号进行sin(x)/x校正·简易的控制接口：可配置为10MHZ串行接口，2线或3线SPI兼容接口或100MHZ 8位并行可编程接口·3.3V单电源供电·具有多路低功耗功能·单输入或差分输入时钟·小型80脚LQFP 封装应用·便携式频率特性分析仪·可编程时钟发生器·应用于雷达和扫频系统的脉冲调频信号源·测试和测量设备·商业和业余的射频（RF）发射机概述AD9854数字合成器是高集成度的器件，它采用先进的DDS技术，片内整合了两路高速、高性能正交D/A转换器通过数字化编程可以输出I、Q两路合成信号。

在高稳定度时钟的驱动下，AD9854将产生一高稳定的频率、相位、幅度可编程的正弦和余弦信号，作为本振用于通信，雷达等方面。

AD9854的DDS核具有48位的频率分辨率（在300M系统时钟下，频率分辨率可达1uHZ）。

AD5282BRU50中文资料

AD5282BRU50中文资料

PRELIMINARY TECHNICAL DATAa+15V, I 2C Compatible Digital PotentiometersPreliminary Technical Data AD5280/AD5282REV PrE 12 MAR 02Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U .S .A . FEATURES 256 PositionAD5280 – 1-ChannelAD5282 – 2-Channel (Independently Programmable) Potentiometer Replacement20K, 50K, 200K Ohm with TC < 50ppm/ºC Internal Power ON Mid-Scale Preset+5 to +15V Single-Supply; ±5.5V Dual-Supply Operation I 2C Compatible InterfaceAPPLICATIONSMulti-Media, Video & Audio CommunicationsMechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage to Current Conversion Line Impedance MatchingGENERAL DESCRIPTIONThe AD5280/AD5282 provides a single/dual channel, 256 position digitally-controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as apotentiometer, trimmer or variable resistor. Each VR offers a completely programmable value of resistance, between the Aterminal and the wiper, or the B terminal and the wiper. The fixed A-to-B terminal resistance of 20, 50 or 200K ohms has a 1%channel-to-channel matching tolerance with a nominal temperature coefficient of 30 ppm/°C.Wiper Position programming defaults to midscale at system power ON. Once powered the VR wiper position is programmed by a I 2C compatible 2-wire serial data interface. Both parts have twoprogrammable logic outputs available to drive digital loads, gates, LED drivers, analog switches, etc.FUNCTIONAL BLOCK DIAGRAMSA WB O OA W BA WB AD0AD1OThe AD5280/AD5282 are available in ultra compact surface mount thin TSSOP-14/-16 packages. All parts are guaranteed to operate over the extended industrial temperature range of -40°C to +85°C. For 3-wire, SPI compatible interface applications, seeAD5203/AD5204/AD5206/AD7376/AD8400/AD8402/AD8403/ AD5260/AD5262/AD5200/AD5201 products.The AD5280/AD5282 die size is 75 mil X 120 mil, 9,000 sq. mil. Contains xxx transistors. Patent Number xxx applies.元器件交易网PRELIMINARY TECHNICAL DATAAD5280/AD52822 REV PrE 12 MAR 02ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (V DD = +5V, V SS = -5V, V LOGIC = +5V, V A = +V DD , V B = 0V, -40°C < T A < +85°C unless otherwise noted.) Parameter Symbol Conditions Min Typ 1MaxUnits元器件交易网PRELIMINARY TECHNICAL DATAAD5280/AD5282REV PrE 12 MAR 02 3ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (V DD = +5V, V SS = -5V, V LOGIC = +5V, V A = +V DD , V B = 0V, -40°C < T A < +85°C unless otherwise noted.) Parameter Symbol Conditions Min Typ 1MaxUnitsNOTES:1. Typicals represent average readings at +25°C, V DD = +5V, V SS = -5V.2.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3. V AB = V DD , Wiper (V W ) = No connect 4. INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V B = 0V. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. 5. Resistor terminals A,B,W have no limitations on polarity with respect to each other. 6. Guaranteed by design and not subject to production test. 9. Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R valueresult in the minimum overall power consumption.10. P DISS is calculated from (I DD x V DD ). CMOS logic level inputs result in minimum power dissipation. 11. All dynamic characteristics use V DD = +5V.12. See timing diagram for location of measured values.元器件交易网PRELIMINARY TECHNICAL DATAAD5280/AD52824 REV PrE 12 MAR 02ABSOLUTE MAXIMUM RATINGS (T A = +25°C, unless otherwise noted)V DD to GND.............................................................-0.3, +15V V SS to GND..................................................................0V, -7V V DD to V SS ...................................................................... +15V V A , V B , V W to GND...................................................V SS , V DD A X – B X , A X – W X , B X – W X .........................................±20mA Digital Input Voltage to GND.........................................0V, 7V Operating Temperature Range...........................-40°C to +85°C Thermal Resistance * θJA,TSSOP-14........................................................206°C/W TSSOP-16........................................................180°C/W Maximum Junction Temperature (T J MAX )....................+150°C Storage Temperature........................................-65°C to +150°C Lead TemperatureRU-14, RU-16 (Vapor Phase, 60 sec) .......................+215°C RU-14, RU-16 (Infrared, 15 sec) ..............................+220°C*Package Power Dissipation (T J MAX - T A ) / θJAAD5280 PIN CONFIGURATIONA WB V DD SHDN SHDN SCL SDA O1 V L O2 V SS GND AD1 AD014 13 12 11 10 981 2 3 4 5 6 7AD5282 PIN CONFIGURATIONO1 A1 W1 B1 V DD SHDN SHDN SCL SDAA2 W2 B2 V L V SSGND AD1 AD016 15 14 13 12 11 10 91 2 3 4 5 6 7 8TABLE 1: AD5280 PIN Function Descriptions Pin Name Description1 A Resistor terminal A2 W Wiper terminal W3 B Resistor terminal B4 V DDPositive power supply, specified foroperation from +5 to +15V.5 SHDN Active Low, Asynchronous connection ofthe wiper W to terminal B, and open circuit of terminal A. RDAC register contents unchanged.6 SCL Serial Clock Input7 SDA Serial Data Input/Output8 AD0 Programmable address bit for multiplepackage decoding. Bits AD0 & AD1 provide 4 possible addresses.9 AD1 Programmable address bit for multiplepackage decoding. Bits AD0 & AD1 provide 4 possible addresses.10 GND Common Ground 11 V SS Negative power supply, specified for operation from 0 to -5V 12 O2 Logic Output terminal O213 V LLogic Supply Voltage, needs to be same voltage as the digital logic controlling the AD5280.14 O1Logic Output terminal O1元器件交易网PRELIMINARY TECHNICAL DATAAD5280/AD5282REV PrE 12 MAR 02 5TABLE 2: AD5282 PIN Function Descriptions Pin Name Description1 O1 Logic Output terminal O12 A 1 Resistor terminal A 13 W 1 Wiper terminal W 14 B 1 Resistor terminal B 15 V DD Positive power supply, specified for operation from +5 to +15V.6SHDNActive Low, Asynchronous connection of the wiper W to terminal B, and open circuit of terminal A. RDAC register contents unchanged. 7SCL Serial Clock Input8 SDASerial Data Input/Output9AD0Programmable address bit for multiple package decoding. Bits AD0 & AD1 provide 4 possible addresses.10 AD1 Programmable address bit for multiplepackage decoding. Bits AD0 & AD1 provide 4 possible addresses.11 GND Common Ground 12 V SS Negative power supply, specified for operation from 0 to -5V13 V LLogic Supply Voltage, needs to be same voltage as the digital logic controlling the AD5282.14 B 2 Resistor terminal B 2 15 W 2 Wiper terminal W 2 16 A 2 Resistor terminal A 2SDASCLData of AD5280/AD5282 is accepted from the I 2C bus in the following serial format:S 0 1 0 1 1 AD 1A D 0R/WAA /BR SS DO 1O 2X X X A D7D 6D 5D 4D 3D 2D 1D 0A PSlave Address Byte Instruction Byte Data ByteWhere:S = Start Condition P = Stop Condition A = Acknowledge X = Don’t CareAD1, AD0 = Package pin programmable address bits R/W = Read Enable at High and Write Enable at LowA /B = RDAC sub address select. “Zero” for RDAC1 and “One” for RDAC2 SD = Shutdown, same as SHDN pin operation except inverse logic O2, O1 = Output logic pin latched values D7,D6,D5,D4,D3,D2,D1,D0 = Data BitsSCL SDA1910110AD0AD1R/WACK.BY AD5280D7D6D5D3D4D0D1D219ACK.BY AD5280A/B RS SD O2O1X X X 19ACK.BY AD5280FRAME 1Slave Address Byte START BY MASTERFRAME 2Instruction Byte FRAME 3Data ByteFigure 2. Writing to the RDAC Register元器件交易网PRELIMINARY TECHNICAL DATAAD5280/AD52826 REV PrE 12 MAR 02SCL SDA19111AD0AD1R/WACK.BY AD528019D7D6D5D3D4D0D1D2NO ACK.BY MASTERFRAME 1Slave Address ByteSTART BY MASTERFRAME 2Data From Selected RDAC Regis terSTOP BY MASTERFigure 3. Reading Data from a Previously Selected RDAC RegisterOPERATIONThe AD5280/AD5282 provides a single/dual channel, 256-position digitally-controlled variable resistor (VR) device. The terms VR and RDAC are used interchangeably throughout this documentation. To program the VR settings, refer to the Digital Interface section. Both parts have an internal power ON preset that places the wiper in mid scale during power on, whichsimplifies the fault condition recovery at power up. In addition, the shutdown SHDN pin of AD5280/AD5282 places the RDAC in a zero power consumption state where terminal A is open circuited and the wiper W is connected to terminal B, resulting in only leakage currents being consumed in the VR structure. In shutdown mode the VR latch settings are maintained, so that, returning to operational mode from power shutdown, the VR settings return to their previous resistance values.PROGRAMMING THE VARIABLE RESISTOR Rheostat OperationThe nominal resistance of the RDAC between terminals A and B are available in 20K Ω, 50K Ω, and 200K Ω. The final three digits of the part number determine the nominal resistance value, e.g. 20K Ω = 20; 50K Ω = 50; 200K Ω = 200. The nominal resistance (R AB ) of the VR has 256 contact pointsaccessed by the wiper terminal, plus the B terminal contact. The eight bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assume a 20K Ω part is used, the wiper's first connection starts at the B terminal for data 00H . Since there is a 60Ω wiper contact resistance, such connection yields a minimum of 60Ω resistance between terminals W and B. The second connection is the first tap point corresponds to 138Ω (R WB = R AB /256 + R W = 78Ω+60Ω) for data 01H . The third connection is the next tap point representing 216Ω (78x2+60)for data 02H and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19982Ω [R AB –1LSB+R W ]. The wiper does not directly connect to the B terminal. See Figure 4 for a simplified diagram of the equivalent RDAC circuit.The general equation determining the digitally programmed output resistance between W and B is: 1 eqn. 256)(W AB WB R R DD R +⋅=where D is the decimal equivalent of the binary code which is loaded in the 8-bit RDAC register, and R AB is the nominal end-to-end resistance.For example, R AB =20K Ω, when V B = 0V and A–terminal is open circuit, the following output resistance values R WB will be set for the following RDAC latch codes. Result will be the same if terminal A is tied to W:Note that in the zero-scale condition a finite wiper resistance of 60Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum current of no more than 5mA. Otherwise, degradation or possible destruction of the internal switch contact can occur.Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled resistance R WA . When these terminals are used the B–terminal should be let open or tied to the wiper terminal. Setting the resistance value for R WA starts at amaximum value of resistance and decreases as the data loaded in the latch is increased in value. The general equation for this operation is: 2 eqn. 256256)(W AB WA R R DD R +⋅−=元器件交易网PRELIMINARY TECHNICAL DATAAD5280/AD5282REV PrE 12 MAR 02 7For example, R AB =20K Ω, when V A = 0V and B–terminal is open circuit, the following output resistance R WA will be set for the following RDAC latch codes. Result will be the same if terminal B is tied to W:The typical distribution of the nominal resistance R AB from channel-to-channel matches within ±1%. Device to devicematching is process lot dependent and is possible to have ±30% variation. Since the resistance element is processed in thin film technology, the change in R AB with temperature has a 30 ppm/°C temperature coefficient.PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output OperationThe digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the inputvoltage at A-to-B. Let’s ignore the effect of the wiper resistance at the moment. For example connecting A–terminal to +5V and B–terminal to ground produces an output voltage at the wiper-to-B starting at zero volts up to 1 LSB less than +5V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 position of the potentiometer divider. Since AD5280/AD5282 can be supplied by dual supplies, the general equation defining the output voltage at V W with respect toground for any given input voltage applied to terminals AB is: 3 eqn. 256256256)(B A W V D V D D V −+=where D is decimal equivalent of the binary code which is loaded in the 8-bit RDAC register.Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent on the ratio of the internal resistors R WA and R WB and not the absolute values, therefore, the temperature drift reduces to 5ppm/°C.DIGITAL INTERFACE 2-WIRE SERIAL BUSThe AD5280/AD5282 are controlled via an I 2C compatible serial bus. The RDACs are connected to this bus as slave devices.Referring from Figures 2 and 3, the first byte ofAD5280/AD5282 is a Slave Address Byte. It has a 7-bit slave address and a R/W bit. The 5 MSBs are 01011 and the following2 bits are determined by the state of the AD0 and AD1 pins ofthe device. AD0 and AD1 allow the user to use up to four of these devices on one bus.The 2-wire I 2C serial bus protocol operates as follows:1. The master initiates data transfer by establishing a STARTcondition, which is when a high-to-low transition on the SDA line occurs while SCL is high, Figure 2. Thefollowing byte is the Slave Address Byte which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device).The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. On the other hand, if the R/W bit is low, the master will write to the slave device.2. A Write operation contains an extra Instruction Byte morethan the Read operation. Such Instruction Byte in Write mode follows the Slave Address Byte. The MSB of the Instruction Byte labeled A /B is the RDAC sub-addressselect. A “low” select RDAC1 and a “high” selects RDAC2 for dual channel AD5282. The 2nd MSB RS is the Mid-scale reset. A logic high of this bit moves the wiper of a selected RDAC to the center tap where R WA =R WB . The 3rd MSB SD is a shutdown bit. A logic high causes the RDAC open circuit at terminal A while shorting wiper to terminal B. This operation yields almost a zero Ohm in rheostat mode or zero volt in potentiometer mode. This SD bitserves the same function as the SHDN pin except it reacts in active low. The following two bits are O2 and O1. They are extra programmable logic output that users can make use of them by driving other digital loads, logic gates, LED drivers, and analog switches, etc. The 3 LSBs are DON’T CARE. See Figure 2. 3. After acknowledged the Instruction Byte, the last byte inWrite mode is the Data Byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an “Acknowledge” bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL, Figure 1. 4. In Read mode, the Data Byte goes right after theacknowledgment of the Slave Address Byte. Data istransmitted over the serial bus in sequences of nine clock pulses (slight difference with the Write mode, there are eight data bits followed by a “No Acknowledge” bit). Similarly, the transitions on the SDA line must occurduring the low period of SCL and remain stable during the high period of SCL. 5. When all data bits have been read or written, a STOPcondition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In Write mode, the master will pull the SDA line high during the 10th clock pulse to establish a STOP元器件交易网PRELIMINARY TECHNICAL DATAAD5280/AD52828 REV PrE 12 MAR 02condition, Figure 2. In Read mode, the master will issue a No Acknowledge for the 9th clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the 10th clock pulse which goes high to establish a STOP condition, Figure 3.A repeated Write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. During the Write cycle, each Data byte will update the RDAC output. For example, after the RDAC has acknowledged its Slave Address and Instruction Bytes, the RDAC output will update after these two bytes. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. If different instructions are needed, the Write mode has to start with a new Slave Address, Instruction, and Data Bytes again. Similarly, a repeated Read function of the RDAC is also allowed. MULTIPLE DEVICES ON ONE BUSFigure 5 shows four AD5282 devices on the same serial bus. Each has a different slave address sine the state of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain pull downs in a fully I 2C compatible interface.SDASCLFigure 5. Multiple AD5282 Devices on One BusLEVEL SHIFT FOR BI-DIRECTIONAL INTERFACE While most old systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper method of level shifting is needed. For instance, one can use a 3.3V E 2PROM to interface with a 5V digital potentiometer. A level shift scheme is needed in order to enable a bi-directional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E 2PROM. Figure 6shows one of the techniques. M1 and M2 can be N-Ch FETs 2N7002 or low threshold FDV301N if V DD falls below 2.5V.SDA1SCL1SDA2SCL2V =5VFigure 6. Level Shift for different potential operation.All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in figure 7. Applies to元器件交易网PRELIMINARY TECHNICAL DATAAD5280/AD5282REV PrE 12 MAR 02 9TEST CIRCUITSFigures 9 to 17 define the test conditions used in product specification table.Figure 9. Potentiometer Divider Nonlinearity error test circuit(INL, DNL)Figure 10. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)Figure 11. Wiper Resistance test CircuitFigure 12. Power supply sensitivity test circuit (PSS, PSSR)Figure 13. Inverting Gain test CircuitFigure 14. Non-Inverting Gain test circuitFigure 15. Gain Vs Frequency test circuitFigure 16. Incremental ON Resistance Test CircuitFigure 17. Common Mode Leakage current test circuit元器件交易网PRELIMINARY TECHNICAL DATAAD5280/AD528210 REV PrE 12 MAR 02OUTLINE DIMENSIONSDimensions shown in inches and (mm)元器件交易网。

ADW-510ACC-A型(欧洲)中文规格书

ADW-510ACC-A型(欧洲)中文规格书


备注：
1.所有的供料斗、计量斗及集合斗均采用白色轴承。 58
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制造编号 2 数量 1 台 型号 4 仪表 1：RCU-900 2：RCU901C 1 pcs 客户 最终用户 6 国家 目的地港口 AC 220 V / 50 Hz 要求出厂日期 8 电压频率 1: 无 2: 单个 1: 重量式 供料锥 3: 双分式 4: 双分式+分流器 2: 光电对射式 10 料位控制 5: 分流槽体(ADW514AC_粉体) 3: 光电反射式 1: 单个 (ADW510/514/314AC) 4: 无 主振 2: 两个 (ADW520AC) 1: 扁平 2: V-型 12 线性振动盘形状 3: 无 (ADW514AC_粉体) 3: U-型 4：其他 料斗 溜槽 1: 45 (ADW510AC,520AC_单个) 1: 平板 2: 花纹板 (角度) 2: 50 (ADW514AC,ADW514AWC) 振动盘 1: 单个 (ADW510/514/520/314AC) 3: 55 (ADW520AC_两个) 4: 60 (ADW514AHC) 15 集合锥 2: 两个 (ADW520AC) 5: 52 (ADW314AC) 6: 65 (ADW514AC_粉体) C-C = 900 / 724 / 600mm 7: 8: 1: 无 2:单方向 9: 其他 ( ) 2: 有 (YCO需要用) 3: 双方向 4: 特殊（ ） 17 集合锥托架 1: 无 集合斗(CB) 0.5L 1L 3L 5L 7.5L 容量 18 仪表电缆长度 8 m (= 标准) 横拉式 1: 否 2：是 1:英语 2:德语 3:法语 4:意大利语 5:波兰语 6:西班牙语 7:日语 8:中文(简) 9:中文(繁) 10:荷兰语 11:丹麦语 12:芬兰语 仪表显示语言 13:瑞典 14:匈牙利语 15:俄语 16:波兰语 17:捷克语 18:土耳其语 19:斯洛文尼亚 20:葡萄牙语 21:克罗地亚 22:韩语 认证 1：无 2：CE认证 3：UL&Cul 4:其他（ ） 可选 1: 无 1: 无 打印机(PRT90) 2: 有 2. 普通防碎装置 1: 无 2: 整体式 23 防碎装置 3. 上下式防碎装置 料层调整装置 3: 两个(仅用于ADW520AC) 4. 固定式防碎装置 4: 独立分开式 5: 其他（集合斗防碎装置） 1. 无 25 RS232C端子 1: 无 2: 有 供给装置 2. 有（ 电磁式振动给料机 ） 27 大斗 1: 否 2: 是 1: 无 2: A 型 (侧面安装挡板) 29 粉体 1: 否 2: 是 料斗防漏 3: B 型 (A型+硅橡胶片) 4: 直角斗型+硅橡胶片 30 密封 1: 否 2: 是 (本体及集合斗) 机架 1: 碳钢喷漆 2: SUS304 31 供料斗 1: 单开门 2: 双开门 32 计量斗 2: 双开门 1: 单开门 1: 无 33 振动盘防漏 2: 有 1: 无 2: 计数功能 34 集合斗防漏 1: 无 2: A 型 3: B 型 4:粉体 3: 优先头功能 35 5XX用3L计量斗、供料斗弹簧 1: 无 2: 有 软件 4: 数据获取功能 36 振动盘带翘起 1: 无 2: 有 5: 其他 ( ) 51 手册名称 手册编号（备注） 1：英文使用说明书 GB48108A0086（RCU900） 备品备件 2：英文使用说明书 GB48108G0026（RCU-901C） 1 主振动密封圈 3：英文安装手册 GB46108G0001（RCU900） 个/台 默认备品备件 1 线振动密封圈 4：英文安装手册 GB46108G0007（RCU-901C） 个/台 0 5：英文安装手册 GB46108G0011（RCU-901C，UL） 套/台 0 套/台 可选备品备件 0 运转速度 套/台 54 目标重量范围 常规目标重量 0 g g 包/分钟 套/台 资料提供 1：技术图纸 1 份/台 2：英文使用说明书 1 份/台 3：英文安装手册 1 份/台 放入木箱 4：英文部品手册 1 份/台 5：英文参数设置表 份/台 6：CE认证证书 1 份/台 7：过程记录 1 份/台 8：英文维护手册 1 份/台 9：俄语说明书 份/台 提供资料 1：技术图纸 3 份/台 2：英文使用说明书 份/台 3：英文安装手册 份/台 寄日本大 4：英文部品手册 2 份/台 5：英文参数设置表 1 份/台 6：CE认证证书 份/台 和 7：过程记录 份/台 8：其他 1： 英语 2：日语 铭牌 5611105-000-97 铭牌 3：中文 4：西班牙语 认证贴纸 1：无 2：CE贴纸 3：UL贴纸 57 说明书语言 及 5: 俄语 6: 瑞典语 警示贴纸 1: 标准 2：日本 标志 7：其他（ ） 包装方式 1：出口包装 2：国内包装
HA7-5147R5254中文资料

HA7-5147R5254中文资料


θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . . 135
50
Maximum Junction Temperature (Hermetic Package). . . . . . . .175oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Features
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V/µs • Wide Gain Bandwidth (AV ≥ 10). . . . . . . . . . . . . . 120MHz • Low Noise . . . . . . . . . . . . . . . . . . . . . 3.2nV/√Hz at 1kHz • Low VOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30µV • High CMRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120dB • High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V/mV • Pb-Free Available (RoHS Compliant)