Zigbee协议的API接口函数手册

JennicTECHNOLOGY FOR A CHANGING WORLDIntegrated Peripherals APIReference ManualJN-RM-2001Revision 2.318-Jun-2007JennicImportant NoticeJennic reserves the right to make corrections, modifications, enhancements, improvements and other changes to its products and services at any time, and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders, and should verify that such information is current and complete. All products are sold subject to Jennic’s terms and conditions of sale, supplied at the time of order acknowledgment. Information relating to device applications, and the like, is intended as suggestion only and may be superseded by updates. It is the customer’s responsibility to ensure that their application meets their own specifications. Jennic makes no representation and gives no warranty relating to advice, support or customer product design.Jennic assumes no responsibility or liability for the use of any of its products, conveys no license or title under any patent, copyright or mask work rights to these products, and makes no representations or warranties that these products are free from patent, copyright or mask work infringement, unless otherwise specified.Jennic products are not intended for use in life support systems/appliances or any systems where product malfunction can reasonably be expected to result in personal injury, death, severe property damage or environmental damage. Jennic customers using or selling Jennic products for use in such applications do so at their own risk and agree to fully indemnify Jennic for any damages resulting from such use.All trademarks are the property of their respective owners.2 © Jennic 2007 JN-RM-2001 (v2.3) 18-Jun-2007JennicContentsImportant Notice 2 Contents 3 About this Manual 7 Organisation 7 Conventions 7 Definitions, Acronyms and Abbreviations 81 Introduction 9 1.1 Scope 9readership 91.2 Intended2 API Description 10 2.1 General 10 2.1.1 u32AHI_Init 10Handling 10 2.2 InterruptControl 13 2.3 System2.3.1 u8AHI_PowerStatus 13 2.3.2 vAHI_MemoryHold 14 2.3.3 vAHI_CpuDoze 14 2.3.4 vAHI_PowerDown 14 2.3.5 vAHI_Sleep (JN513x Only) 15 2.3.6 vAHI_ProtocolPower 15 2.3.7 vAppApiSetBoostMode (JN513x Only) 16 2.3.8 vAHI_HighPowerModuleEnable (JN513x Only) 16 2.3.9 vAHI_ExternalClockEnable (JN513x Only) 16 2.3.10 vAHI_AntennaDiversityOutputEnable (JN513x Only) 17 2.3.11 vAHI_SysCtrlRegisterCallback 17 2.3.12 vAHI_SwReset 17Timers 18 2.4 Wake2.4.1 vAHI_WakeTimerEnable 18 2.4.2 vAHI_WakeTimerStart 18 2.4.3 vAHI_WakeTimerStop 18 2.4.4 u8AHI_WakeTimerStatus 19 2.4.5 u32AHI_WakeTimerCalibrate 19 2.4.6 u8AHI_WakeTimerFiredStatus 19Peripherals 20 2.5 Analogue2.5.1 vAHI_ApConfigure 20 2.5.2 bAHI_APRegulatorEnabled 21 2.5.3 vAHI_APRegisterCallback 21 2.6 ADC 22 2.6.1 vAHI_AdcEnable 22 2.6.2 vAHI_AdcStartSample 22 2.6.3 bAHI_AdcPoll 23 2.6.4 u16AHI_AdcRead 23 2.6.5 vAHI_AdcDisable 23 2.7 DACs 24 2.7.1 vAHI_DacEnable 24 2.7.2 bAHI_DacPoll 24JN-RM-2001 (v2.3) 18-Jun-2007 © Jennic 2007 3Jennic2.7.3 vAHI_DacOutput 25 2.7.4 vAHI_DacDisable 25 2.8 Comparators 26 2.8.1 vAHI_CompEnable 26 2.8.2 vAHI_ComparatorEnable (JN513x Only) 27 2.8.3 vAHI_CompDisable 27 2.8.4 vAHI_CompIntEnable 28 2.8.5 vAHI_CompWakeEnable 28 2.8.6 u8AHI_CompStatus 28 2.8.7 u8AHI_CompWakeStatus 28 2.9 DIO 29 2.9.1 vAHI_DioSetDirection 29 2.9.2 vAHI_DioSetOutput 30 2.9.3 u32AHI_DioReadInput 30 2.9.4 u8AHI_DioSetByte 30 2.9.5 u8AHI_DioReadByte 31 2.9.6 vAHI_DioSetPullup 31 2.9.7 vAHI_DioInterruptEdge 31 2.9.8 vAHI_DioInterruptEnable 32 2.9.9 u32AHI_DioInterruptStatus 32 2.10 UARTs 33 2.10.1 vAHI_UartEnable 33 2.10.2 vAHI_UartDisable 34 2.10.3 vAHI_UartSetClockDivisor 34 2.10.4 vAHI_UartSetBaudDivisor 34 2.10.5 vAHI_UartSetControl 35 2.10.6 vAHI_UartSetInterrupt 36 2.10.7 vAHI_UartSetRTSCTS (JN513x Only) 36 2.10.8 vAHI_UartReset 37 2.10.9 u8AHI_UartReadLineStatus 37 2.10.10 u8AHI_UartReadModemStatus 38 2.10.11 u8AHI_UartReadInterruptStatus 38 2.10.12 vAHI_UartWriteData 38 2.10.13 u8AHI_UartReadData 39 2.10.14 vAHI_Uart0RegisterCallback 39 2.10.15 vAHI_Uart1RegisterCallback 39 2.11 Timers 40 2.11.1 vAHI_TimerEnable 40 2.11.2 vAHI_TimerClockSelect 41 2.11.3 vAHI_TimerStartSingleShot 41 2.11.4 vAHI_TimerStartRepeat 42 2.11.5 vAHI_TimerStartDeltaSigma 42 2.11.6 vAHI_TimerStartCapture 43 2.11.7 vAHI_TimerReadCapture 43 2.11.8 vAHI_TimerStop 43 2.11.9 vAHI_TimerDisable 44Only) 44(JN513x2.11.10 vAHI_TimerDIOControl2.11.11 u8AHI_TimerFired 44 2.11.12 vAHI_Timer0RegisterCallback 45 2.11.13 vAHI_Timer1RegisterCallback 45 2.12 Tick Timer 464 © Jennic 2007 JN-RM-2001 (v2.3) 18-Jun-2007Jennic 2.12.1 vAHI_TickTimerInit 46 2.12.2 vAHI_TickTimerWrite 46 2.12.3 vAHI_TickTimerIntPendClr 46 2.12.4 bAHI_TickTimerIntStatus 46 2.12.5 vAHI_TickTimerConfigure 47 2.12.6 vAHI_TickTimerIntEnable 47 2.12.7 u32AHI_TickTimerRead 47 2.12.8 vAHI_TickTimerInterval 47 2.13 Serial Peripheral Interface 48 2.13.1 vAHI_SpiConfigure 48 2.13.2 vAHI_SpiReadConfiguration 49 2.13.3 vAHI_SpiRestoreConfiguration 49 2.13.4 vAHI_SpiSelect 49 2.13.5 vAHI_SpiStop 50 2.13.6 vAHI_SpiStartTransfer32 50 2.13.7 u32AHI_SpiReadTransfer32 50 2.13.8 vAHI_SpiStartTransfer16 50 2.13.9 u16AHI_SpiReadTransfer16 51 2.13.10 vAHI_SpiStartTransfer8 51 2.13.11 u8AHI_SpiReadTransfer8 51 2.13.12 bAHI_SpiPollBusy 51 2.13.13 vAHI_SpiWaitBusy 52 2.13.14 vAHI_SpiRegisterCallback 52 2.14 Serial Interface (2 Wire) 53 2.14.1 vAHI_SiConfigure 53 2.14.2 vAHI_SiSetCmdReg 54 2.14.3 vAHI_SiWriteData8 54 2.14.4 vAHI_SiWriteSlaveAddr 55 2.14.5 u8AHI_SiReadData8 55 2.14.6 bAHI_SiPollBusy 55 2.14.7 bAHI_SiPollTransferInProgress 55 2.14.8 bAHI_SiPollRxNack 56 2.14.9 bAHI_SiPollArbitrationLost 56 2.14.10 vAHI_SiRegisterCallback 56 2.15 Intelligent Peripheral Mode 57 2.15.1 vAHI_IpEnable 57 2.15.2 bAHI_IpSendData 57 2.15.3 bAHI_IpReadData 58 2.15.4 bAHI_IpTxDone 58 2.15.5 bAHI_IpRxDataAvailable 58 2.15.6 vAHI_IpRegisterCallback 58 2.16 Flash 59 2.16.1 bAHI_FlashInit (JN513x Only) 59 2.16.2 bAHI_FlashErase 59 2.16.3 bAHI_FlashEraseSector (JN513x Only) 60 2.16.4 bAHI_FlashProgram 60 2.16.5 bAHI_FullFlashProgram (JN513x Only) 61 2.16.6 bAHI_FlashRead 61 2.16.7 bAHI_FullFlashRead (JN513x Only) 62 References 63 JN-RM-2001 (v2.3) 18-Jun-2007 © Jennic 2007 5Jennic6 © Jennic 2007 JN-RM-2001 (v2.3) 18-Jun-2007JennicAbout this ManualThis manual describes the software Application Programming Interface (API) to the peripheral devices on the JN5121 and JN513x single-chip IEEE 802.15.4 compliant wireless microcontrollers. This is known as the Integrated Peripherals API. It details the calls that may be made through the API in order to set up, control and respond to events generated by the peripheral blocks, such as UARTs, general-purpose IO lines and timers among others. Setting up and using power saving modes are also covered.The software invoked by this API is present in the on-chip ROM. This API does not include support for the IEEE 802.15.4 MAC hardware built into the device; this hardware is controlled using the MAC software stack that is built into the on-chip ROM. Readers are recommended to refer to [1] for further information on the use of this feature.Note 1: This manual was previously known as the Hardware Peripheral Library Reference Manual.Note 2: This manual covers both the JN5121 and JN513x versions of the Integrated Peripherals API. Some of the API functions described in this manual are for the JN513x only - these are clearly marked.OrganisationThis document consists of two chapters.• Chapter 1 gives a brief overview of the scope of the manual• Chapter 2 describes in detail the calls available to control each feature of the deviceConventionsCode fragments or function prototypes are represented by Courier typeface. When referringto constants or functions defined in the code they are emboldened, like so.JN-RM-2001 (v2.3) 18-Jun-2007 © Jennic 2007 7JennicDefinitions, Acronyms and AbbreviationsACL Access Control ListADC Analogue to Digital Converter AES Advanced Encryption Standard AHI Application Hardware Interface API Application Programming Interface CPU Central Processor Unit CTS Clear-To-Send DAC Digital to Analogue Converter DIO Digital Input OutputFIFO First-In, First-Out queue MAC Medium Access Control PAN Personal Area Network PIB PAN Information Base PWM Pulse Width Modulation RAM Random Access Memory RTS Ready-To-SendSPI Serial Peripheral InterfaceUARTUniversal Asynchronous Receiver Transmitter8 © Jennic 2007 JN-RM-2001 (v2.3) 18-Jun-2007Jennic 1 Introduction1.1 ScopeThis document describes the Application Programming Interface (API) for the JN5121/JN513x hardware peripherals – the Integrated Peripherals API. Its functionality is as follows: • System Controller• Wake timers• Analogue to digital converter (ADC)• Digital to analogue converters (DACs)• Comparators• Digital Input/Output (DIO)• Universal asynchronous receiver-transmitters (serial ports) (UARTs)• Timers• Serial Peripheral Interface (SPI)• Serial Interface (2 Wire)• Tick Timer• External FLASH memoryNote 1: This API was previously known as the Hardware Peripheral Library or the Hardware API.Note 2: This manual covers both the JN5121 and JN513x versions of the Integrated Peripherals API. Some of the API functions described in this manual are for the JN513x only - these are clearly marked.This API (sometimes referred to in this document as the AHI) provides a thin layer above the registers used to control the JN5121/JN513x peripherals, by encapsulating several register accesses into one function call and hence making it easier to use the peripherals without having to acquire detailed knowledge of their operation.This document does not describe the Baseband Controller, Modem or Radio, as these are driven by the 802.15.4 Stack API, which is always provided with the JN5121 and JN513x devices. The 802.15.4 Stack API is described in [1].This document does not describe the API for features found on evaluation kit boards such as sensors or display panels, although the buttons and LEDs on the evaluation kit boards are connected to the GPIO pins on the JN5121/JN513x chip. The API for evaluation kit board features is described in [2].1.2 Intended readershipIt is assumed that the reader has a reasonable knowledge of ‘C’ programming.JN-RM-2001 (v2.3) 18-Jun-2007 © Jennic 2007 9Jennic2 API DescriptionThe API is described in terms of the functions it provides, and these are grouped by peripheral.The functions are defined in AppHardwareApi.h.Note: There are small differences in the Integrated Peripherals API for the JN5121 and JN513x chips. Some API functions are for the JN513x only - these are clearly marked in the section headings.2.1 General2.1.1 u32AHI_InitDeclaration PUBLIC uint32 u32AHI_Init(void);Inputs NoneOutputs 0 if initialisation failed, otherwise a 32-bit version number (most significant 16 bits are main revision, least significant 16 bits are minor revision)Description Used to initialise the AHI. This should be called after every reset or wake-up and before any other AHI calls are made. Note that the application API should havebeen initialised before this function is called, and the call to initialise theapplication API includes a parameter to register a function to call whenever aninterrupt from the peripherals occurs, see following section for details.2.2 Interrupt HandlingInterrupts from peripheral devices are handled by a set of device-specific callbacks. These canbe set within the Integrated Peripherals API by using the appropriate callback registrationroutines. For example the user can write their own UART interrupt handler and then register this routine using the vAHI_Uart0RegisterCallback function. All device-specific callback functions registered must have the following prototype:PRIVATE void vHwDeviceIntCallback(uint32 u32DeviceId, uint32 u32ItemBitmap)The device ID, u32DeviceId, is an enumerated value indicating the peripheral that generatedthe interrupt, as follows:Enumeration Interrupt Source Callback registration functionE_AHI_DEVICE_TICK_TIMER Tick Timer vAHI_TickTimerInitcontroller vAHI_SysCtrlRegisterCallback E_AHI_DEVICE_SYSCTRL SystemE_AHI_DEVICE_AES Encryption engine See JN-RM-2013-AES-Coprocessor-APIE_AHI_DEVICE_UART0 UART 0 vAHI_Uart0RegisterCallbackE_AHI_DEVICE_UART1 UART 1 vAHI_Uart1RegisterCallbackE_AHI_DEVICE_TIMER0 Timer 0 vAHI_Timer0RegisterCallbackE_AHI_DEVICE_TIMER1 Timer 1 vAHI_Timer1RegisterCallbackmaster vAHI_SpiRegisterCallback E_AHI_DEVICE_SPIM SPI10 © Jennic 2007 JN-RM-2001 (v2.3) 18-Jun-2007E_AHI_DEVICE_SI Serial Interface (2 wire) vAHI_SiRegisterCallbackvAHI_IpRegisterCallbackperipheralE_AHI_DEVICE_INTPER Intelligentperipherals vAHI_APRegisterCallbackE_AHI_DEVICE_ANALOGUE AnalogueThe item u32ItemBitmap is an enumerated value indicating the individual interrupt sourcewithin the peripheral, as described in the tables below.Before calling the callback function, the library clears the source of the interrupt, so there is no danger of the same interrupt causing the processor to enter a state of permanently trying to handle the same interrupt due to a malformed callback function. This also means that it is possible to have a NULL callback function.The UARTs are the exception to this rule; when generating a ‘receive data available’ or ‘timeout indication’ interrupt, the UARTs will only clear the interrupt when the data is read from the UART receive buffer. It is therefore vital that if UART interrupts are to be enabled, the callback function handles the ‘receive data available’ and ‘timeout indication’ interrupts by reading the data from the UART before returning.Note that if the Application Queue API is being used, the issue with UART interrupts is handled by the API, so the application does not have to cope with it. See [3] for more information about the Application Queue API.The enumerated values are defined as follows:TickTimerMask (Bit) Description0 Single source for Tick Timer interrupt, therefore returns 1 every time System ControllerMask (Bit) DescriptionE_AHI_SYSCTRL_COMP_MASK (29) Comparator eventsWake Timer eventsE_AHI_SYSCTRL_WK1_MASK (27)E_AHI_SYSCTRL_WK0_MASK (26)Digital IO eventsE_AHI_DIO20_INT (20)E_AHI_DIO19_INT (19)E_AHI_DIO18_INT (18)..E_AHI_DIO0_INT (0)UART (Identical for both UARTs)Enumerated Value DescriptionE_AHI_UART_TIMEOUT_MASK (6) Timeout indicationE_AHI_UART_RXLINE_MASK (3) Receive line statusE_AHI_UART_RXDATA_MASK (2) Receive data availableE_AHI_UART_TX_MASK (1) Transmit FIFO emptyE_AHI_UART_MODEM_MASK (0) Modem statusTimers (Identical for both timers)Mask (Bit) DescriptionE_AHI_TIMER_RISE_MASK (1) Interrupt status, generated on timer rising edge, end of low period - will benon-zero if interrupt for timer output going high has been setE_AHI_TIMER_PERIOD_MASK (0) Interrupt status, generated on timer falling edge, end of period - will benon-zero if interrupt for timer period complete has been setSerial Interface (2-wire)Mask (Bit) DescriptionE_AHI_SI_RXACK_MASK (7) Asserted if no acknowledge is received from the addressed slaveE_AHI_SI_BUSY_MASK (6) Asserted if a START signal is detectedCleared if a STOP signal is detectedE_AHI_SI_AL_MASK (5) Asserted to indicate loss of arbitrationE_AHI_SI_ACK_CTRL_MASK (2) Acknowledge control:0 indicates sent ACK1 indicates sent NACKE_AHI_SI_TIP_MASK (1) Asserted to indicate transfer in progressE_AHI_SI_INT_STATUS_MASK (0) Interrupt status; interrupt indicates loss of arbitration or that byte transferhas completedSPI MasterMask (Bit) DescriptionE_AHI_SPIM_TX_MASK (1) Asserted to indicate transfer has completedIntelligent PeripheralMask (Bit) DescriptionE_AHI_IP_INT_STATUS_MASK (6) Asserted to indicate transaction has completed, i.e slave select goes highand TXGO or RXGO has gone lowE_AHI_IP_TXGO_MASK (1) Asserted when TX data is copied to the internal buffer and cleared when ithas been sent out.E_AHI_IP_RXGO_MASK (0) Asserted when device is ready to receive state and cleared when data RXis complete.Analogue PeripheralsMask (Bit) DescriptionE_AHI_AP_INT_STATUS_MASK (0) Asserted to indicate capture complete or new sample ready2.3 System ControlThe system controller provides control for the CPU and memory power and sleep operation. There are two significant blocks in the system controller. The 32kHz domain runs from a simple oscillator and is designed for very low power sleep states. Whilst sleeping, the CPU does not run and relies on an interrupt to wake it up. The interrupt can be generated externally or from within the 32kHz domain. Later sections describe the ways in which interrupts can be generated within the chip, using the wake timers to generate events within the 32kHz domain or the DIO pins for external stimuli.The 16MHz domain is used to run the CPU and several peripherals (security engine, ADC,timing accuracy.device powers up. The RAM is powered by its own regulator, separate from the regulator for the CPU. This allows the RAM to remain powered when the CPU is asleep and powered down. This is useful for short sleep periods, when the time taken to re-load the RAM from flash is significant when compared to the sleep time. Alternatively, for longer sleep periods, the memory power may be removed as well, reducing the sleep current consumption.In addition, there are two other power domains, one for analogue peripherals and the other (the protocol domain) for the modem, encryption coprocessor, radio and baseband controller. The analogue power domain is switched on if the analogue peripherals are in use.As well as the normal sleep mode, it is possible to enter a deep sleep. In this state both the16MHz and 32kHz clock domains are turned off and the device can only be woken by the device reset line being pulled low.A final low power mode is doze mode, in which the CPU remains powered but the 16MHz clock to it is stopped. This uses more power than sleep mode but requires less time to restart. The CPU is brought out of doze mode by an interrupt (note that a tick timer interrupt cannot be used to bring the CPU out of doze mode).2.3.1 u8AHI_PowerStatusDeclaration PUBLIC uint8 u8AHI_PowerStatus(void);Inputs NoneOutputs uint8 containing power domain control settingsbit 0: 1 if chip has completed a sleep-wake up cyclebit 1: If 1 after wake up, memory contents were retained during sleepbit 2: 1 if analogue power domain is switched onbit 3: 1 if protocol power domain is switched onDescription Returns the power domain settings for the JN5121/JN513x, as described above.2.3.2 vAHI_MemoryHoldDeclaration PUBLIC void vAHI_MemoryHold(bool_t bHoldDuringSleep);Inputs bool_tbHoldDuringSleep TRUE to power memory during sleepFALSE to remove power from memory during sleepOutputs NoneDescription Determines whether the memory will remain powered during the next sleep period.2.3.3 vAHI_CpuDozeDeclaration PUBLIC void vAHI_CpuDoze(void);Inputs NoneOutputs NoneDescription Causes the CPU to stop operating until an interrupt occurs. The CPU clock will be disabled during sleep to minimise power consumption, although other modules willstill be operational. The function returns when the CPU re-starts.2.3.4 vAHI_PowerDownDeclaration PUBLIC void vAHI_PowerDown(bool_t bDeepNotNormalSleep);Inputs bool_tbDeepNotNormalSleep TRUE for the sleep to be deep sleep (device only awakes through a reset)FALSE for normal sleep (device wakes after interrupt or reset)Outputs NoneDescription Sends the device to sleep. In normal sleep mode, all parts of the device are inactive or powered down apart from the 32 kHz oscillator and those parts of thesystem controller used for wake up. In deep sleep, even these are powereddown. This function does not return. When the device restarts, it will beginprocessing at the reset vector.2.3.5 vAHI_Sleep (JN513x Only)Declaration PUBLIC void vAHI_Sleep(teAHI_SleepMode sSleepMode);Inputs teAHI_SleepModesSleepMode One of:E_AHI_SLEEP_OSCON_RAMON 32 kHz oscillator on and RAM onE_AHI_SLEEP_OSCON_RAMOFF 32 kHz oscillator on and RAM offE_AHI_SLEEP_OSCOFF_RAMON 32 kHz oscillator off and RAM onE_AHI_SLEEP_OSCOFF_RAMOFF 32 kHz oscillator off and RAM offE_AHI_SLEEP_DEEPDeep sleep (all components off)Outputs NoneDescription Sends the JN513x chip to sleep, allowing the 32 kHz oscillator and the RAM to be individually left on or switched off, as required. When in normal sleep mode, thedevice wakes after an interrupt or a reset. When in deep sleep mode, the devicewakes only after a reset. When the JN513x restarts, it will begin processing at thecold start or warm start entry point. This function does not return.2.3.6 vAHI_ProtocolPowerDeclaration PUBLIC void vAHI_ProtocolPower(bool_t bOnNotOff);Inputs bool_t bOnNotOff TRUE to turn the protocol power domain on.FALSE to turn the protocol power domain off. Outputs NoneDescription Controls the regulator that supplies the protocol domain (the radio, modem baseband and encryption coprocessor). If you intend to turn the protocol power offand then back on again without performing a reset, you must store the currentMAC settings before turning the protocol power off. You can save the MACsettings using the function vAppApiSaveMacSettings(). Turning the protocol powerback on can then be achieved simply by restoring the MAC settings using thefunction vAppApiRestoreMacSettings(). These functions are described in [1].While the protocol is powered down, you must not make any calls into the stack asthis may result in the stack trying to access the hardware (which is turned off) andtherefore a crash.2.3.7 vAppApiSetBoostMode (JN513x Only)Declaration PUBLIC void vAppApiSetBoostMode(bool_t bOnNotOff);Inputs bool_t bOnNotOff TRUE to enable boost mode.FALSE to disable boost mode (default setting). Outputs NoneDescription Enables or disables boost mode on a JN513x device – this increases the transmission power by approximately 3 dB (beware that this results in increasedcurrent consumption). A new setting only takes effect when the device isinitialised, so this function call must be followed by a call to either u32AppApiInit()or u32AppQApiInit(). The setting is maintained throughout sleep mode if memoryis held up, but is lost if memory is turned off.2.3.8 vAHI_HighPowerModuleEnable (JN513x Only)Declaration PUBLIC void vAHI_HighPowerModuleEnable(bool_t bRFTXEn,bool_t bRFRXEn);bool_t bRFTXEn TRUE to enable high power module transmitter InputsFALSE to disable high power module transmitter bool_t bRFRXEn TRUE to enable high power module receiverFALSE to disable high power module receiver Outputs NoneDescription Allows the transmitter and receiver sections of a High-Power Module (HPM) to be individually enabled or disabled. Must be called before using radio on an HPM.2.3.9 vAHI_ExternalClockEnable (JN513x Only)Declaration PUBLIC void vAHI_HighPowerModuleEnable(bool_t bExClockEn);Inputs bool_t bExClockEn TRUE to enable external clock inputFALSE to disable external clock inputOutputs NoneDescription Enables the use of an external source for the 32 kHz clock.2.3.10 vAHI_AntennaDiversityOutputEnable (JN513x Only)Declaration PUBLIC void vAHI_AntennaDiversityOutputEnable(bool_t bOddRetryOutEn,bool_t bEvenRetryOutEn);bool_t bOddRetryOutEn TRUE to enable output on DIO12FALSE to disable output on DIO12Inputsbool_t bEvenRetryOutEn TRUE to enable output on DIO13FALSE to disable output on DIO13Outputs NoneDescription Supports the provision of an alternative antenna in case of a transmission failure.DIO12 and DIO13 are each associated with an antenna, and are used to indicatewhether a transmission retry on the corresponding antenna is required. When bothDIOs are enabled for this feature, DIO13 goes high for the first transmission. If noacknowledgement is received, the need for a first retry of the transmission isindicated by DIO12 going high (DIO13 goes low). If required, a second retry isindicated by DIO13 going high (DIO12 goes low). Subsequently, all odd numberedretries are requested using DIO12 and all even numbered retries are requestedusing DIO13. The application must choose the antenna for each retry accordingly.2.3.11 vAHI_SysCtrlRegisterCallbackDeclaration PUBLIC void vAHI_SysCtrlRegisterCallback(PR_HWINT_APPCALLBACK prSysCtrlCallback);Inputs PR_HWINT_APPCALLBACKprSysCtrlCallback Pointer to function that is to be called when a system control interrupt occurs.Outputs NoneDescription Registers an application callback that will be called when the system control interrupt (caused by wake timer, comparator and DIO events) is triggered.2.3.12 vAHI_SwResetDeclaration PUBLIC void vAHI_SwReset (void);Inputs NoneOutputs NoneDescription Generates an internal reset when called, which completely re-starts the system.2.4 Wake TimersThe wake timers are normally used to time sleep periods and can be programmed to generate interrupts when the timeout period has completed. However, they can also be used whilst the CPU is running. There is another set of timers with more functionality that can operate only whilst the CPU is running; see Section 2.11.The wake timers run at a nominal 32kHz but to minimise complexity and hence power consumption, they may run at up to 30% fast or slow depending on temperature, supply voltage and manufacturing tolerance. A self-calibration facility is provided to time the 32kHz clock against the 16MHz clock if accurate timing is required.2.4.1 vAHI_WakeTimerEnableDeclaration PUBLIC void vAHI_WakeTimerEnable(uint8 u8Timer,bool_t bIntEnable);uint8 u8Timer Timer identity:E_AHI_WAKE_TIMER_0 orE_AHI_WAKE_TIMER_1Inputsbool_t bIntEnable TRUE to enable interrupt when timer fires FALSE to disable interruptOutputs NoneDescription Prepares a wake timer for use, enabling the associated interrupt if desired.2.4.2 vAHI_WakeTimerStartDeclaration PUBLIC void vAHI_WakeTimerStart(uint8 u8Timer, uint32 u32Count);uint8 u8Timer Timer identity:E_AHI_WAKE_TIMER_0 orE_AHI_WAKE_TIMER_1Inputsuint32 u32Count Count time in 32kHz periods, i.e. 32 is 1 millisecond Outputs NoneDescription Starts a wake timer to time for the specified interval.2.4.3 vAHI_WakeTimerStopDeclaration PUBLIC void vAHI_WakeTimerStop(uint8 u8Timer);Inputs uint8 u8Timer Timer identity:E_AHI_WAKE_TIMER_0 orE_AHI_WAKE_TIMER_1Outputs NoneDescription Stops a wake timer. No interrupt will be generated.2.4.4 u8AHI_WakeTimerStatusDeclaration PUBLIC uint8 u8AHI_WakeTimerStatus(void);Inputs NoneOutputs uint8 Bitmap:Returned value logical ANDed with E_AHI_WAKE_TIMER_MASK_0 will benon-zero if wake timer 0 is runningReturned value logical ANDed with E_AHI_WAKE_TIMER_MASK_1 will benon-zero if wake timer 1 is runningDescription Returns a bitmap where the relevant bits are set to show which timers are active.It is possible to have more than one timer active at once. Note that a timer remainsactive after the timed interval has completed.2.4.5 u32AHI_WakeTimerCalibrateDeclaration PUBLIC uint32 u32AHI_WakeTimerCalibrate(void);Inputs NoneOutputs uint32 Returned value shows the calibration offset from the ideal, measuredagainst the 16MHz clock. The ideal result would be 10000 decimal. Alower value means that the 32kHz clock is running fast and a highervalue means it is running slow.Description Performs a calibration of the 32kHz clock against the more accurate 16MHz clock.The returned value can be used to adjust the time interval values used to programthe wake timers.Note that the 32kHz clock has a tolerance of +/-30%.2.4.6 u8AHI_WakeTimerFiredStatusDeclaration PUBLIC uint8 u8AHI_WakeTimerFiredStatus(void);Inputs NoneOutputs uint8 Bitmap:Returned value logical ANDed with E_AHI_WAKE_TIMER_MASK_0 will benon-zero if wake timer 0 has firedReturned value logical ANDed with E_AHI_WAKE_TIMER_MASK_1 will benon-zero if wake timer 1 has firedDescription Returns a bitmap where the relevant bits are set to show which timers have fired.Any fired timer status is cleared as a result of this call.。