AD402M166RBB-5中文资料

ASCEND Semiconductor 4Mx4 EDO Data sheetDescriptionThe device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).Features• Single 3.3V(%) only power supply • High speed t RAC acess time: 50/60ns • Low power dissipation- Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas)• Extended - data - out(EDO) page mode access • I/O level: CMOS level (Vcc = 3.3V)• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)• 4 refresh modesh: - RAS only refresh- CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version)10±Pin Name FunctionA0-A10Address inputs- Row address - Column address - Refresh address DQ1~DQ4Data-in / data-out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+ 3.3V)VssGroundVCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7A6A5A4VSSAD404M42VSPin Description Pin Configuration21222324 2526151416 A1026/24-PIN 300mil Plastic SOJA9VCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7 A6A5 A4VSSAD404M42VT212223242526151416 A1026/24-PIN 300mil Plastic TSOP (ll)A9A0-A10A0-A10A0-A10WECASNO. 2 CLOCK GENERATORCOLUMN ADDRESS BUFFERS (11)REFRESH CONTROLLERREFRESH COUNTERBUFFERS (11)ADDRESS ROW NO. 1 CLOCK GENERATORA0RASA1A2A3A4A5A6A7A8CONTROLLOGICDATA-IN BUFFERDATA-OUT BUFFEROEDQ1.DQ4.COLUMN DECODER2048SENSE AMPLIFIERSI/O GATING2048x42048x2048x4MEMORY ARRAY2048R O W D E C O D E RVcc VssBlock DiagramA9A10TRUTH TABLENotes: 1. EARLY WRITE only.FUNCTIONRASCAS WE OE ADDRESSESDQ SNotesROW COL STANDBY H X X X X High-Z READL L H L ROW COL Data-Out WRITE: (EARLY WRITE )L L L X ROW COL Data-lnREAD WRITE L L ROW COL Data-Out,Data-ln EDO-PAGE-MODE READ1st Cycle L H L ROW COL Data-Out 2nd CycleL H L n/a COL Data-Out EDO-PAGE MODE WRITE1st CycleL L X ROW COL Data-In 2nd Cycle L L Xn/a COL Data-InEDO-PAGE-MODEREAD-WRITE 1st Cycle L ROW COL Data-Out, Data-In 2nd Cycle L n/a COL Data-Out, Data-In HIDDEN REFRESHREAD L H L ROW COL Data-Out WRITEL L X ROW COL Data-In 1RAS-ONLY REFRESH L H X X ROW n/a High-Z CBR REFRESHLHXXXHigh-ZH X →H L →L H →H L →H L →H L →H L →H L →H L →L H →H L →H L →L H→L H L →→L H L→→H L→Absolute Maximum RatingsRecommended DC Operating ConditionsCapacitanceTa = 25°C, V CC = 3.3V%, f = 1MHz Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout.ParameterSymbol Value Unit Voltage on any pin relative to Vss V T -0.5 to + 4.6V Supply voltage relative to Vss V CC -0.5 to + 4.6V Short circuit output current I OUT 50mA Power dissipation P D 1.0WOperating temperature T OPT 0 to + 70°C Storage temperatureT STG-55 to + 125°CParameter/Condition Symbol3.3 Volt VersionUnitMinTyp MaxSupply VoltageV CC 3.0 3.33.6V Input High Voltage, all inputs V IH 2.0-V CC + 0.3V Input Low Voltage, all inputsV IL-0.3-0.8VParameterSymbol Typ Max Unit Note Input capacitance (Address)C I1 -5pF 1Input capacitance (RAS, CAS, OE, WE)C I2-7pF 1Output capacitance(Data-in, Data-out)C I/O-7pF1, 210±DC Characteristics :(T a = 0 to 70°C, V CC = + 3.3V%, V SS = 0V)Parameter Symbol Test Conditions AD404M42V Unit Notes-5-6Min Max Min MaxOperating current I CC1RAS cyclingCAS, cyclingt RC = min-120-110mA1, 2Standby Current LowpowerS-versionI CC2LVTTL interfaceRAS, CAS = V IHDout = High-Z-0.5-0.5mACMOS interfaceRAS, -0.2VDout = High-Z-0.15-0.15mAStandardpowerversionLVTTL interfaceRAS, CAS = V IHDout = High-Z-2-2mACMOS interfaceRAS,-0.2VDout = High-Z-0.5-0.5mARAS- only refresh current I CC3RAS cycling, CAS = V IHt RC = min-120-110mA1, 2 EDO page mode current I CC4t PC = min-90-80mA1, 3CAS- before- RAS refresh current I CC5t RC = minRAS, CAS cycling-120-110mA1, 2Self- refresh current (S-Version)I CC8 - 550 - 55010±CAS V CC≥CAS V CC≥t RASS100µs≥µADC Characteristics :(T a = 0 to 70°C , V CC = +3.3V %, V SS = 0V)Notes:1. I CC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. I CC max is specified at the output open condition.2. Address can be changed once or less while RAS = V IL .3. For I CC4, address can be changed once or less within one EDO page mode cycle time.Parameter Symbol Test Conditions AD404M42VUnitNotes-5-6Min MaxMin MaxInput leakage current I LI + 0.3V -55-55Output leakage current I LO + 0.3V Dout = Disable -55-55Output high Voltage V OH I OH = -2mA 2.4- 2.4-V Output low voltage V OLI OL = +2mA-0.4-0.4V10±0V Vin V CC ≤≤µA 0V Vout V CC ≤≤µAAC Characteristics(T a = 0 to + 70°C , V cc = 3.3V %, V ss = 0V) *1, *2, *3, *4Test conditions• Output load: one TTL Load and 100pF (V CC = 3.3V %)• Input timing reference levels:V IH = 2.0V, V IL = 0.8V (V CC = 3.3V %)• Output timing reference levels:V OH = 2.0V, V OL = 0.8V10±10±10±Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters)ParameterSymbol AD404M42V UnitNotes-5-6Min MaxMin MaxRandom read or write cycle time t RC 84-104-ns RAS precharge timet RP 30-40-ns CAS precharge time in normal mode t CPN 10-10-ns RAS pulse width t RAS 50100006010000ns 5CAS pulse width t CAS 8100001010000ns 6Row address setup time t ASR 0-0-ns Row address hold time t RAH 8-10-ns Column address setup time t ASC 0-0-ns 7Column address hold time t CAH 8-10-ns RAS to CAS delay timet RCD 12371445ns 8RAS to column address delay time t RAD 10251230ns 9Column address to RAS lead time t RAL 25-30-ns RAS hold time t RSH 8-10-ns CAS hold timet CSH 38-40-ns CAS to RAS precharge time t CRP 5-5-ns 10OE to Din delay time t OED 12-15-ns Transition time (rise and fall)t T 150150ns 11Refresh periodt REF -32-32ms Refresh period (S- Version)t REF -128-128ms CAS to output in Low- Z t CLZ 0-0-ns CAS delay time from Din t DZC 0-0-ns OE delay time from Dint DZO-0-nsRead CycleWrite Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxAccess time from RAS t RAC-50-60ns12 Access time from CAS t CAC-14-15ns13, 14 Access time from column address t AA-25-30ns14, 15 Access time from OE t OEA-12-15nsRead command setup time t RCS0-0-ns7 Read command hold time to CAS t RCH0-0-ns10, 16 Read command hold time to RAS t RRH0-0-ns16 Output buffer turn-off time t OFF012015ns17 Output buffer turn-off time from OE t OEZ012015ns17Parameter SymbolAD404M42V Unit Notes -5-6Min Max Min MaxWrite command setup time t WCS0-0-ns7, 18 Write command hold time t WCH8-10-nsWrite command pulse width t WP8-10-nsWrite command to RAS lead time t RWL13-15-nsWrite command to CAS lead time t CWL8-10-nsData-in setup time t DS0-0-ns19 Data-in hold time t DH8-10-ns19 WE to Data-in delay t WED10-10-nsRead- Modify- Write CycleRefresh Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxRead-modify- write cycle time t RWC108-133-nsRAS to WE delay time t RWD64-77-ns18 CAS to WE dealy time t CWD26-32-ns18 Column address to WE delay time t AWD39-47-ns18 OE hold time from WE t OEH8-10-nsParameter SymbolAD404M42VUnit Notes -5-6Min Max Min MaxCAS setup time (CBR refresh) t CSR5-5-nsCAS hold time (CBR refresh)t CHR8-10-ns10 RAS precharge to CAS hold time t RPC5-5-ns7 RAS pulse width (self refresh)t RASS100-100-RAS precharge time (self refresh)t RPS90-110-nsCAS hold time (CBR self refresh)t CHS-50--50-nsWE setup time t WSR0-0-nsWE hold time t WHR10-10-nsµsEDO Page Mode CycleEDO Page Mode Read Modify Write CycleParameterSymbol AD404M42VUnit Notes-5-6Min MaxMin MaxEDO page mode cycle timet PC 20-25-ns EDO page mode CAS precharge time t CP 10-10-ns EDO page mode RAS pulse width t RASP 5010560105ns 20Access time from CAS precharge t CPA -30-35ns 10, 14RAS hold time from CAS precharge t CPRH 30-35-ns OE high hold time from CAS high t OEHC 5-5-ns OE high pulse widtht OEP 10-10-ns Data output hold time after CAS low t COH 5-5-ns Output disable delay from WEt WHZ 310310ns WE pulse width for output disable whenCAS hight WPZ7-7-nsParameterSymbol AD404M42V Unit Notes -5-6Min MaxMin MaxEDO page mode read- modify- write cycle CAS precharge to WE delay timet CPW 45-55-ns 10EDO page mode read- modify- write cycle timet PRWC56-68-nsNotes :1. AC measurements assume t T = 2ns.2. An initial pause of 100 is required after power up, and it followed by a minimum of eightinitialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.4. All the V CC and V SS pins shall be supplied with the same voltages.5. t RAS (min) = t RWD (min)+t RWL (min)+t T in read-modify-write cycle.6. t CAS (min) = t CWD (min)+t CWL (min)+t T in read-modify-write cycle.7. t ASC (min), t RCS (min), t WCS (min), and t RPC are determined by the falling edge of CAS .8. t RCD (max) is specified as a reference point only, and t RAC (max) can be met with the t RCD (max) limit.Otherwise, t RAC is controlled exclusively by t CAC if t RCD is greater than the specified t RCD (max) limit. 9. t RAD (max) is specified as a reference point only, and t RAC (max) can be met with the t RAD (max) limit.Otherwise, t RAC is controlled exclusively by t AA if t RAD is greater than the specified t RAD (max) limit. 10. t CRP , t CHR , t RCH , t CPA and t CPW are determined by the rising edge of CAS .11. V IH (min) and V IL (max) are reference levels for measuring timing or input signals. Therefore, transitiontime is measured between V IH and V IL .12. Assumes that t RCD tRCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 13. Assumes that (max) and (max).14. Access time is determined by the maximum of t AA , t CAC , t CPA . 15. Assumes that (max) and (max). 16. Either t RCH or t RRH must be satisfied for a read cycle.17. t OFF (max) and t OEZ (max) define the time at which the output achieves the open circuit condition (highimpedance). t OFF is determined by the later rising edge of RAS or CAS.18. t WCS , t RWD , t CWD , and t AWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If (min),(min), (min) and (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate.19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in adelayed write or a read-modify-write cycle.20. t RASP defines RAS pulse width in EDO page mode cycles.µs ≤≤t RCD t RCD ≥t RADt RAD ≤t RCD t RCD ≤t RAD t RAD ≥t WCS t WCS ≥t RWD t RWD ≥t CWDt CWD ≥t AWD t AWD ≥t CPW t CPW≥Timing Waveforms• Read Cyclet RC t RASt RPtCRPtCPNtRRHtRCHt OEZ t OFF tOEA tCACt AAtRACt CLZD OUTtRCS t ASR tRAH tASC tCAH tRAD t RALtCAStRSH tRCDt TtCSHRASCASADDRESSWEDQ1~DQ4Note : = don’t care OEt OFFRowColumn= Invalid Dout•Early Write CycletRC t RASt RPt WCHt DSt DHt WCS t RALtCAStRSH tRCDt TtCSHRASCASWEDQ1~DQ4tCRPtASRtRAH tASCtCAH ADDRESSColumnRowtCPND INtRADt RAL• Delayed Write CycletRC t RASt RPt RWL t RCSt CAStRSH tRCDt TtCSHRASCAStASR tRAH tCAHADDRESSColumnRow tASC D INDQ1~DQ4WEtCRPtCPNt DHt DSt OEHt OEDOEt DSOPENt WPt CWL• Read - Modify - Write CycletRWC t RASt RPtRWDt WPtRADtRWL tCAStCWL tRCDt TtCPNRASCASWEtCRP t ASRtRAHtASCtCAHADDRESS Column RowDQ1~DQ4t DHt DSOEtRCStAWD tCWD D INt OEDt OEHt OEZt OEA t CAC t RACt AADQ1~DQ4D OUTOPENtDZCtDZO• EDO Page Mode Read CycletRASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtOEPD OUT 1t PCt CPtCAStCPNtCRPtRADtCAHtASCt ASCtCAHt ASCt RAL Row Column 1t OEAt OEHCtRRH tRCHt RACt AAt AAt AA t CPA t CPA t OEZt OFFt OFFt CACt OEZt CAC t CACt COHD OUT NWE OE Column 2Column N Rowt RPD OUT 2• EDO Page Mode Early Write CycletRASPtRPt WCSt CAStRSH tRCDRASCAStASRtRAHtCAHADDRESStCASWEt CPDQ1~DQ4t PCt CPt CAStCPNtCRP tCAH tASCtASC tCAH tASC Row Column 1t DS WE Column 2Column Nt WCH t WCS t WCH t WCS t WCHt DH t DS t DH t DS t DHD IN 1D IN 2D IN Nt TtCSH• EDO Page Mode Read-Early-Write Cyclet RASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtWEDt PCt CPtCAStCPNtCRPtRADtRAHtASCt ASCtCAHt ASCt RAL Row Column 1tWCStRCHt RACt AAt AAt CPA t DHt WHZt CACt CACt COHWE OE Column 2Column N Rowt RPt CAL tWCHDataDoutput 2Data Input NDataDoutput 1t DStCSH• EDO Page Mode Read-Modify-Write Cyclet RASPt CPRHt RCStCASt WP RASCASt ASRtRAHtCAHADDRESSt CASWEtRCDCPDQ1~DQ4tPRWCt CPtCAStCRPtRADtCAHtASCt ASCtCAH tASC Row Column 1tRWLtRCSt OEDt DZOt CAC WE OEt RPt RAL D OUT 2D OUT ND OUT 1tTt Column NColumn 2Column 1tRWD tAWD tCWDtCWLtRCStCWDtAWD tCPW tCWL tCPW tAWD tCWDtCWL t OEDt OEDt OEHt OEHt OEHt CAC t CAC t OEA t AAt RACt OEZt OEAt AA t CPAt OEZt OEAt AA t CPAt OEZ t DSt DHt WP t DSt DHt WP t DSt DHOPENOPENOPEN D IN 1D IN ND IN 2DQ1~DQ4t DZCt DZOt DZCt DZCt DZO• Read Cycle with WE Controlled Disablet WPZt RCStCAStRCDt TtCSHRASCASt ASRtRAHtCAHADDRESSColumnRow tASCD DQ1~DQ4WEt OEZt DSt WHZOEt RCH t OEA t CACt AAt RACt CLZOUTtRADRASADDRESSt RC t CRPt ASRt RAHt Tt RPCROWt OFFCAS t RASt RPOPENt CRPDQ1~DQ4RASt CSRt WSRt RPt T t RPCt OFFCAS t RASt RPOPENt CRPDQ1~DQ4t RPCt CHRt RASt RPt RCt RCt CHRt CSRt WHRt WSRt WHRWECAS-Before-RAS Refresh CycleRASWEt RPCt OFFt CSRt CHSt WSRCASt RASS t RPSOPENDQ1~DQ4t WHRHigh lmpedance• Hidden Refresh Cyclet RPt RASRASt RCDt CRPADDRESSWEt CHRt CASt RSHt RAHt ASRt ASCt CAHt RAL ROW t RCHt OEZCASDQ1~DQ4t Tt RCSD t RASt RASt RPt RPt RC t RCt RCt RADt RRHt OFF t OFFt OEA t CACt AAt RACCOlumnOUTOE(READ)(REFRESH)(REFRESH)Ordering informationAD404M42VSA-5• AD• Ascend Memory Product • 40 • Device Type• 4M4 • Density and Organization • 2• Refresh Rate, 2: 2K Refresh • V• T: 5V, V: 3.3V• S • Package Type (S : SOJ, T : TSOP II)• A• Version• 5• Speed (5: 50 ns, 6: 60 ns)Part Number Access time PackageAD404M42VSA-5AD404M42VSA-6AD404M42VTA-5AD404M42VTA-650 ns 60 ns 50 ns 60 ns300mil 26/24-Pin Plastic SOJTSOP IIPackaging information • 300 mil, 26/24-Pin Plastic SOJ• 300 mil, 26/24-Pin TSOP II。

Single Channel, 16-Bit, Serial Input,Current Source & Voltage Output DAC Preliminary Technical Data AD5422Rev. PrEInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.FEATURES16-Bit Resolution and MonotonicityCurrent Output Ranges: 4–20mA, 0–20mA or 0–24mA 0.1% typ Total Unadjusted Error (TUE)5ppm/°C Output DriftVoltage Output Ranges: 0-5V, 0-10V, ±5V, ±10V,10% over-range0.05% Total Unadjusted Error (TUE)3ppm/°C Output DriftFlexible Serial Digital InterfaceOn-Chip Output Fault DetectionOn-Chip Reference (10 ppm/°C Max)Asynchronous CLEAR FunctionPower Supply RangeAV DD : 10.8V to 40 VAV SS : -26.4V to -3V/0VOutput Loop Compliance to AV DD – 2.5 V Temperature Range: -40°C to +85°CTSSOP and LFCSP PackagesAPPLICATIONSProcess ControlActuator ControlPLC GENERAL DESCRIPTIONThe AD5422 is a low-cost, precision, fully integrated 16-bit converter offering a programmable current source and programmable voltage output designed to meet the requirements of industrial process control applications.The output current range is programmable to 4mA to 20 mA,0mA to 20mA or an overrange function of 0mA to 24mA. Voltage output is provided from a separate pin that can be configured to provide 0V to 5V, 0V to 10V, ±5V or ±10V output ranges, an over-range of 10% is available on all ranges. Analog outputs are short and open circuit protected and can drive capacitive loads of 1uF and inductive loads of 1H.The device is specified to operate with a power supply range from 10.8 V to 40 V. Output loop compliance is 0 V to AV DD – 2.5 V.The flexible serial interface is SPI and MICROWIRE compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications.The device also includes a power-on-reset function ensuring that the device powers up in a known state and an asynchronous CLEAR pin which sets the outputs to zero-scale / mid-scale voltage output or the low end of the selected current range.The total output error is typically ±0.1% in current mode and ±0.05% in voltage mode.Table 1. Related DevicesPart Number DescriptionAD5412 Single Channel, 12-Bit, SerialInput Current Source andVoltage Output DACAD5420 Single Channel, 16-Bit, SerialInput Current Source DACAD5410 Single Channel, 12-Bit, SerialInput Current Source DACAD5422Preliminary Technical DataRev. PrE | Page 2 of 37TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Revision History...............................................................................2 Functional Block Diagram..............................................................3 Specifications.....................................................................................4 AC Performance Characteristics................................................7 Timing Characteristics................................................................8 Absolute Maximum Ratings..........................................................10 ESD Caution................................................................................10 Pin Configuration and Function Descriptions...........................11 Typical Performance Characteristics Voltage output ...............13 Typical Performance Characteristics current output ...............17 Typical Performance Characteristics general ............................20 Terminology....................................................................................22 Theory of Operation......................................................................24 Architecture.................................................................................24 Serial Interface............................................................................24 Default configuration.................................................................28 Transfer Function.......................................................................28 Data Register...............................................................................29 Control Register..........................................................................29 RESET register............................................................................29 Status register..............................................................................30 Features............................................................................................31 fault alert......................................................................................31 voltage output short circuit protection....................................31 Asynchronous Clear (CLEAR).................................................31 Internal Reference......................................................................31 External current setting resistor...............................................31 Voltage ouTput over-range........................................................31 Digital Power Supply..................................................................31 External boost function.............................................................31 digital Slew rate control.............................................................32 I OUT Filtering Capacitors............................................................32 Applications Information..............................................................33 driving inductive loads..............................................................33 Transient voltage protection.....................................................33 Layout Guidelines.......................................................................33 Galvanically Isolated Interface.................................................33 Microprocessor Interfacing.......................................................33 Thermal and supply considerations.........................................34 Outline Dimensions.......................................................................35 Ordering Guide.. (35)REVISION HISTORYPrE – Preliminary Version, November 22, 2007Preliminary Technical DataAD5422Rev. PrE | Page 3 of 37FUNCTIONAL BLOCK DIAGRAMV OUT I OUT LATCH SCLK SDIN SDOCCAGND CLEAR FAULT BOOSTREFOUT REFIN SENSESENSECLEAR SELECT R SET DV CC C COMP2C COMP1DGND**LFCSP PackageFigure 1.AD5422Preliminary Technical DataRev. PrE | Page 4 of 37SPECIFICATIONSAV DD = 10.8V to 40V , AV SS = -26.4V to -3V/0V , AV DD + |AV SS | < 52.8V , AGND = DGND = 0 V , REFIN= +5 V external; DV CC = 2.7 V to 5.5 V , V OUT : R L = 2 kΩ, C L = 200 pF, I OUT : R L = 300Ω, H L = 50mH; all specifications T MIN to T MAX , ±10 V / 0 to 24 mA range unless otherwise noted. Table 2.Parameter Value 1 Unit Test Conditions/CommentsVOLTAGE OUTPUTOutput Voltage Ranges 0 to 5 V 0 to 10 V -5 to +5 V -10 to +10 V ACCURACY Output unloaded Bipolar Output Resolution 16 Bits Total Unadjusted Error (TUE) 0.1 % FSR max Over temperature, supplies, and time, typically 0.05%FSRTUE TC 2 ±3 ppm typ Relative Accuracy (INL) ±0.012 % FSR max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic Bipolar Zero Error ±5 mV max @ 25°C, error at other temperatures obtained usingbipolar zero TCBipolar Zero TC 2±3 ppm FSR/°C max Zero-Scale Error ±1 mV max @ 25°C, error at other temperatures obtained using zeroscale TCZero-Scale TC 2±3 ppm FSR/°C max Gain Error ±0.05 % FSR max @ 25°C, error at other temperatures obtained using gainTCGain TC 2 ±8 ppm FSR/°C max Full-Scale Error 0.05 % FSR max @ 25°C, error at other temperatures obtained using gainTCFull-Scale TC 2 ±3 ppm FSR/°C max Unipolar Output AV SS = 0 V Resolution 16 Bits Total Unadjusted Error (TUE) 0.1 % FSR max Over temperature, supplies, and time, typically 0.05%FSRRelative Accuracy (INL) ±0.012 % FSR max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic (at 16 bit-resolution) Zero Scale Error +10 mV max @ 25°C, error at other temperatures obtained using gainTCZero Scale TC 2±3 ppm FSR/°C max Offset Error ±10 mV max Gain Error ±0.05 % FSR max @ 25°C, error at other temperatures obtained using gainTCGain TC 2±3 ppm FSR/°C max Full-Scale Error 0.05 % FSR max @ 25°C, error at other temperatures obtained using gainTCFull-Scale TC 2±3 ppm FSR/°C maxOUTPUT CHARACTERISTICS 2eadroom 0.8 V max 0.5 V typ Output Voltage TC ±3 ppm FSR/°C max Output Voltage Drift vs. Time ±12 ppm FSR/500 hr typ Vout = ¾ of Full-Scale ±15 ppm FSR/1000 hr typ Short-Circuit Current 12 mA typPreliminary Technical DataAD5422Rev. PrE | Page 5 of 37Parameter Value 1 Unit Test Conditions/Comments Load 2 kΩ min For specified performance Capacitive Load Stability R L = ∞ 20 nF max R L = 2 kΩ TBD nF max R L = ∞ 1 µF max External compensation capacitor of 4nF connected. DC Output Impedance 0.3 Ω typ Power-On Time 10 µs typ DC PSRR TBD µV/VCURRENT OUTPUTOutput Current Ranges 0 to 24 mA 0 to 20 mA 4 to 20 mA ACCURACY Resolution 16 Bits Total Unadjusted Error (TUE) ±0.3 % FSR max Over temperature, supplies, and time, typically 0.1% FSR TUE TC 2 ±5 ppm/°C typ Relative Accuracy (INL) ±0.012 % FSR max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic Offset Error ±0.05 % FSR max Offset Error Drift ±5 µv/°C typ Gain Error ±0.02 % FSR max @ 25°C, error at other temperatures obtained using gainTCGain TC 2 ±8 ppm FSR/°C max Full-Scale Error 0.05 % FSR max @ 25°C, error at other temperatures obtained using gainTCFull-Scale TC 2 ±8 ppm FSR/°COUTPUT CHARACTERISTICS 2Current Loop Compliance Voltage AVDD - 2.5 V max Output Current Drift vs. Time TBD ppm FSR/500 hr typ TBD ppm FSR/1000 hr typ Resistive Load TBD Ω max Inductive Load 1 H max DC PSRR 10 µA/V max Output Impedance 50 MΩ typREFERENCE INPUT/OUTPUTReference Input 2 Reference Input Voltage 5 V nom ±1% for specified performance DC Input Impedance 30 kΩ min Typically 40 kΩ Reference Range 4 to 5 V min to V max Reference Output Output Voltage 4.998 to 5.002 V min to V max @ 25°C Reference TC ±10 ppm/°C max Output Noise (0.1 Hz to 10 Hz)2 18 µV p-p typNoise Spectral Density 2120 nV/√Hz typ @ 10 kHz Output Voltage Drift vs. Time 2 ±40 ppm/500 hr typ ±50 ppm/1000 hr typ Capacitive Load TBD nF max Load Current 5 mA typ Short Circuit Current 7 mA typ Line Regulation 2 10 ppm/V typLoad Regulation 2TBD ppm/mA Thermal Hysteresis 2 TBD ppmAD5422 Preliminary Technical Data1 Temperature range: -40°C to +85°C; typical at +25°C.2 Guaranteed by characterization. Not production tested.Rev. PrE | Page 6 of 37Preliminary Technical DataAD5422Rev. PrE | Page 7 of 37AC PERFORMANCE CHARACTERISTICSAV DD = 10.8V to 40V , AV SS = -26.4V to -3V/0V , AV DD + |AV SS | < 52.8V , AGND = DGND = 0 V , REFIN= +5 V external; DV CC = 2.7 V to 5.5 V , V OUT : R L = 2 kΩ, C L = 200 pF, I OUT : R L = 300Ω, H L = 50mH; all specifications T MIN to T MAX , ±10 V / 0 to 24 mA range unless otherwise noted. Table 3.Parameter 1 Unit Test Conditions/Comments DYNAMIC PERFORMANCEVOLTAGE OUTPUTOutput Voltage Settling Time 8 µs typ Full-scale step (10 V) to ±0.03% FSR 10 µs max 5 µs max 512 LSB step settlingOutput Current Settling Time 10 µs max To 0.1% FSR Slew Rate 1 V/µs typ Power-On Glitch Energy 10 nV-sec typ Digital-to-Analog Glitch Energy 10 nV-sec typ Glitch Impulse Peak Amplitude 20 mV typ Digital Feedthrough 1 nV-sec typ Output Noise (0.1 Hz to 10 Hz Bandwidth) 0.1 LSB p-p typ Output Noise (100 kHz Bandwidth) 80 µV rms max 1/f Corner Frequency 1 kHz typ Output Noise Spectral Density 100 nV/√Hz typ Measured at 10 kHz AC PSRR TBD dB 200mV 50/60Hz Sinewavesuperimposed on power supply voltage.CURRENT OUTPUTOutput Current Settling Time TBD µs typ To 0.1% FSR , L = 1H TBD µs typ To 0.1% FSR , L < 1mH1Guaranteed by characterization, not production tested.AD5422Preliminary Technical DataRev. PrE | Page 8 of 37TIMING CHARACTERISTICSAV DD = 10.8V to 40V , AV SS = -26.4V to -3V/0V , AV DD + |AV SS | < 52.8V , AGND = DGND = 0 V , REFIN= +5 V external; DV CC = 2.7 V to 5.5 V , V OUT : R L = 2 kΩ, C L = 200 pF, I OUT : R L = 300Ω, H L = 50mH; all specifications T MIN to T MAX , ±10 V / 0 to 24 mA range unless otherwise noted. Table 4.Parameter 1, 2, 3 Limit at T MIN , T MAX Unit DescriptionWrite Modet 1 33 ns min SCLK cycle time t 2 13 ns min SCLK low time t 3 13 ns min SCLK high time t 4 13 ns min LATCH delay time t 5 40 ns min LATCH high time t 5 5 µs min LATCH high time (After a write to the CONTROL register) t 6 5 ns min Data setup time t 7 5 ns min Data hold time t 8 40 ns min LATCH low time t 9 20 ns min CLEAR pulsewidth t 10 5 µs max CLEAR activation timeReadback Modet 11 82 ns min SCLK cycle time t 12 33 ns min SCLK low time t 13 33 ns min SCLK high time t 14 13 ns min LATCH delay time t 15 40 ns min LATCH high time t 16 5 ns min Data setup time t 17 5 ns min Data hold time t 18 40 ns min LATCH low time t 19 40 ns max Serial output delay time (C L SDO 4 = 15pF) t 20 33 ns max LATCH rising edge to SDO tri-stateDaisychain Modet 21 82 ns min SCLK cycle time t 22 33 ns min SCLK low time t 23 33 ns min SCLK high time t 24 13 ns min LATCH delay time t 25 40 ns min LATCH high time t 26 5 ns min Data setup time t 27 5 ns min Data hold time t 28 40 ns min LATCH low time t 29 40 ns max Serial output delay time (C L SDO 4 = 15pF)1 Guaranteed by characterization. Not production tested.2All input signals are specified with t R = t F = 5 ns (10% to 90% of DV CC ) and timed from a voltage level of 1.2 V. 3See Figure 2, Figure 3, and Figure 4. 4C L SDO = Capacitive load on SDO output.Preliminary Technical DataAD5422Rev. PrE | Page 9 of 37SCLK LATCHSDINCLEAROUTPUTFigure 2. Write Mode Timing DiagramSCLKLATCHSDINSDOSELECTED REGISTER DATA CLOCKED OUTFIRST 8 BITS ARE DON’T CARE BITSFigure 3. Readback Mode Timing DiagramSCLKSDINSDOLATCHFigure 4. Daisychain Mode Timing DiagramAD5422Preliminary Technical DataRev. PrE | Page 10 of 37ABSOLUTE MAXIMUM RATINGST A = 25°C unless otherwise noted.Transient currents of up to 100 mA do not cause SCR latch-up. Table 5.Parameter Rating AV DD to AGND, DGND −0.3V to 48V AV SS to AGND, DGND +0.3 V to −48 V AV DD to AV SS -0.3V to 60V DV CC to AGND, DGND −0.3 V to +7 V Digital Inputs to AGND, DGND −0.3 V to DV CC + 0.3 V or 7 V(whichever is less)Digital Outputs to AGND, DGND −0.3 V to DV CC + 0.3 V or 7V(whichever is less)REFIN/REFOUT to AGND, DGND −0.3 V to +7 V V OUT to AGND, DGND AV SS to AV DD I OUT to AGND, DGND −0.3V to AV DD AGND to DGND -0.3V to +0.3V Operating Temperature Range Industrial −40°C to +851°C Storage Temperature Range −65°C to +150°C Junction Temperature (T J max) 125°C 24-Lead TSSOP Package θJA Thermal Impedance 42°C/W 40-Lead LFCSP Package θJA Thermal Impedance 28°C/W Power Dissipation (T J max – T A )/ θJA Lead Temperature JEDEC Industry StandardSoldering J-STD-020Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTION1Power dissipated on chip must be de-rated to keep junction temperature below 125°C. Assumption is max power dissipation condition is sourcing 24mA into Ground from AV DD with a 3mA on-chip current.PIN CONFIGURATION AND FUNCTION DESCRIPTIONSAGND SDOAV SSSENSE GNDLATCH CLEAR CLEAR SELECT REFIN SELECT SCLK SDIN GND R SETOUTBOOST C COMP1REFOUT DV CC C COMP2I OUTSENSEAV DDDV CCD G N G N A V S CA V S SA V D D N CN CV S E N S EV C CNCNC DV CC SELECT V S E N S EO U TBOOST C COMP1C COMP2I OUT N R S E NC A G N CN N R E F I R E F O U CAP2CAP1Figure 5. TSSOP Pin ConfigurationFigure 6. LFCSP Pin ConfigurationTSSOP Pin No. LFCSP Pin No. Mnemonic Descriptionoutputpin.19 26 I OUT Current20 27 BOOSTOptional external transistor connection. Connecting an external transistor will reducethe power dissipated in the AD5422. Refer to the features section.N/A 28 CAP1 Connection for optional output filtering capacitor. Refer to Features section.N/A 29 CAP2 Connection for optional output filtering capacitor. Refer to Features section.21 32 V OUT Buffered Analog Output Voltage. The output amplifier is capable of directly driving a 2kΩ, 2000 pF load.22 33 +V SENSE Sense connection for the positive voltage output load connection.23 34 -V SENSE Sense connection for the negative voltage output load connection.24 36 AV DD Positive Analog Supply Pin. Voltage ranges from 10.8V to 60V.Paddle Paddle AV SS Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can beconnected to 0V if output voltage range is unipolar.TYPICAL PERFORMANCE CHARACTERISTICSVOLTAGE OUTPUTFigure 7. Integral Non Linearity Error vs DAC Code (Four Traces)Figure 8. Differential Non Linearity Error vs. DAC Code (Four Traces)Figure 9. Total Unadjusted Error vs. DAC Code (Four Traces)Figure 10. Integral Non Linearity vs. Temperature (Four Traces)Figure 11. Differential Non Linearity vs. Temperature (Four Traces)Figure 12. Integral Non Linearity vs. Supply Voltage (Four Traces)Figure 13.Differential Non Linearity Error vs. Supply Voltage (Four Traces)Figure 14. Integral Non Linearity Error vs. Reference Voltage (Four traces)Figure 15. Differential Non Linearity Error vs. Reference Voltage (Four Traces)Figure 16. Total Unadjusted Error vs.Reference Voltage (Four Traces)Figure 17. Total Unadjusted Error vs. Supply Voltage (Four Traces)Figure 18. Offset Error vs.TemperatureFigure 19. Bipolar Zero Error vs. TemperatureFigure 20. Gain Error vs. TemperatureFigure 21. Source and Sink Capability of Output AmplifierFull-Scale Code LoadedFigure 22. Source and Sink Capability of Output AmplifierZero-Scale LoadedFigure 23.Full-Scale Positive StepFigure 24. Full-Scale Negative StepFigure 25. Digital-to-Analog Glitch EnergyFigure 26. Peak-to-Peak Noise (0.1Hz to 10Hz Bandwidth)Figure 27. Peak-to-Peak Noise (100kHz Bandwidth)Figure 28. V OUT vs. Time on Power-upFigure 29. V OUT vs, Time on Output EnabledTYPICAL PERFORMANCE CHARACTERISTICS CURRENT OUTPUTFigure 30. Integral Non Linearity vs. CodeFigure 31.Differential Non Linearity vs. CodeFigure 32. Total Unadjusted Error vs. CodeFigure 33. Integral Non Linearity vs. TemperatureFigure 34. Differential Non Linearity vs. TemperatureFigure 35. Integral Non Linearity vs. SupplyFigure 36. Differential Non Linearity vs. Supply VoltageFigure 37. Integral Non Linearity vs. Reference VoltageFigure 38. Differential Non Linearity vs. Reference VoltageFigure 39. Total Unadjusted Error vs. Reference VoltageFigure 40. Total Unadjusted Error vs. Supply VoltageFigure 41. Offset Error vs. TemperatureFigure 42. Gain Error vs. TemperatureFigure 43. Voltage Compliance vs. TemperatureFigure 44. I OUT vs. Time on Power-upFigure 45. I OUT vs. Time on Output EnabledTYPICAL PERFORMANCE CHARACTERISTICS GENERALFigure 46. DI CC vs.Logic Input VoltageFigure 47. AI DD /AI SS vs AV DD /AV SSFigure 48. AI DD vs AV DDFigure 49. DVCC Output Voltage vs. DI CC Load CurrentFigure 50. Refout Turn-on TransientFigure 51. Refout Output Noise (0.1Hz to 10Hz Bandwidth)Figure 52. Refout Output Noise (100kHz Bandwidth)Figure 53. Refout Line TransientFigure 54. Refout Load TransientFigure 55. Refout Histogram of Thermal HysteresisFigure 56. Refout Voltage vs. Load CurrentTERMINOLOGYRelative Accuracy or Integral Nonlinearity (INL)For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 7. Differential Nonlinearity (DNL)Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 10.MonotonicityA DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5724R/AD5734R/AD5754R are monotonic over their full operating temperature range.Bipolar Zero ErrorBipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen in Table TBD.Bipolar Zero TCBipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C.Full-Scale ErrorFull-Scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed in percent offull-scale range (% FSR).Negative Full-Scale Error/Zero-Scale ErrorNegative full-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage should be negative full-scale− 1 LSB. A plot of zero-scale error vs. temperature can be seen in Table TBD Zero-Scale TCThis is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C. Output Voltage Settling TimeOutput voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. A plot of settling time can be seen in Table TBD Slew RateThe slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage-output D/A converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs.Gain ErrorThis is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed in % FSR. A plot of gain error vs. temperature can be seen in Table TBDGain TCThis is a measure of the change in gain error with changes in temperature. Gain Error TC is expressed in ppm FSR/°C. Total Unadjusted ErrorTotal unadjusted error (TUE) is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR.Current Loop Voltage ComplianceThe maximum voltage at the I OUT pin for which the output currnet will be equal to the programmed value.Power-On Glitch EnergyPower-on glitch energy is the impulse injected into the analog output when the AD5422 is powered-on. It is specified as the area of the glitch in nV-sec. See Table TBDDigital-to-Analog Glitch ImpulseDigital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Table TBDGlitch Impulse Peak AmplitudeGlitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to0x8000). See Table TBD.Digital FeedthroughDigital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus.Power Supply Rejection Ratio (PSRR)PSRR indicates how the output of the DAC is affected by changes in the power supply voltage.Reference TCReference TC is a measure of the change in the reference output voltage with a change in temperature. It is expressed in ppm/°C. Line RegulationLine regulation is the change in reference output voltage due to a specified change in supply voltage. It is expressed in ppm/V. Load RegulationLoad regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA. Thermal HysteresisThermal hysteresis is the change of reference output voltage after the device is cycled through temperatures from +25°C to −40°C to +85°C and back to +25°C. This is a typical value from a sample of parts put through such a cycle. See Table TBDfor a histogram of thermal hysteresis.TCOOHYSOVVV__C)25(−°=6__10C)25(C)25()(×°−°=OTCOOHYSO VVVppmVwhere:V O(25°C) = V O at 25°CV O_TC = V O at 25°C after temperature cycleTHEORY OF OPERATIONThe AD5422 is a precision digital to current loop and voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop and unipolar/bipolar voltage outputs. The current ranges available are; 0 to 20mA, 0 to 24mA and 4 to 20mA, the voltage ranges available are; 0 to 5V , ±5V , 0 to 10V and ±10V , the current and voltage outputs are available onseparate pins and only one is active at any one time. The desired output configuration is user selectable via the CONTROL register.ARCHITECTUREThe DAC core architecture of the AD5422 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 57. The 4 MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects 1 of 15 matched resistors to either ground or the reference buffer output. The remaining 12 bits of the data-word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.V REFV OUT12-BIT R-2R LADDE RFOUR MSBs DECODED INTO 15 EQUAL SEGMENTSFigure 57. DAC Ladder StructureThe voltage output from the DAC core is either converted to a current (see diagram, Figure 58) which is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground or it is buffered and scaled to output a software selectable unipolar or bipolar voltage range (See diagram, Figure 59). The current and voltage are output onseparate pins and cannot be output simultaneously.I OUTFigure 58. Voltage to Current conversion circuitryREFINL1Figure 59. Voltage OutputVoltage Output AmplifierThe voltage output amplifier is capable of generating both unipolar and bipolar output voltages. It is capable of driving a load of 2 kΩ in parallel with 1 µF to AGND. The source and sink capabilities of the output amplifier can be seen in Figure TBD. The slew rate is 1 V/µs with a full-scale settling time of 10 µs, (10V step). Figure 59 shows the voltage output drving a load, R L on top of a common mode voltage of up to ±3V .In output module applications where a cable could possibly become disconnected from +V SENSE resulting in the amplifier loop being broken and most probably resulting in largedestructive voltages on V OUT , a resistor, R 1, of value 2k Ω to 5k Ω should be included as shown to ensure the amplifier loop is kept closed.Driving Large Capacitive LoadsThe voltage output amplifier is capable of driving capacitive loads of up to 1uF with the addition of a non-polarised 4nF compensation capacitor between the C COMP1 and C COMP2 pins. Without the compensation capacitor, up to 20nF capacitive loads can be driven.Reference BuffersThe AD5422 can operate with either an external or internal reference. The reference input has an input range of 4 V to 5 V , 5 V for specified performance. This input voltage is then buffered before it is applied to the DAC.SERIAL INTERFACEThe AD5422 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI®, QSPI™, MICROWIRE™, and DSP standards.Input Shift RegisterThe input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the rising edge of SCLK. The input register consists of 8 control bits and 16 data bits as shown in Table 7. The 24 bit word is unconditionally latched on the rising edge of LATCH. Data will continue to be clocked in irrespective of the state of LATCH, on the rising edge of LATCH the data that is present in the input register will be latched, in other words the last 24 bits to be clocked in before。

B-W040DN-402-EN, 2016-08-05TWA SeriesThree-Phase Winding Ohmmeters & Tap Changer & Winding AnalyzersDescriptionThe TWA series instruments are designed for six-winding resistance measurement and simultaneous three phase on-load tap changer analysis of both the primary and the secondary transformer windings (provided by the TWA40 model). This is performed with a one single-step cable setup, with test currents of up to 40A. Each transformer configuration has a special measurement algorithm which is optimized for the fast stabilization of test results. The TWA instruments generate a true DC ripple-free current. Both the injection of the current and the discharge of energy from the magnetic circuit are automatically regulated.ApplicationThe list of the instrument application includes:∙ A six-winding measurement of transformer winding resistances with a one-time cable connection ∙ Quick YN mode, which enables measuring the resistances of three transformer windings in the YNconfiguration simultaneously (TWA40D)∙ Dynamic resistance measurement (DVtest) of on-load tap changers, which can be performedsimultaneously on all three phases, or on a single phase (TWA40D)∙ An evaluation of synchronization between on-load tap changer phases (TWA40D)∙ A measurement of on-load tap changer motor current by using a dedicated channel (TWA40D)∙ A three-phase or single-phase automatic transformer demagnetization∙ Resistance measurement of all tap positions in all six windings performed in a single test∙ True three-phase on-load tap changer dynamic resistance measurement∙ Extremely quick measurement, single-step cable setup ∙ Automatic discharge process ∙ Rapid automatic demagnetization ∙ Built-in tap changer control unitB-W040DN-402-EN, 2016-08-05Connecting the TWA to a TransformerUsing two sets of four cables, all bushings of the primary and the secondary sides are connected only once. The connection to the transformer is made using two-contact clamps that provide the four-wire Kelvin test method.The figure presents the simultaneous testing of both windings (high side and low side) on a three-phase transformer. The setup time is minimized and the test is performed very quickly. The speed is increased by saturating the magnetic core through the HV and LV windings at the same time, so the total test time is very short. The TWA test leads are interchangeable with the test leads for the TRTThree-Phase Transformer Turns Ratio Testers.Benefits and FeaturesSix-Winding Resistance MeasurementThe TWA injects the current with a voltage value as high as 55 V. This ensures that the magnetic core is saturated quickly and duration of the test is as short as possible. All transformer windings, both primary and secondary, can be measured with a single cable setup. The TWA has internal memory capacity to store up to 500 measurements. All measurements are time and date-stamped. The instrument is equipped with thermal and overcurrent protection. The TWA has very high ability to cancel electrostatic and electromagnetic interference that exists in HV electric fields. It is achieved by a proprietarysolution applied to both the hardware construction and the application software implementation.A special mode is provided for the resistance measurement in multiple de-energized tap changer (DETC) positions.On Load Tap Changers –Simultaneous Dynamic Resistance Measurement (DRM) of All Three PhasesThe TWA40D can be used to measure the winding resistance of the individual taps of a power transformer without discharging between the tests.The unit also checks whether the on-load tap changer (OLTC) switches without an interruption. The moment a tap position is changed from one tap to another, the device detects a sudden, very short drop of the test current. These drops called "Ripple" should be consistent, where any drop out-of-line should be investigated. Tap changer malfunctions can be detected by analyzing the measurements of transition ripple, transition time, and visualizing DRM graphs, can be observed too. The currents in all three phases are recorded simultaneously. Test currents can reach up to 40 A in total during the test.Dynamic resistance graphs are recorded for all three phases simultaneously, so the synchronization is verified using the cursors provided in the DV-Win software. All three phase traces are plotted on the same graph. In addition, the tap changer motor current is recorded, and displayed on the same graph. The built-in tap changer control unit enables remote control of the tap changer operation from the instrument's keyboard.DV-Win SoftwareThe Windows-based DV-Win software enables control and observation of the test process, as well as saving and analyzing the results on a PC. It pro-vides a test report, arranged in a selectable form as an Excel spreadsheet, PDF, Word, or ASCII format. The software provides an OLTC (tap changer) condition assessment through analysis of the graphs representing dynamic resistance values during the tap changer transitions. Additionally, the DV-Win measures and calculates the OLTC transition time, the ripple and the winding resistance for each tap changing operation. The standard interface is USB. RS232 is optional.Additional testing mode, Quick YN, is enabled by the DV-Win software for the TWA40D model. In this mode, it is possible to measure the resistances of three transformer windings in the YN configuration simultaneously. It is also possible to test the resistances of all tap changer positions of all three phases in a single pass through the tap changer positions.Tap Changer Motor Current Monitoring ChannelThe AC and/or DC current monitoring channel enables monitoring and recording the OLTC mechanical drive motor current during the tap changer operation on the TWA40D model. The motor current waveform (or another useful signal) is printed on the same DV-Win-generated DRM graph, and can help in detecting OLTC mechanical problems. Motor recording allows for DRM recording using the motor operation trigger, which is useful for reactance tap changers. An AC/DC current clamp is available as an optional accessory.Automatic Transformer DemagnetizationAfter a DC current test, such as a winding resistance measurement, the magnetic core of a power or instrument transformer may be magnetized. Also, when disconnecting a transformer from a service, some amount of magnetic flux trapped in the core could be present.The remnant magnetism can cause various problems such as erroneous measurements on a transformer, or an inrush current at start-up of a power transformer, or an incorrect operation of the protective relays due to the magnetized CT cores. To eliminate this source of potential problems, demagnetization should be performed. When the discharging process has been completed, the TWA can perform fully automatic demagnetization.Demagnetizing the magnetic core of a transformer requires alternating current applied with decreasing magnitude down to zero. The TWA provides this alternating current byB-W040DN-402-EN, 2016-08-05B-W040DN-402-EN, 2016-08-05internally changing the polarity of a controlled DC current. During the demagnetization process the TWA supplies current at decreasing magnitude for each step, following the proprietary developed program. The TWA40D enables performing both single-phase and three-phase demagnetization.Technical DataWinding Resistance Measurement∙ Test currents: 5 mA – 25 A DC (TWA25A)5 mA – 40 A DC (TWA40D)∙ Output voltage: up to 55 V DC ∙ Measurement range: 0,1 μΩ - 10 kΩ ∙Typical accuracy: ± (0,1 % rdg + 0,1 % F.S.)Resolution∙ 0,1 μΩ – 999,9 μΩ: 0,1 μΩ ∙ 1,000 mΩ – 9,999 mΩ: 1 μΩ ∙ 10,00 mΩ – 99,99 mΩ: 10 μΩ ∙ 100,0 mΩ – 999,9 mΩ: 0,1 mΩ ∙ 1,000 Ω – 9,999 Ω: 1 mΩ ∙ 10,00 Ω - 99,99 Ω: 10 mΩ ∙ 100,0 Ω – 999,9 Ω: 0,1 Ω ∙1 000 Ω – 9 999 Ω: 1 ΩData Storage∙ 500 internal memory positions∙USB flash drive feature enables storage of a huge number of measurementsOLTC Dynamic Resistance Measurement∙ Sampling rate: 0,1 ms for TWA40D, 4 ms for TWA25A∙ Automatic open circuit detection and warning ∙ Transition current ripple measurement ∙ Transition time measurement using DV-Win software∙Timing measurement of different transition changes using DV-Win graph analysis toolAC Current Measurement Channel (TWA40D)∙ Resolution: 0,1 ms ∙Amplitude resolution: 16 bitCurrent Clamp Meter Specifications∙ Nominal current: 300 A RMS or 450 A DC PK ∙ Measuring ranges: 30/300 A∙ Frequency range: DC to 20 kHz (-3 dB) ∙ Resolution: ± 50 / ± 100 mA ∙Accuracy: ± 1% of the readingComputer Interface∙ USB∙Optional: RS232Warranty∙Three yearsEnvironmental Conditions∙ Operating temperature:-10 ºC - + 55 ºC / 14 ºF - +131 ºF ∙ Storage & transportation: -40 ºC - + 70ºC / -40 ºF - +158 ºF ∙Humidity 5 % - 95 % relative humidity, non-condensingDimensions and Weight∙Dimensions (W x H x D): 480 mm x 197 mm x 395 mm18.9 in x 7.8 in x 15.6 in ∙Weight:12,8 kg / 28.3 lbsB-W040DN-402-EN, 2016-08-05Mains Power Supply∙ Connection according to IEC/EN60320-1; UL498, CSA 22.2∙ Mains supply: 90 V - 264 V AC ∙ Frequency: 50/60 Hz∙Mains supply voltage fluctuations up to±10 % of the nominal voltage ∙ Input power: 2 250 VA∙Fuse 15 A / 250 V, type F, not user replaceableApplicable Standards∙ Installation/overvoltage: category II ∙ Pollution: degree 2 ∙Low voltage directive:Directive 2014/35/EU (CE Conform) Applicable standards, for a class Iinstrument, pollution degree 2, installation category II : IEC EN 61010-1∙Electromagnetic compatibility: Directive 2014/30/EU (CE Conform) Applicable standard EN 61326-1∙CAN/CSA-C22.2 No. 61010-1, 2nd edition, including Amendment 1All specifications herein are valid at ambient temperature of + 25 °C and recommended accessories. Specifications are subject to change without noticeSpecifications are valid if the instrument is used with the recommended set of accessoriesH winding test cable setX winding test cable setCable plastic caseCurrent clamp 30/300 A(TWA40D)Test shuntTransport caseTWA Series – ModelsYes Yes5 mA – 25 A5 mA – 25 A; up to 25 A for winding resistance measurement and up to 40 A for the 3-phase synchronization test± (0,1 % rdg + 0,1 % FS)Yes (Quick YN test)0.1 msYesYesYesYesB-W040DN-402-EN, 2016-08-05Order InfoB-W040DN-402-EN, 2016-08-05IBEKO Power AB ContactStockholmsvägen 18Phone: +46 70 0925 000181 50 Lidingö, Sweden E-mail:******************。

[报废处理注意事项]
报废时 将本产品当作工业废弃物处理
! 小心
A-3
修订记录
印刷日期 2000 年 9 月 2001 年 6 月
手册编号 SH(NA)-080087-A SH(NA)-080087-B
第一次印刷 程序示例修改 部分修改 总称 缩写的 2.1 节 3.5.2 节 4.7.2 节
2.2 节
2. 系统配置
2-1 至 2-2
2.1 整个配置......................................................................................................................................................2-1 2.2 适用系统......................................................................................................................................................2-2
[接线注意事项] ! 小心
在开始安装 接线或其它工作之前 必须断开外部所有相的电源 不这样做可能会损坏产品或出现误动作 必须采用 PLC 专用的 D 种接地 第三种接地 方式把 FG 端子和 FG1 端子接地 不这样做可能导致误动作 在确认了产品的额定电压和端子接线正确无误之后再为模块正确接线 如果连接不符合额定值的 电源或接错线 可能导致火灾或故障 一定要在规定扭矩范围内紧固端子螺钉 如果没有拧紧可能导致短路或误动作 如果拧得过紧可能损坏螺钉或模块而导致短路或误动作 一定不要让异物 如切屑或接线头等 进入模块 异物进入模块可能导致火灾 故障或误动作