MU03-3205中文资料

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内 部开关拉到低电平，表示充电正在进行；否则 管脚处于高阻态． ＣＥ 芯片使能输入端 ．高输入电平将使ＣＮ３０５２Ａ处于正常工作状态；低输入电 平使ＣＮ３０５２Ａ处于被禁止状态． ＣＥ管脚可以被ＴＴＬ电平或者ＣＭＯＳ电平驱 动． １ ＴＥＭＰ ２ ＩＳＥＴ ５ ＢＡＴ ６ ７ ８ 极限参数 管脚电压………………………－０．３Ｖ ｔｏ ６．５Ｖ ＢＡＴ 管脚短路持续时间………连续 静电放电（ＨＢＭ）……………．…２ＫＶ 热阻（ＳＯＰ８）……………………ＴＢＤ 最高结温…．… ………………１５０℃ 工作温度…．………－４０℃ ｔｏ ８５℃ 存储温度……………－６５℃ ｔ ｏ １５０℃ 焊接温度（１０ 秒）……………．．３００℃ 超出以上所列的极限参数可能造成器件的永久损坏．以上给出的仅仅是极限范围 ，在这样的极限条件下 工作，器件的技术指标将得不到保证，长期在这种条件下还会影 响器件的可靠性． ＲＥＶ １．４ ４ 电气参数： （ＶＩＮ＝５Ｖ， 除非另外注明，ＴＡ＝－４０℃ 到 ８５℃， 典型值在环境温度为２５℃时测得） 参数 符号 测试条件 最小 典型 输入电源电压 工作电流 电源电压过低锁存阈 值 电源电压过低检测阈 值迟滞 恒压充电电压 ＶＩＮ ＩＶＩＮ Ｖｕｖｌｏ Ｈｕｖｌｏ ＶＲＥＧ ＣＮ３０５２Ａ Ｒ ＩＳＥＴ＝３．６Ｋ， 恒流充电模式 ＣＮ３０５２Ａ 电池连接端电流 ＩＢＡＴ ＲＩＳＥＴ＝３．６Ｋ， ＶＢＡＴ＝２．３Ｖ ＣＮ３０５２Ａ ＶＢＡＴ＝ＶＲＥＧ ＣＥ＝ＧＮＤ， 芯片被禁止状态 ＶＩＮ＝０Ｖ， 睡眠模式 预充电阈值 预充电 阈值 预充电阈值迟滞 充电结束阈值 充电结束阈值 再充电阈值 再充电阈值 睡眠模 式 睡眠模式阈值 睡眠模式解除阈值 ＩＳＥＴ管脚 ＩＳＥＴ管脚电压 ＴＥＭＰ管脚 高端阈值 低 端阈值 输入电流 ＣＥ管脚 输入低电平 输入高电平 输入电流 ＶＣＥＬ ＶＣＥＨ ＩＣＥＬ ＩＣＥＨ ＣＥ电压下降 ＣＥ电压上升 ＣＥ＝ＧＮＤ， ＶＩＮ＝６Ｖ ＣＥ＝ＶＩＮ＝６Ｖ ２．０ －１ １ ０．７５ Ｖ Ｖ ｕＡ ＶＨＩＧＨ ＶＬＯＷ ＴＥＭＰ到ＶＩＮ或到地端的电流 ４２．５ ８０ ４５ ０．５ ８２．５ ％ＶＩＮ ％ＶＩＮ ｕＡ ＶＩＳＥＴ ＶＢＡＴ＜２ ．９Ｖ，预充电模式 恒流充电模式 ０．２ ２．０ Ｖ ＶＳＬＰ ＶＳＬＰＲ ＶＩＮ下降 测量电压差（ＶＩＮ－ＶＢ ＡＴ） ＶＩＮ上升 测量电压差（ＶＩＮ－ＶＢＡＴ） ４０ ９０ ｍｖ ｍｖ ＶＲＥＣＨ ＶＲＥＧ－０．１ Ｖ Ｖｔｅｒｍ 测量ＩＳ ＥＴ管脚的电压 ０．１８ ０．２２ ０．２６ Ｖ ＶＰＲＥ ＨＰＲＥ ＢＡＴ管脚电压上升 ２．９ ３．０ ０．１ ３．１ Ｖ Ｖ ４．１５８ ４００ ２５ １．７５ ＣＥ＝ＶＩＮ，ＢＡＴ端无负载 芯片被禁止状态，ＣＥ＝ＧＮＤ ＶＩＮ上升 ３．８３ ４．３５ ４００ ６５０ ４ ４．０３ ０．１ ４．２ ５００ ５０ ３．５ ４．２４２ ６００ ｍＡ ７５ ７ ３ ３ ｕＡ ４．２３ 最大 ６ ９５０ 单位 Ｖ ｕＡ Ｖ Ｖ Ｖ ＲＥＶ １．４ ５ 电气参数（接上页） 参数 管脚 下拉电流 漏电流 管脚 下拉电流 漏电流 ＩＦＡＵＬＴ ＶＦＡＵＬＴ＝０．３Ｖ，电池 故障状态 ＣＥ＝ＧＮＤ， ＶＦＡＵＬＴ＝６Ｖ １０ １ ｍＡ ｕＡ ＩＣＨＲＧ ＶＣＨＲＧ＝０．３Ｖ，充电模式 ＣＥ＝ＧＮＤ， ＶＣ ＨＲＧ＝６Ｖ １０ １ ｍＡ ｕＡ 符号 测试条件 最小 典型 最大 单位 详细描述 ＣＮ３０５２Ａ是专门为一节锂离子或锂聚合物电池而设计的线性充电器电路，利用芯片 内部的功率晶体管对 电池进行恒流和恒压充电．充电电流可以用外部电阻编程设定，最 大持续充电电流可达５００ｍＡ，不需要 另加阻流二极管和电流检测电阻．ＣＮ３０５２Ａ包含两个 漏极开路输出的状态指示输出端，充电状态指示端 和电池故障状态指示输出端 ． 芯片 内部的功率管理电路在芯片的结温超过１１５℃时自动降低充 电电流，这个功能可以使用 户最大限度的利用芯片的功率处理能力，不用担心芯片过热而损坏芯片或者 外部元器

e) 应对所有不锈钢小管进行液压或气压测试 例如 一个系统中的一组小管或每个单独 的小管
f) 在移交已安装完毕的系统之前 应对可能被 NSP 里其它施工活动所破坏的裸露的管线 更换
g) 仪表管安装时应按以下要求和总布置图 6 的规则作为最低要求进行管道的详细布置安 装.当安装时,由于设备工艺管道或结构部件占据了仪表管的安装空间而根据设计图纸 (文件)必须从此通过时,此问题必须由工程师出面解决.另外因超过本程序或者 98-60610-TS-001 安装要求的也应通过工程师解决
7.6 小管敷设
7.6.1 一般要求
a) 一般地 要求要在一块清洁的区域对小管进行预制和装配 然后运到现场并以下方式 进行安装 保证正确的坡度 与柱和轴线垂直 明敷的小管 例如进入/引出贯穿板 进出小管桥架/小管支架的小管 到盘或台架的管线 其安装后看起来应美观 装配和 安装不锈钢小管的工人应戴上白色棉质手套
5.3.2 电气队 QC 组应对班组的施工进行检查 并形成记录
5.3.3 QC 人员应负责验证安装工作是否按照程序和安装标准进行的
5.4 材料管理
5.4.1 在工作场所应控制材料的流失 使用和暂时的短缺
5.4.2 小管安装前应把管子和管件放在指定的工作场所 按要求储存和保护 避免和不同 材料的表面接触 不锈钢管材不应与碳钢材料相接触 应妥善保管 如在地面上或碳钢 架 台上放置应用木块垫起 搬运时不能在地面拖拉 注意不要使其表面划伤
b) 要保证端盖上塑料盖 所有管线 在连接前都用不带油渍的干燥的空气或惰性气体进行吹扫
c) 管线在如下的地方用不锈钢标签作永久性的标志 小管和大管连接处 在小管连接到 设备 无焊口的小管
d) 对每个单独的小管管线 在进行最终的连接前 要吹扫干净 然后正确连接 并作好 记录 第一个焊口应在工艺侧 最后一个焊口应在上游的隔离阀

Features•Utilizes the AVR® RISC Architecture•AVR – High-performance and Low-power RISC Architecture –120 Powerful Instructions – Most Single Clock Cycle Execution –32 x 8 General Purpose Working Registers–Fully Static Operation–Up to 20 MIPS Throughput at 20 MHz•Data and Non-volatile Program and Data Memories–2K Bytes of In-System Self Programmable FlashEndurance 10,000 Write/Erase Cycles–128 Bytes In-System Programmable EEPROMEndurance: 100,000 Write/Erase Cycles–128 Bytes Internal SRAM–Programming Lock for Flash Program and EEPROM Data Security •Peripheral Features–One 8-bit Timer/Counter with Separate Prescaler and Compare Mode–One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes –Four PWM Channels–On-chip Analog Comparator–Programmable Watchdog Timer with On-chip Oscillator–USI – Universal Serial Interface–Full Duplex USART•Special Microcontroller Features–debugWIRE On-chip Debugging–In-System Programmable via SPI Port–External and Internal Interrupt Sources–Low-power Idle, Power-down, and Standby Modes–Enhanced Power-on Reset Circuit–Programmable Brown-out Detection Circuit–Internal Calibrated Oscillator•I/O and Packages–18 Programmable I/O Lines–20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF•Operating Voltages–1.8 - 5.5V (ATtiny2313V)–2.7 - 5.5V (ATtiny2313)•Speed Grades–ATtiny2313V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V–ATtiny2313: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V•Typical Power Consumption–Active Mode1 MHz, 1.8V: 230 µA32 kHz, 1.8V: 20 µA (including oscillator)–Power-down Mode< 0.1 µA at 1.8V 8-bit Microcontroller2ATtiny2313/V2543IS–AVR–04/06Pin ConfigurationsFigure 1. Pinout ATtiny2313OverviewThe ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle,the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.3ATtiny2313/V2543IS–AVR–04/06Block DiagramFigure 2. Block Diagram4ATtiny2313/V2543IS–AVR–04/06The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 18general purpose I/O lines, 32 general purpose working registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with compare modes, internal and external interrupts, a serial program-mable USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The Power-down mode saves the register con-tents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.The device is manufactured using Atmel’s high density non-volatile memory technology.The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, or by a conventional non-volatile memory programmer.By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a mono-lithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.The ATtiny2313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-cuit Emulators, and Evaluation kits.5ATtiny2313/V2543IS–AVR–04/06Pin DescriptionsVCC Digital supply voltage.GNDGround.Port A (PA2..PA0)Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port A also serves the functions of various special features of the ATtiny2313 as listed on page 53.Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port B also serves the functions of various special features of the ATtiny2313 as listed on page 53.Port D (PD6..PD0)Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port D also serves the functions of various special features of the ATtiny2313 as listed on page 56.Reset input. A low level on this pin for longer than the minimum pulse length will gener-ate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 34. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate function for PA2 and dW.XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.XTAL1 is an alternate function for PA0.XTAL2Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.ResourcesA comprehensive set of development tools, application notes and datasheets are avail-able for downloadon /avr.6ATtiny2313/V2543IS–AVR–04/06Register SummaryAddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page0x3F (0x5F)SREG I T H S V N Z C 70x3E (0x5E)Reserved ––––––––0x3D (0x5D)SPL SP7SP6SP5SP4SP3SP2SP1SP0100x3C (0x5C)OCR0B Timer/Counter0 – Compare Register B780x3B (0x5B)GIMSK INT1INT0PCIE –––––600x3A (0x5A)EIFR INTF1INTF0PCIF –––––620x39 (0x59)TIMSK TOIE1OCIE1A OCIE1B –ICIE1OCIE0B TOIE0OCIE0A 79, 1100x38 (0x58)TIFR TOV1OCF1A OCF1B –ICF1OCF0B TOV0OCF0A 790x37 (0x57)SPMCSR –––CTPB RFLB PGWRT PGERS SELFPRGEN1560x36 (0x56)OCR0A Timer/Counter0 – Compare Register A780x35 (0x55)MCUCR PUD SM1SE SM0ISC11ISC10ISC01ISC00530x34 (0x54)MCUSR ––––WDRF BORF EXTRF PORF 370x33 (0x53)TCCR0B FOC0A FOC0B ––WGM02CS02CS01CS00770x32 (0x52)TCNT0Timer/Counter0 (8-bit)780x31 (0x51)OSCCAL –CAL6CAL5CAL4CAL3CAL2CAL1CAL0250x30 (0x50)TCCR0A COM0A1COM0A0COM0B1COM0B0––WGM01WGM00740x2F (0x4F)TCCR1A COM1A1COM1A0COM1B1COM1BO ––WGM11WGM101050x2E (0x4E)TCCR1B ICNC1ICES1–WGM13WGM12CS12CS11CS101080x2D (0x4D)TCNT1H Timer/Counter1 – Counter Register High Byte 1090x2C (0x4C)TCNT1L Timer/Counter1 – Counter Register Low Byte 1090x2B (0x4B)OCR1AH Timer/Counter1 – Compare Register A High Byte 1090x2A (0x4A)OCR1AL Timer/Counter1 – Compare Register A Low Byte 1090x29 (0x49)OCR1BH Timer/Counter1 – Compare Register B High Byte 1100x28 (0x48)OCR1BL Timer/Counter1 – Compare Register B Low Byte1100x27 (0x47)Reserved ––––––––0x26 (0x46)CLKPR CLKPCE–––CLKPS3CLKPS2CLKPS1CLKPS0270x25 (0x45)ICR1H Timer/Counter1 - Input Capture Register High Byte 1100x24 (0x44)ICR1L Timer/Counter1 - Input Capture Register Low Byte1100x23 (0x43)GTCCR –––––––PSR10820x22 (ox42)TCCR1C FOC1A FOC1B ––––––1090x21 (0x41)WDTCSR WDIF WDIE WDP3WDCE WDE WDP2WDP1WDP0420x20 (0x40)PCMSK PCINT7PCINT6PCINT5PCINT4PCINT3PCINT2PCINT1PCINT0620x1F (0x3F)Reserved ––––––––0x1E (0x3E)EEAR –EEPROM Address Register 150x1D (0x3D)EEDR EEPROM Data Register160x1C (0x3C)EECR ––EEPM1EEPM0EERIE EEMPE EEPE EERE 160x1B (0x3B)PORTA –––––PORTA2PORTA1PORTA0580x1A (0x3A)DDRA –––––DDA2DDA1DDA0580x19 (0x39)PINA –––––PINA2PINA1PINA0580x18 (0x38)PORTB PORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0580x17 (0x37)DDRB DDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB0580x16 (0x36)PINB PINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB0580x15 (0x35)GPIOR2General Purpose I/O Register 2200x14 (0x34)GPIOR1General Purpose I/O Register 1200x13 (0x33)GPIOR0General Purpose I/O Register 0200x12 (0x32)PORTD –PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD0580x11 (0x31)DDRD –DDD6DDD5DDD4DDD3DDD2DDD1DDD0580x10 (0x30)PIND –PIND6PIND5PIND4PIND3PIND2PIND1PIND0580x0F (0x2F)USIDR USI Data Register1450x0E (0x2E)USISR USISIF USIOIF USIPF USIDC USICNT3USICNT2USICNT1USICNT01460x0D (0x2D)USICR USISIE USIOIE USIWM1USIWM0USICS1USICS0USICLK USITC 1470x0C (0x2C)UDR UART Data Register (8-bit)1300x0B (0x2B)UCSRA RXC TXC UDRE FE DORUPE U2X MPCM 1300x0A (0x2A)UCSRB RXCIE TXCIE UDRIE RXEN TXENUCSZ2RXB8TXB81320x09 (0x29)UBRRL UBRRH[7:0]1340x08 (0x28)ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1ACIS01500x07 (0x27)Reserved ––––––––0x06 (0x26)Reserved ––––––––0x05 (0x25)Reserved ––––––––0x04 (0x24)Reserved ––––––––0x03 (0x23)UCSRC –UMSEL UPM1UPM0USBSUCSZ1UCSZ0UCPOL1330x02 (0x22)UBRRH ––––UBRRH[11:8]1340x01 (0x21)DIDR ––––––AIN1D AIN0D 1510x00 (0x20)Reserved––––––––7ATtiny2313/V2543IS–AVR–04/06Note:1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addressesshould never be written.2.I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In theseregisters, the value of single bits can be checked by using the SBIS and SBIC instructions.3.Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBIinstructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.4.When using the I/O specific commands IN and OUT , the I/O addresses 0x00 - 0x3F must be used. When addressing I/ORegisters as data space using LD and ST instructions, 0x20 must be added to these addresses.8ATtiny2313/V2543IS–AVR–04/06Instruction Set SummaryMnemonicsOperandsDescriptionOperation Flags#ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two RegistersRd ← Rd + RrZ,C,N,V,H 1ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2SUB Rd, Rr Subtract two RegistersRd ← Rd - Rr Z,C,N,V,H 1SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1SBCI Rd, K Subtract with Carry Constant from Reg.Rd ← Rd - K - C Z,C,N,V,H 1SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2AND Rd, Rr Logical AND RegistersRd ← Rd • Rr Z,N,V 1ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1OR Rd, Rr Logical OR RegistersRd ← Rd v RrZ,N,V 1ORI Rd, K Logical OR Register and Constant Rd ← Rd v KZ,N,V 1EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K)Z,N,V 1INC Rd Increment Rd ← Rd + 1Z,N,V 1DEC Rd DecrementRd ← Rd − 1 Z,N,V 1TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1SER Rd Set Register Rd ← 0xFF None 1BRANCH INSTRUCTIONSRJMP kRelative Jump PC ← PC + k + 1None 2IJMP Indirect Jump to (Z)PC ← Z None 2RCALL kRelative Subroutine Call PC ← PC + k + 1None 3ICALL Indirect Call to (Z)PC ←Z None 3RET Subroutine Return PC ← STACK None 4RETI Interrupt Return PC ← STACKI 4CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3None 1/2/3CP Rd,Rr CompareRd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with CarryRd − Rr − C Z, N,V,C,H 1CPI Rd,K Compare Register with Immediate Rd − KZ, N,V,C,H 1SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3None 1/2/3SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3None 1/2/3BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC+k + 1None 1/2BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC+k + 1None 1/2BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1None 1/2BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1None 1/2BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1None 1/2BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1None 1/2BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1None 1/2BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1None 1/2BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1None 1/2BRPL k Branch if Plusif (N = 0) then PC ← PC + k + 1None 1/2BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1None 1/2BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1None 1/2BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1None 1/2BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1None 1/2BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1None 1/2BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1None 1/2BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1None 1/2BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1None 1/2BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1None 1/2BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1None 1/2BIT AND BIT-TEST INSTRUCTIONSSBI P,b Set Bit in I/O Register I/O(P,b) ←1None 2CBI P,b Clear Bit in I/O Register I/O(P,b) ←0None 2LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V 1LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V 1ROLRd Rotate Left Through CarryRd(0)←C,Rd(n+1)← Rd(n),C ←Rd(7)Z,C,N,V19ATtiny2313/V2543IS–AVR–04/06ROR Rd Rotate Right Through CarryRd(7)←C,Rd(n)← Rd(n+1),C ←Rd(0)Z,C,N,V 1ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6Z,C,N,V 1SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)None 1BSET s Flag Set SREG(s) ← 1SREG(s)1BCLR s Flag ClearSREG(s) ← 0 SREG(s)1BST Rr, b Bit Store from Register to T T ← Rr(b)T 1BLD Rd, bBit load from T to Register Rd(b) ← T None 1SEC Set Carry C ←1C 1CLC Clear Carry C ← 0 C 1SEN Set Negative Flag N ← 1N 1CLN Clear Negative Flag N ← 0 N 1SEZ Set Zero Flag Z ←1Z 1CLZ Clear Zero Flag Z ← 0 Z 1SEI Global Interrupt Enable I ←1I 1CLI Global Interrupt Disable I ← 0 I 1SES Set Signed Test Flag S ← 1S 1CLS Clear Signed Test FlagS ← 0S 1SEV Set Twos Complement Overflow.V ← 1V 1CLV Clear Twos Complement Overflow V ← 0V 1SET Set T in SREG T ← 1T 1CLT Clear T in SREGT ← 0T 1SEH Set Half Carry Flag in SREG H ← 1H 1CLHClear Half Carry Flag in SREG H ← 0H 1DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← RrNone 1MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1LDI Rd, K Load Immediate Rd ←KNone 1LD Rd, X Load IndirectRd ← (X)None 2LD Rd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None 2LD Rd, - X Load Indirect and Pre-Dec.X ← X - 1, Rd ← (X)None 2LD Rd, Y Load IndirectRd ← (Y)None 2LD Rd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None 2LD Rd, - Y Load Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)None 2LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q)None 2LD Rd, Z Load IndirectRd ← (Z)None 2LD Rd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None 2LD Rd, -Z Load Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None 2LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q)None 2LDS Rd, k Load Direct from SRAM Rd ← (k)None 2ST X, Rr Store Indirect(X) ← RrNone 2ST X+, Rr Store Indirect and Post-Inc.(X) ← Rr, X ← X + 1None 2ST - X, Rr Store Indirect and Pre-Dec.X ← X - 1, (X) ← Rr None 2ST Y, Rr Store Indirect(Y) ← RrNone 2ST Y+, Rr Store Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None 2ST - Y, Rr Store Indirect and Pre-Dec.Y ← Y - 1, (Y) ← Rr None 2STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2ST Z, Rr Store Indirect(Z) ← RrNone 2ST Z+, Rr Store Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None 2ST -Z, Rr Store Indirect and Pre-Dec.Z ← Z - 1, (Z) ← Rr None 2STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2STS k, RrStore Direct to SRAM (k) ← Rr None 2LPM Load Program Memory R0 ← (Z)None 3LPM Rd, Z Load Program MemoryRd ← (Z)None 3LPM Rd, Z+Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1None 3SPM Store Program Memory (Z) ← R1:R0None -IN Rd, P In Port Rd ←P None 1OUT P, Rr Out PortP ← Rr None 1PUSH Rr Push Register on Stack STACK ← Rr None 2POP Rd Pop Register from Stack Rd ← STACKNone 2MCU CONTROL INSTRUCTIONSNOP No Operation None1SLEEP Sleep(see specific descr. for Sleep function)None 1WDRWatchdog Reset(see specific descr. for WDR/timer)None 1BREAKBreakFor On-chip Debug OnlyNoneN/AMnemonicsOperandsDescriptionOperationFlags#Clocks10ATtiny2313/V2543IS–AVR–04/06Ordering InformationNote:1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informationand minimum quantities.2.Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-tive).Also Halide free and fully Green.3.For Speed vs. V CC, see Figure 82 on page 181 and Figure 83 on page 181.Speed (MHz)(3)Power SupplyOrdering Code Package (1)Operation Range10 1.8 - 5.5VA Ttiny2313V-10PI A Ttiny2313V-10PU (2)A Ttiny2313V-10SI A Ttiny2313V-10SU (2)A Ttiny2313V-10MU (2)20P320P320S 20S 20M1Industrial (-40°C to 85°C)20 2.7 - 5.5VA Ttiny2313-20PI A Ttiny2313-20PU (2)A Ttiny2313-20SI A Ttiny2313-20SU (2)A Ttiny2313-20MU (2)20P320P320S 20S 20M1Industrial (-40°C to 85°C)Package Type20P320-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)20M120-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)11ATtiny2313/V2543IS–AVR–04/06Packaging Information20P312ATtiny2313/V2543IS–AVR–04/0620S13ATtiny2313/V2543IS–AVR–04/0620M114ATtiny2313/V2543IS–AVR–04/06ErrataThe revision in this section refers to the revision of the ATtiny2313 device.ATtiny2313 Rev B•Wrong values read after Erase Only operation •Parallel Programming does not work •Watchdog Timer Interrupt disabled•EEPROM can not be written below 1.9 volts1.Wrong values read after Erase Only operationAt supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00).Problem Fix/WorkaroundIf it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed.2.Parallel Programming does not workParallel Programming is not functioning correctly. Because of this, reprogramming of the device is impossible if one of the following modes are selected: –In-System Programming disabled (SPIEN unprogrammed)–Reset Disabled (RSTDISBL programmed)Problem Fix/WorkaroundSerial Programming is still working correctly. By avoiding the two modes above, the device can be reprogrammed serially.3.Watchdog Timer Interrupt disabledIf the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-out following an interrupt, the device works correctly.Problem fix / WorkaroundMake sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. This is done by selecting a long enough time-out period.4.EEPROM can not be written below 1.9 voltsWriting the EEPROM at V CC below 1.9 volts might fail.Problem fix / WorkaroundDo not write the EEPROM when V CC is below 1.9 volts.ATtiny2313 Rev ARevision A has not been sampled.15ATtiny2313/V2543IS–AVR–04/06Datasheet Revision HistoryPlease note that the referring page numbers in this section are referred to this docu-ment. The referring revision in this section are referring to the document revision.Changes from Rev. 2514H-02/05 to Rev. 2514I-04/06Changes from Rev. 2514G-10/04 to Rev. 2514H-02/05Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04Changes from Rev. 2514E-04/04 to Rev. 2514F-08/041.Updated typos.2.Updated Figure 1 on page 2.3Added “Resources” on page 6.4.Updated “Default Clock Source” on page 25.5.Updated “128 kHz Internal Oscillator” on page 30.6.Updated “Power Management and Sleep Modes” on page 337.Updated Table 3 on page 25,Table 13 on page 33, Table 14 on page 34,Table 19 on page 45, Table 31 on page 63, Table 79 on page 180.8.Updated “External Interrupts” on page 62.9.Updated “Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0” on page 65.10.Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 153.11.Updated “Calibration Byte” on page 164.12.Updated “DC Characteristics” on page 181.13.Updated “Register Summary” on page 6.14.Updated “Ordering Information” on page 10.15.Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x to OCF1x.1.Updated Table 6 on page 24, Table 15 on page 34, Table 68 on page 161and Table 80 on page 180.2.Changed CKSEL default value in “Default Clock Source” on page 22 to 8 MHz.3.Updated “Programming the Flash” on page 166, “Programming the EEPROM” on page 168 and “Enter Programming Mode” on page 164.4.Updated “DC Characteristics” on page 178.5.MLF option updated to “Quad Flat No-Lead/Micro Lead Frame (QFN/MLF)”1.Updated “Features” on page 1.2.Updated “Pinout ATtiny2313” on page 2.3.Updated “Ordering Information” on page 10.4.Updated “Packaging Information” on page 11.5.Updated “Errata” on page 14.1.Updated “Features” on page 1.2.Updated “Alternate Functions of Port B” on page 53.3.Updated “Calibration Byte” on page 161.16ATtiny2313/V2543IS–AVR–04/06Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03Changes from Rev. 2514A-09/03 to Rev. 2514B-09/034.Moved Table 69 on page 161 and Table 70 on page 162 to “Page Size”on page 161.5.Updated “Enter Programming Mode” on page 164.6.Updated “Serial Programming Algorithm” on page 174.7.Updated Table 78 on page 175.8.Updated “DC Characteristics” on page 178.9.Updated “ATtiny2313 Typical Characteristics” on page 182.10.Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE and EEWE to EEPE in the document.1.Speed Grades changed - 12MHz to 10MHz - 24MHz to 20MHz2.Updated Figure 1 on page 2.3.Updated “Ordering Information” on page 10.4.Updated “Maximum Speed vs. V CC ” on page 181.5.Updated “ATtiny2313 Typical Characteristics” on page 182.1.Updated Table 2 on page 22.2.Replaced “Watchdog Timer” on page 39.3.Added “Maximum Speed vs. V CC ” on page 181.4.“Serial Programming Algorithm” on page 174 updated.5.Changed mA to µA in preliminary Figure 136 on page 208.6.“Ordering Information” on page 10 updated. MLF package option removed7.Package drawing “20P3” on page 11 updated.8.Updated C-code examples.9.Renamed instances of SPMEN to SELFPRGEN, Self Programming Enable.1.Updated “Calibrated Internal RC Oscillator” on page 24.1.Fixed typo from UART to USART and updated Speed Grades and Power Consumption Estimates in “Features” on page 1.2.Updated “Pin Configurations” on page 2.3.Updated Table 15 on page 34 and Table 80 on page 180.4.Updated item 5 in “Serial Programming Algorithm” on page 174.5.Updated “Electrical Characteristics” on page 178.6.Updated Figure 82 on page 181 and added Figure 83 on page 181.7.Changed SFIOR to GTCCR in “Register Summary” on page 6.8.Updated “Ordering Information” on page 10.9.Added new errata in “Errata” on page 14.2543IS–AVR–04/06© Atmel Corporation 2006. All rights reserved. Atmel ®, logo and combinations thereof, Everywhere You Are ®, AVR ®, AVR Studio ®, and others,are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. 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Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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MAX3222/MAX3232/MAX3237/MAX32413.0V至5.5V、低功耗、1Mbps、真RS-232收发器，使用四只0.1µF外部电容________________________________________________________________Maxim Integrated Products119-0273; Rev 7; 1/07MegaBaud和UCSP是Maxim Integrated Products, Inc.的商标。

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M A X 3222/M A X 3232/M A X 3237/M A X 32413.0V至5.5V、低功耗、1Mbps、真RS-232收发器，使用四只0.1µF外部电容2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(V CC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Note 1:V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V.V CC ...........................................................................-0.3V to +6V V+ (Note 1)...............................................................-0.3V to +7V V- (Note 1)................................................................+0.3V to -7V V+ + V- (Note 1)...................................................................+13V Input VoltagesT_IN, SHDN , EN ...................................................-0.3V to +6V MBAUD...................................................-0.3V to (V CC + 0.3V)R_IN.................................................................................±25V Output VoltagesT_OUT...........................................................................±13.2V R_OUT....................................................-0.3V to (V CC + 0.3V)Short-Circuit DurationT_OUT....................................................................ContinuousContinuous Power Dissipation (T A = +70°C)16-Pin TSSOP (derate 6.7mW/°C above +70°C).............533mW 16-Pin Narrow SO (derate 8.70mW/°C above +70°C)....696mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C)........762mW 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)...842mW 18-Pin SO (derate 9.52mW/°C above +70°C)..............762mW 18-Pin Plastic DIP (derate 11.11mW/°C above +70°C)..889mW 20-Pin SSOP (derate 7.00mW/°C above +70°C).........559mW 20-Pin TSSOP (derate 8.0mW/°C above +70°C).............640mW 28-Pin TSSOP (derate 8.7mW/°C above +70°C).............696mW 28-Pin SSOP (derate 9.52mW/°C above +70°C).........762mW 28-Pin SO (derate 12.50mW/°C above +70°C).....................1W Operating Temperature RangesMAX32_ _C_ _.....................................................0°C to +70°C MAX32_ _E_ _ .................................................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX3222/MAX3232/MAX3237/MAX32413.0V至5.5V、低功耗、1Mbps、真RS-232收发器，使用四只0.1µF外部电容_______________________________________________________________________________________3TIMING CHARACTERISTICS—MAX3222/MAX3232/MAX3241(V CC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)ELECTRICAL CHARACTERISTICS (continued)(V CC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)A X 3222/M A X 3232/M A X 3237/M A X 32413.0V至5.5V、低功耗、1Mbps、真RS-232收发器，使用四只0.1µF外部电容4_______________________________________________________________________________________典型工作特性Ω, T A = +25°C, unless otherwise noted.)LOAD CAPACITANCE (pF)0246810121416182022150MAX3222/MAX3232SLEW RATEvs. LOAD CAPACITANCELOAD CAPACITANCE (pF)S L E W R A T E (V /µs )20003000100040005000510152025303540MAX3222/MAX3232SUPPLY CURRENT vs. LOAD CAPACITANCEWHEN TRANSMITTING DATALOAD CAPACITANCE (pF)S U P P L Y C U R R E N T (m A )20003000100040005000TIMING CHARACTERISTICS—MAX3237(V CC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)Note 2:MAX3222/MAX3232/MAX3241: C1–C4 = 0.1µF tested at 3.3V ±10%; C1 = 0.047µF, C2–C4 = 0.33µF tested at 5.0V ±10%.MAX3237: C1–C4 = 0.1µF tested at 3.3V ±5%; C1–C4 = 0.22µF tested at 3.3V ±10%; C1 = 0.047µF, C2–C4 = 0.33µF tested at 5.0V ±10%.Note 3:Transmitter input hysteresis is typically 250mV.MAX3222/MAX3232/MAX3237/MAX32413.0V至5.5V、低功耗、1Mbps、真RS-232收发器，使用四只0.1µF外部电容_______________________________________________________________________________________5-7.5-5.0-2.502.55.07.50MAX3241TRANSMITTER OUTPUT VOLTAGEvs. LOAD CAPACITANCELOAD CAPACITANCE (pF)T R A N S M I T T E R O U T P U T V O L T A G E (V )2000300010004000500046810121416182022240MAX3241SLEW RATEvs. LOAD CAPACITANCELOAD CAPACITANCE (pF)S L E W R A T E (V /µs )20003000100040005000510152025303545400MAX3241SUPPLY CURRENT vs. LOADCAPACITANCE WHEN TRANSMITTING DATALOAD CAPACITANCE (pF)S U P P L Y C U R R E N T (m A )20003000100040005000-7.5-5.0-2.502.55.07.50MAX3237TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = GND)LOAD CAPACITANCE (pF)T R A N S M I T T E R O U T P U T V O L T A G E (V )200030001000400050000102030504060700MAX3237SLEW RATE vs. LOAD CAPACITANCE(MBAUD = V CC )LOAD CAPACITANCE (pF)S L E W R A T E (V /µs )500100015002000-7.5-5.0-2.502.55.07.50MAX3237TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = V CC )LOAD CAPACITANCE (pF)T R A N S M I T T E R O U T P U T V O L T A G E (V )5001000150020001020304050600MAX3237SUPPLY CURRENT vs.LOAD CAPACITANCE (MBAUD = GND)LOAD CAPACITANCE (pF)S U P P L Y C U R R E N T (m A )200030001000400050000246810120MAX3237SLEW RATE vs. LOAD CAPACITANCE(MBAUD = GND)LOAD CAPACITANCE (pF)S L E W R A T E (V /µs )2000300010004000500010302040506070MAX3237SKEW vs. LOAD CAPACITANCE(t PLH - t PHL )LOAD CAPACITANCE (pF)1000150050020002500____________________________________________________________________典型工作特性(续)(V CC = +3.3V, 235kbps data rate, 0.1µF capacitors, all transmitters loaded with 3k Ω, T A = +25°C, unless otherwise noted.)M A X 3222/M A X 3232/M A X 3237/M A X 32413.0V至5.5V、低功耗、1Mbps、真RS-232收发器，使用四只0.1µF外部电容6_________________________________________________________________________________________________________________________________________________________________引脚说明MAX3222/MAX3232/MAX3237/MAX32413.0V至5.5V、低功耗、1Mbps、真RS-232收发器，使用四只0.1µF外部电容_______________________________________________________________________________________7_______________________________详细说明双电荷泵电压转换器MAX3222/MAX3232/MAX3237/MAX3241的内部电源由两路稳压型电荷泵组成，只要输入电压(V CC )在3.0V至5.5V范围以内，即可提供+5.5V (倍压电荷泵)和-5.5V (反相电荷泵)输出电压。