SiT1533-datasheet温补PDF

iP1203PbF Power BlockDescriptionThe iP1203PbF is a fully optimized solution for medium current synchronous buck applications requiring up to 15A. It includes full function PWM control, with optimized power semiconductor chipsets and associated passives, achieving high power density. Very few external components are required to create a complete synchronous buck power supply.iPOWIR ™ technology offers designers an innovative space-saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection.• 5.5V to 13.2V Input Voltage •0.8V to 8V Output Voltage • 15A Maximum Load Capability•200-400kHz Nominal Switching Frequency •Over Current Hiccup•External Synchronization Capable •Overvoltage Protection•Over Temperature Protection•Internal Features Minimize Layout Sensitivity •Very Small Outline 9mm x 9mm x 2.3mmFeaturesSingle Output Full Function Synchronous Buck Power BlockIntegrated Power Semiconductors,PWM Control & PassivesiP1203PbFPD- 97108iP1203PbFAbsolute Maximum RatingsRecommended Operating ConditionsElectrical Specifications @ V IN = 12VAll specifications @ 25°C (unless otherwise specified)iP1203PbF Electrical Specifications (continued)iP1203PbF ArrayFig. 1:iP1203PbF Internal Block DiagramiP1203PbFFig. 2: Power Loss vs. Current0102030405060708090100110120130Case Temperature (°C)102030405060708090100110120130PCB Temperature (°C)0246810121416O u t p u t C u r r e n t (A )Tx51015Output Current (A)0123456P o w e r L o s s (W )iP1203PbFFig. 6: Normalized Power Loss vs. FrequencyFig. 4: Normalized Power Loss vs. V INFig. 5: Normalized Power Loss vs. V OUTTypical Performance CurvesFig. 7: Normalized Power Loss vs. Inductance0.40.81.21.62.0 2.4Output Inductance (µH)0.961.001.041.081.121.161.201.24P o w e r L o s s (N o r m a l i z e d )-1.00.01.02.03.04.05.06.0SOA Temp Adju stment (°C)Fig. 8: Nominal Overcurrent Threshold Setting200250300350400Swiching Frequency (kHz)0.9601.0001.0401.0801.120P o w e r L o s s (N o r m a l i z e d )-0.50.00.51.01.5SOA Temp Adju stment (°C)681012141618202224Overload Current (A)525456585105125145165185205ROC-SET (kO hms) for 5.5Vin510152025303540455055R O C -S E T (k O h m s ) f o r 12V i n20253035404550R T (kOhms)200220240260280300320340360380400S w i t c h i n g F r e q u e n c y (k H z )0.81.62.43.24.04.85.66.47.28.0Output Voltage (V)0.920.961.001.041.081.121.161.201.241.281.321.36P o w e r L o s s (N o r m a l i z e d )-2-1012345678910SOA Temp Adjustment (°C)567891011121314Input Voltage (V)0.960.981.001.021.041.06P o w e r L o s s (N o r m a l i z e d )-1.0-0.50.00.51.01.5SOA Temp Adjustment (°C)iP1203PbFAdjusting the Power Loss and SOA Curves for Different Operating ConditionsTo make adjustments to the power loss curves in Fig. 2, multiply the normalized value obtained from the curves in Figs. 4,5, 6 or 7 by the value indicated on the power loss curve in Fig. 2. Then if multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 2. The resulting product is the final power loss based on all factors. See example no. 1.To make adjustments to the SOA curve in Fig. 3, determine your maximum PCB Temp & Case Temp at the maximum operating current of each iP1203PbF . Then, add the correction temperature from the normalized curves in Figs. 4, 5, 6 or 7 to the T X axis intercept (see procedure no. 2 above) in Fig. 3. When multiple adjustments are required, add all of the temperatures together, then add the sum to the T X axis intercept in Fig. 3. See example no. 2.Operating Conditions for the following examples:Output Current = 12A Input Voltage = 13.2V Inductor = 0.6µHOutput Voltage = 1.2VSw Freq= 400kHzExample 1) Adjusting for Maximum Power Loss:(Fig. 2)Maximum power loss = 4.1W(Fig. 4)Normalized power loss for input voltage ≈ 1.025(Fig. 5)Normalized power loss for output voltage ≈ 0.97(Fig. 6)Normalized power loss for frequency ≈ 1.08(Fig. 7)Normalized power loss for inductor value ≈ 1.08Adjusted Power Loss = 4.1 x 1.025 x 0.97 x 1.08 x 1.08 ≈ 4.75WApplying the Safe Operating Area (SOA) CurveThe SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn out through the printed circuit board and the top of the case.Procedure1)Draw a line from Case Temp axis at T CASE to the PCBTemp axis at T PCB .2)Draw a vertical line from the T X axis intercept to the SOAcurve. (see AN-1047 for further explanation of T X )3)Draw a horizontal line from the intersection of the verticalline with the SOA curve to the Y axis. The point at which the horizontal line meets the y-axis is the SOA current.4)If no top sided heatsinking is available, assume T CASEtemperature of 125°C for worst case performance.120102030405060708090100110102030405060708090100110120PCB Temperature (ºC)O u t p u t C u r r e n t (A )Case Temperature (ºC)iP1203PbFExample 2) Adjusting for SOA Temperature:Assuming T CASE = 110°C & T PCB = 90°C for both outputsOutput1(Fig. 4)Normalized SOA Temperature for input voltage ≈ +0.7°C(Fig. 5)Normalized SOA Temperature for output voltage ≈ -0.75°C (Fig. 6)Normalized SOA Temperature for frequency ≈ +1.0°C (Fig. 7)Normalized SOA Temperature for inductor value ≈ +2.0°CT X axis intercept temp adjustment = +0.5°C - 0.75°C + 1.0°C +2.0°C ≈ +2.75°CThe following example shows how the SOA current is adjusted for a T X change of +2.75°C and output is in SOAFig. 10: Power Loss Test Circuit120102030405060708090100110102030405060708090100110120PCB Temperature (ºC)O u t p u t C u r r e n t (A )Case Temperature (ºC)TXFig. 11: Recommended PCB Footprint (Top View)iP1203PbFThe operating switching frequency (f SW ) range of iP1203PbF is 200 kHz to 400 kHz. The desired fre-quency is set by placing an external resistor to the R T pin of the iP1203PbF . See Fig. 9 for the proper resistor value.The iP1203PbF is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge clock. The free run-ning oscillator frequency is twice the switching fre-quency. During synchronization, R T is selected such that the free running frequency is 20% below the synchronization frequency. The maximum synchro-nization frequency that iP1203PbF can accept is 800kHz. Note that the actual switching frequency is half the synchronization frequency.iP1203PbF User s Design GuidelinesThe iP1203PbF is a single output 15A power block consisting of optimized power semiconductors, PWM control and its associated passive components. It is based on a synchronous buck topology and offers an optimized solution where space, efficiency and noise caused by parasitics are of concern. The power block operates with fixed frequency voltage mode control. The iP1203PbF components are integrated in a land grid array (LGA) package.V IN / Enabling the OutputThe input operating voltage range of the iP1203PbF is 5.5V to 13.2V.The iP1203PbF output is turned on upon application of input voltage. The V IN slew rate should not exceed 50mV/µs. The converter can also be turned on and off by releasing or pulling the SS pin low through a logic level MOSFET, the drain of which connects to the soft start pin (see Fig.12). This feature can be useful if sequencing or different start-up timing of dif-ferent system outputs are required. In situations where the output has undergone a latched shutdown due to overvoltage, cycling Vin will reset the output. Cycling soft start pin will not unlatch the output.Soft StartThe Soft Start function provides a controlled rise of the output voltage, thus limiting the inrush current.The soft start function has an internal 25µA +/-20%current source that charges the external soft start capacitor C ss up to 3V. During power-up, the output voltage starts ramping up only after the charging volt-age across the C ss capacitor has reached a 0.8Vtyp threshold, as shown in Fig. 13.Fig. 13: Power Up Threshold3V0.8VtypV Css V OUTFig.12: Soft Start/Enable CircuitFrequency and SynchronizationOvercurrent Protection HICCUPThe overcurrent protection function of the iP1203PbF offers a hiccup feature. During overloads, when the overcurrent trip threshold is reached, the power sup-ply output shuts down and attempts to restart (out-put HICCUP mode). The time duration between the shutdown of the output and the restart is determined by the time it takes to discharge the soft start ca-pacitor. Typically, the discharge time of the soft start capacitor is 10 times the charge time. The duty cycle of the hiccup process is typically 5%. The output will stay in hiccup indefinitely until the overload is re-moved. The typical overcurrent trip threshold of the device is internally set at 30A. The overcurrent shut-down / HICCUP threshold is about ±30% accurate.The iP1203PbF overcurrent shutdown and HICCUP threshold can be set externally by adding R OCSET re-sistor from OCSET pin. Refer to Fig.8 for R OCSET se-lection.Overvoltage Protection (OVP)Overvoltage is sensed through output voltage sense pin FB s . The OVP threshold is set to 115% of the output voltage. Upon overvoltage condition, the OVP forces a latched shutdown. In this mode, the upper FET turns off and the lower FET turns on, thus crowbaring the output. Reset is performed by recy-cling the input voltage. Overvoltage can be sensed by either connecting FB s to its corresponding output through a separate output voltage divider resistor network, or it can be connected directly to its corre-sponding feedback pin FB. For Type III control loop compensation, FB s should be connected through voltage dividers only.Refer to the iP1203PbF Design Procedure section on how to set the OVP trip threshold.PGOODThis is an output voltage status signal that is open collector and is pulled low when the output voltage falls below 85% of the output voltage. High state in-dicates that outputs are in regulation. The PGOOD pin can be left floating if not used.Thermal ShutdownThe iP1203PbF provides thermal shutdown. The threshold typically is set to 140°C. When the trip threshold is exceeded, thermal shutdown turns the output off. Thermal shutdown is not latched and au-tomatic restart is initiated when the sensed tempera-ture drops to the normal range.Only a few external components are required to com-plete a dual output synchronous buck power supply using iP1203PbF. The following procedure will guide the designer through the design and selection pro-cess of these external components.A typical application for the iP1203 is:V IN = 12V, V OUT = 1.5V, I OUT = 15A, f sw = 300kHz, V p-p == 50mVSetting the Output VoltageThe output voltage of the iP1203PbF is set by the 0.8V reference Vand external voltage dividers.Fig. 14: Typical Scheme for Output Voltage Setting V OUT is set according to equation (1):V OUT = V REF x (1 + R 2 /R 5 ) (see Fig. 14)(1)Setting R 2 to 1K, V OUT to 1.5V and V REF to 0.8V, will result in R 5= 1.14 Kohms. Final values can be se-lected according to the desired accuracy of the out-put.To set the output voltage for Type III compensation,refer to equation (24) in Type III compensation sec-tion.iP1203PbF Design ProcedureSetting the Overvoltage TripThe output of the iP1203 will shut down if it experi-ences a voltage in the range of 115% of V OUT . The overvoltage sense pin FB s is connected to the out-put through voltage dividers, R26 and R27 (Fig. 14),and the trip setpoint is programmed according to equation (1). A separate overvoltage sense pin FB s is provided to protect the power supply output if for some reason the main feedback loop is lost (for in-stance, loss of feedback resistors). An optional 100pF capacitor (C14) is used for delay and filtering.If this redundancy is not required and if a Type II con-trol loop compensation scheme is utilized, FB s pin can be connected to FB.Selecting the Soft-Start CapacitorThe soft start capacitor C ss is selected according to equation (2):t ss = 40 x C ss(2)where,t ss is the output voltage ramp time in milliseconds,and C ss is the soft start capacitor in µF.A 0.1µF capacitor will provide an output voltage ramp-up time of about 4ms.Input Capacitor SelectionThe switching currents impose RMS current require-ments on the input capacitors. Equation (3) allows the selection of the input capacitors.where, I out is the output current, and D is the duty cycle and is expressed as:D = V OUT / V IN .For the above example D= 0.13 and, using equation (3) the capacitor rms current yields 5.0A.For Type II compensation,(3))1(D D I I out RMS −=For better efficiency and low input ripple, select low ESR ceramic capacitors. The amount of the capaci-tors is determined based on the rms rating. In the above example, a total of 3 x 22µF, 2A capacitors will be required to support the input rms current.Output Capacitor C O SelectionSelection of the output capacitors depends on two factors:a. Low effective ESR for ripple and load transient re-quirementsTo support the load transients and to stay within a specified voltage dip ∆V due to the transients, ESR selection should satisfy equation (4):R ESR ≤ ∆V / I Loadmax(4)Where,I Loadmax is the maximum load current.If output voltage ripple is required to be maintained at specified levels then the expression in equation (5) should be used to select the output capacitors.R ESR ≤ V p-p / I ripple(5)Where,V p-p is the peak to peak output ripple voltage .I ripple is the inductor peak-to peak ripple current.In addition, the voltage ripple caused by the output capacitor needs to be significantly smaller than the ripple caused by the ESR of the capacitor. Use equa-tion (6) to satisfy this requirement.If the inductor current ripple I ripple is 30% of I OUT1, the 50mV peak to peak output voltage ripple requirement will be met if the total ESR of the output capacitors is less than 11m Ω. This will require 2 x 470µF POSCAP capacitors. Additional ceramic capacitors can be added in parallel to further reduce the ESR. Care should be given to properly compensate the control loop for low output capacitor ESR values.When selecting output capacitors, it is important to consider the overshoot performance of the power sup-ply. If the amount of capacitance is not adequate, then,when unloading the output, the magnitude of the over-shoot due to stored inductor energy, and depending on the speed of the response of the control loop, can exceed the overvoltage trip threshold of the iP1203PbF and can cause undesirable shutdown of the output. The magnitude of the overshoot should be kept below 1.125V OUT . To prevent the overshoot from tripping the output a delay can be added by in-stalling capacitor C14 as shown in Fig.14.b. StabilityThe value of the output capacitor ESR zero frequency f esr plays a major role in determining stability. f esr is calculated by the expression in equation (7).f ESR = 1 / (2 π x R ESR x C O )(7)Details on how to consider this parameter to design for stability are outlined in the control loop compen-sation section of this datasheet.Inductor L O SelectionInductor selection is based on trade-offs between size and efficiency. Low inductor values result in smaller sizes, but can cause large ripple currents and lower efficiency. Low inductor values also benefit the tran-sient performance.The inductor L o is selected according to equation (8):L O = V out x (1 - D) / (f sw x I ripple )(8)For the above example, and for I ripple of 30% of I OUT , L O is calculated to be 1.0µH.The core must be selected according to the peak of maximum output current.(6)ESRs o R f C ××>π210Control Loop CompensationThe iP1203PbF feedback control is based on single loop voltage mode control principle.The goal in the design of the compensator is to achieve the highest unity gain (0 db) crossover fre-quency with sufficient phase margin for the closed loop transfer function. The LC filter of the power sup-ply introduces a double pole with 40db/dec slope and 180° phase lag. The 180° phase contribution from the LC filter is the source of instabilty.The resonant frequency of the LC filter is expressed by equation (9):(9)The error amplifier of the iP1203PbF PWM controlleris transconductance amplifier, and its output is avail-able for external compensation.Two types of compensators are studied in this sec-tion. The first one is called Type II and it is used to compensate systems the ESR frequency f esr (equa-tion 7) of which is in the midfrequency range and Type III that can be used for any type of output capacitors and have a wide range of f esr .For output voltage settings less than 1.0V that use low ESR ceramic capacitors, it is recommended that the unity gain crossover frequency be set around 20kHz to maintain stable operation.where, g m is the transconductance of the error am-plifier.(12)Follow the steps below to determine the feedback loop compensation component values:1. Select a zero db crossover frequency f 0 in the range of 10% to 20% of the switching frequency f sw.)(2 / 1 00C L f LC ×=πType IIFrom Fig.15 the transfer function H(s) of the error amplifier is given by (10):(10)The term s represents the frequency dependence ofthe transfer function.The Type II controller introduces a gain and a zero expressed by equations (11) and (12):9199192551)(C sR C sR R R R g s H m +×+×=91921C R f z ××=πFig. 15: Typical Type II Compensation and its Gain Plot(11)19255)(R R R R g s H m ×+×=3. Place a zero at 75% of f LC to cancel one of the LC filter poles.oo z C L f ××=π2175.04. Calculate C 9 using equations (12) and (14)Calculation of the compensation components based on the example above, yields:f LC = 5.0kHz f z = 3.8kHzf 0 = 45kHz (15% of 300kHz)f esr = 14kHz, per equation (7) using R esr = 12m Ω.R 19 = 2.49K C 9 = 18nFSometimes, a pole f p2 is added at half the switching frequency to filter the switching noise. This is done by adding a capacitor C opt in Fig.15 from the output of the error amplifier (CC pin of iP1203PbF) to ground.This pole is given by equation (15):C opt is found from equation (16) by rearranging the terms in equation (15) and by setting f p2 = f sw / 2:(16)Fig. 16: Typical Type III Compensation and its Gain PlotType IIIThe Type III compensation scheme allows the use of any type of capacitors with ESR frequency of any range. This scheme suggests a double pole double zero compensation and requires more components around the error amplifier to achieve the desired gain and phase margins. Fig. 13 represents the Type III compensation network for iP1203PbF.The transfer function of the Type III compensator is given by equation (17)2. Calculate R 5 using equation (13):Where,V IN = Maximum input voltagef 0 = Error amplifier zero crossover frequency f esr = Output capacitor C o zero frequency f LC = Output frequency resonant filterg m = Error amplifier transconductance. Use 2mS for g m .V ramp = Oscillator ramp voltage. Use 1.25V for V ramp(14)(13)(15)optp C R f ××=19221π19221R f C p opt ××=π)1()1()1()1(1)(8217208292092C sR C sR C sR C sR C sR s H +×++×+×=(17)mLC esr in ramp g R R R f f f V V R 115252019×+××××=R 210Vref V o- VrefMore than one iteration may be required to calculate the values of the compensation components if cross-over frequencies higher than the range specified in step 1 are required (for higher bandwidths and faster transient response performance). To ensure stability a phase margin greater than 45° should be achieved.Refer to AN-1043 for more detailed compensation techniques using Transconductance Amplifiers.7. Place the second pole f p2 at or near f esr of the out-put capacitor C o and determine the value of R 21 fromequation (19). Make sure R 21 <8. Use equation (24) to calculate R 5.R 5 = R 2 x (24)The crossover frequency f 0 for Type III compensa-tion is represented by equation (23):Follow the steps below to determine the feedback loop compensation component values:1. Select a zero db crossover frequency f 0 in the range of 10% to 20% of the switching frequency f sw.2. Select R 20~ 10k Ω3. Place the first zero f z1 at 75% of the resonant fre-quency f LC of the output filter.Determine C 9 from equation (21).4. Place a third pole f P3 at or near the switching fre-quency f SW .Select C7 such that C 7 <5. Calculate C 8 from equation (23).6. Place the second zero at 125% of the resonant frequency f LC of the output filter. Calculate R 2 using equation (22).109C The frequencies of the three poles and the two zeros of the Type III compensation scheme are represented by the following equations:f p1= 0(18)(19)(21)(20)821221C R f p ××=π720321C R f p ××=π920121C R f z ××=π82221C R f z ××=π008200211C L C R V V f IN ramp××××××=π(22)(23)Typical WaveformsCh1: Switching node, 400kHzCh2: 800kHz external synchronizationFig. 17: iP1203PbF Outputs Synchronized to800kHz Ch1: Output voltage, 500mV/divCh3: Output current, 10A/divFig. 18: iP1203PbF Output Hiccup, Due to Over-loadCh1: Output voltage, 100mV/div acCh3: Load current, 5A/divFig. 19: iP1203PbF Transient Response Load Step 1A to 12A Ch1: Output voltage, 100mV/div acCh3: Load current, 5A/divFig. 20: iP1203PbF Transient Response Load Step12A to 0ACh1: FB s input, 200mV/divCh2: Output voltage, 1V/divFig. 21: iP1203PbF Overvoltage Trip. Output Voltage Turns Off When Voltage at FB s Pin Exceeds 15% of FB (0.8V)For stable and noise free operation of the whole power system, it is recommended that the design-ers use the following guidelines:1. Follow the layout scheme presented in Fig. 23. Make sure that the output inductor L is placed as close to iP1203PbF as possible to prevent noise propagation that can be caused by switching of power at the switching node Vsw, to sensitive cir-cuits.2. Provide a mid-layer solid ground plane with con-nections to the top layer through vias. The PGND pads of iP1203PbF also need to be connected to the same ground plane through vias.3. To increase power supply noise immunity, place input and output capacitors close to one another, as shown in the layout diagram. This will provide short high current paths that are essential at the ground terminals.4. Although there is a certain degree of VIN bypass-ing inside the iP1203PbF, the external input decoupling capacitors should be as close to the device as pos-sible.5. The feedback track from the output VOUTto FB should be routed as far away from noise generating traces as possible.6. The compensation components and the Vref by-pass capacitor should be placed as close as pos-sible to their corresponding iP1203PbF pins, away from noise generating traces.7. Refer to IR application note AN-1029 (Optimizinga PCB Layout for an iPOWIR Technology Design) to determine what size vias and copper weight and thickness to use when designing the PCB.8. Place the overcurrent threshold setting resistors ROCSETclose to the iP1203PbF block at the corre-sponding connection node.Layout GuidelinesFig. 24: Typical Application Schematic 21This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions.AN-1030: Applying iPOWIR Products in Your Thermal EnvironmentThis paper explains how to use the Power Loss vs Current and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.AN-1043: Stabilize the Buck Converter with Transconductance AmplifierThis paper explains how to stabilize a buck converter for Type II and Type III control loop compensation using transconductance amplifiers.AN-1047: Graphical solution to two branch heatsinking Safe Operating AreaThis paper is a suppliment to AN-1030 and explains how to use the double side Power Loss vs Current and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier s iPOWIR Technology BGA and LGA PackagesThis paper discusses optimization of the layout design for mounting iPOWIR BGA and LGA packages on printed circuit boards, accounting for thermal and electrical performance and assembly considerations.Topics discussed includes PCB layout placement, routing, and via interconnect suggestions, as well as soldering, pick and place, reflow, cleaning and reworking recommendations.芯天下--/22iP1203PbFFig. 27: Part Marking芯天下--/ 23This product has been designed and qualified for the industrial market.IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105TAC Fax: (310) 252-7903Visit us at for sales contact information .Data and specifications subject to change without notice.8/06Fig.28: Recommended Solder Profile and Stencil Design芯天下--/。

TMFEATURESAPPLICATIONSDESCRIPTIONTHD+N–TotalHarmonicDistortion+Noise–%1070G0120.010.12010.110P O – Output Power – W1TAS5186ASLES156–OCTOBER2005 6-Channel,210-W,Digital-Amplifier Power StageThe TAS5186A requires only simple passivedemodulation filters on its outputs to deliver •Total Output Power@10%THD+Nhigh-quality,high-efficiency audio amplification.The –5×30W@6Ω+1×60W@3Ωdevice efficiency of the TAS5186A is greater than90%when driving6-Ωsatellites and a3-Ωsubwoofer •105-dB SNR(A-Weighted)speaker.•0.07%THD+N@1WThe TAS5186A has an innovative protection system •Power Stage Efficiency>90%Intointegrated on-chip,safeguarding the device against a Recommended Loads(SE)wide range of fault conditions that could damage the •Integrated Self-Protection Circuits system.These safeguards are short-circuit protection,–Undervoltage overload protection,undervoltage protection,andovertemperature protection.The TAS5186A has a –Overtemperaturenew proprietary current-limiting circuit that reduces –Overloadthe possibility of device shutdown during high-level –Short Circuit music transients.A new programmable overcurrentdetector allows the use of lower-cost inductors in the •Integrated Active-Bias Control to Avoid DCdemodulation output filter.Pop•Thermally Enhanced44-Pin HTSSOP Package TOTAL HARMONIC DISTORTION+NOISEvs•EMI-Compliant When Used WithOUTPUT POWER Recommended System Design•DVD Receiver•Home Theater in a BoxThe TAS5186A is a high-performance,six-channel,digital-amplifier power stage with an improvedprotection system.The TAS5186A is capable ofdriving a6-Ω,s ingle­ended load up to30W per eachfront/satellite channel and a3-Ω,single-endedsubwoofer greater than60W at10%THD+Nperformance.A low-cost,high-fidelity audio system can be builtusing a TI chipset comprising a modulator(e.g.,TAS5086)and the TAS5186A.This device does notrequire power-up sequencing because of the internalpower-on reset.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©2005,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.DDV PACKAGE (TOP VIEW)P0016-03TAS5186ASLES156–OCTOBER 2005These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.The TAS5186A is available in a thermally enhanced 44-pin HTSSOP PowerPAD™package.The heat slug is located on the top side of the device for convenient thermal coupling to a heatsink.2TAS5186ASLES156–OCTOBER 2005GENERAL INFORMATION (continued)TERMINAL FUNCTIONSTERMINAL TYPE (1)DESCRIPTIONNAME NO.AGND 12P Analog groundBST_A 23P HS bootstrap supply (BST),capacitor to OUT_A required BST_B 29P HS bootstrap supply (BST),external capacitor to OUT_B required BST_BIAS 21P BIAS bootstrap supply,external capacitor to OUT_BIAS required BST_C 30P HS bootstrap supply (BST),external capacitor to OUT_C required BST_D 37P HS bootstrap supply (BST),external capacitor to OUT_D required BST_E 38P HS bootstrap supply (BST),external capacitor to OUT_E required BST_F 44P HS bootstrap supply (BST),external capacitor to OUT_F required GND 11P Chip groundGVDD_ABC 20P Gate drive voltage supply GVDD_DEF 3P Gate drive voltage supply M110I Mode selection pin M29I Mode selection pin M38I Mode selection pinOC_ADJ 14O Overcurrent threshold programming pin,resistor to ground required OTW 16O Overtemperature warning open-drain output signal,active-low OUT_A 25O Output,half-bridge A,satellite OUT_B 27O Output,half-bridge B,satellite OUT_BIAS 22O BIAS half-bridge output pin OUT_C 32O Output,half-bridge C,subwoofer OUT_D 35O Output,half-bridge D,satellite OUT_E 40O Output,half-bridge E,satellite OUT_F42OOutput,half-bridge F,satellite1,26,PGND 33,P Power ground34,41PVDD_A 24P Power-supply input for half-bridge A PVDD_B 28P Power-supply input for half-bridge B PVDD_C 31P Power-supply input for half-bridge C PVDD_D 36P Power-supply input for half-bridge D PVDD_E 39P Power-supply input for half-bridge E PVDD_F 43P Power-supply input for half-bridge F PWM_A 19I PWM input signal for half-bridge A PWM_B 18I PWM input signal for half-bridge B PWM_C 17I PWM input signal for half-bridge C PWM_D 6I PWM input signal for half-bridge D PWM_E 5I PWM input signal for half-bridge E PWM_F 2I PWM input signal for half-bridge F RESET 7I Reset signal (active-low logic)SD 15O Shutdown open-drain output signal,active-low VDD 4P Power supply for digital voltage regulator VREG 13ODigital regulator supply filter pin,output(1)I =input;O =output;P =power3PACKAGE HEAT DISSIPATION RATINGS (1)ABSOLUTE MAXIMUM RATINGSTAS5186ASLES156–OCTOBER 2005Table 1.MODE Selection PinsMODE PINS (1)MODEM2M3NAMEDESCRIPTION00 2.1mode Channels A,B,and C enabled;channels D,E,and F disabled01 5.1mode All channels enabled10/1Reserved(1)M1must always be connected to GND.0indicates a pin connected to GND;1indicates a pin connected to VREG.PARAMETERTAS5186ADDVR θJC (°C/W)—1satellite (sat.)FET only 10.3R θJC (°C/W)—1subwoofer (sub.)FET only5.2R θJC (°C/W)—1sat.half-bridge 5.2R θJC (°C/W)—1sub.half-bridge 2.6R θJC (°C/W)—5sat.half-bridges +1sub.1.74Typical pad area (2)34.9mm 2(1)JC is junction-to-case,CH is case-to-heatsink.(2)R θCH is an important consideration.Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink.The R θCH with this condition is typically 2°C/W for this package.over operating free-air temperature range (unless otherwise noted)(1)TAS5186AVDD to AGND –0.3V to 13.2V GVDD_X to AGND –0.3V to 13.2V PVDD_X to PGND_X (2)–0.3V to 50V OUT_X to PGND_X (2)–0.3V to 50V BST_X to PGND_X (2)–0.3V to 63.2V VREG to AGND –0.3V to 4.2V PGND to GND –0.3V to 0.3V PGND to AGND –0.3V to 0.3V GND to AGND–0.3V to 0.3V PWM_X,OC_ADJ,M1,M2,M3to AGND –0.3V to 4.2V RESET,SD,OTW to AGND–0.3V to 7V Maximum operating junction temperature range (T J )0to 125°C Storage temperature–40°C to 125°CLead temperature –1,6mm (1/16inch)from case for 10seconds 260°C Minimum PWM pulse duration,low 30ns(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)These voltages represent the dc voltage +peak ac waveform measured at the terminal of the device in all conditions.4M1M2RESETSD OTWAGND OC_ADJVREG VDDGVDD_DEF M3GNDPWM_FOUT_F PGND PVDD_FBST_FPWM_EOUT_E PGND PVDD_E BST_EPWM_DOUT_D PGND PVDD_D BST_DPWM_COUT_C PGND PVDD_C BST_CPWM_BOUT_B PGND PVDD_B BST_BPWM_AOUT_APVDD_A BST_AOUT_BIASBST_BIASB0034-03GVDD_ABC TAS5186ASLES156–OCTOBER 2005TYPICAL SYSTEM DIAGRAMA schematic diagram for a typical system is appended at the end of the data sheet.FUNCTIONAL BLOCK DIAGRAM5RECOMMENDED OPERATING CONDITIONSAUDIO SPECIFICATIONTAS5186ASLES156–OCTOBER 2005MINTYPMAX UNIT PVDD_X Half-bridge supply,SEDC supply voltage at pin(s)040V GVDD Gate drive and guard ring supply voltage DC voltage at pin(s)10.81213.2V VDD Digital regulator supply DC supply voltage at pin 10.81213.2V Any value of R PU,EXT within VPU Pullup voltage supply35 5.5V recommended rangeResistive load impedance,satellite Recommended demodulation filter R L,SAT 46Ωchannels (1)Resistive load impedance,subwoofer Recommended demodulation filter R L,SUB 2.253ΩchannelMinimum output inductance under L output Demodulation filter inductance 522µH short-circuit conditionC output,sat Demodulation filter capacitance 1µF C output,sub Demodulation filter capacitance 1µF F PWM PWM frame rate192384432kHz(1)Load impedance outside range listed might cause shutdown due to OLP,OTE,or NLP.PVDD_X =40V,GVDD =12V,audio frequency =1kHz,AES17measurement filter,F PWM =384kHz,case temperature =75°C.Audio performance is recorded as a chipset,using TAS5086PWM processor with an effective modulation index limit of 97%.All performance is in accordance with the foregoing specifications and recommended operating conditions unless otherwise specified.PARAMETERCONDITIONSMINTYP MAXUNITR L =6Ω,10%THD,clipped input signal30R L =8Ω,10%THD,clipped input signal 25P O,satPower output per satellite channelWR L =6Ω,0dBFS,unclipped input signal 25R L =8Ω,0dBFS,unclipped input signal 20R L =3Ω,10%THD,clipped input signal60R L =4Ω,10%THD,clipped input signal 52P O,subPower output,subwooferW R L =3Ω,0dBFS,unclipped input signal 50R L =4Ω,0dBFS,unclipped input signal40R L =6Ω,P O =25W 0.3%Total harmonic distortion +noise,satelliteR L =6Ω,1W 0.07%THD +NR L =3Ω,P O =50W 0.5%Total harmonic distortion +noise,subwooferR L =3Ω,1W 0.05%Output integrated noise,satellite A-weighted 55V n µV Output integrated noise,subwoofer A-weighted 60SNR System signal-to-noise ratio A-weighted105dB Dynamic range (1)A-weighted,–60dBFS input signal,105DNRdB measured with TAS5086PWM processor P O =0W,all channels running 5.1mode (2).22-µH Kwang-Sung inductors (see 4.5W Power dissipation due to idle losses schematic for information)P idle(IPVDDX)P O =0W,2.1mode.22-µH Kwang-Sung 2.2W inductors (see schematic for information)(1)SNR is calculated relative to 0-dBFS input level.(2)Actual system idle losses are affected by core losses of output inductors.6ELECTRICAL CHARACTERISTICSTAS5186ASLES156–OCTOBER 2005F PWM =384kHz,GVDD =12V,VDD =12V,T C (case temperature)=75°C,unless otherwise noted.All performance is in accordance with recommended operating conditions,unless otherwise specified.SYMBOL PARAMETERCONDITIONSMIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR ANDCURRENT CONSUMPTIONVREG Voltage regulator,only used as reference node VDD =12V33.3 3.6V Operating,50%duty cycle 720IVDD VDD supply currentmA Idle,reset mode 61650%duty cycle 522IGVDD_XGate supply current per half-bridgemAIdle,reset mode1350%duty cycle,without output filter or load,5.1110mode.22-µH Kwang-Sung inductorsIPVDD_X Half-bridge idle currentmA50%duty cycle,without output filter or load,2.160mode.22-µH Kwang-Sung inductors OUTPUT STAGE MOSFETs R DSon ,LS Sat Drain-to-source resistance,low side,satellite T J =25°C,includes metallization resistance 210m ΩR DSon ,HS Sat Drain-to-source resistance,high side,satellite T J =25°C,includes metallization resistance 210m ΩR Dson ,LS Sub Drain-to-source resistance,low side,subwoofer T J =25°C,includes metallization resistance 110m ΩR Dson ,HS Sub Drain-to-source resistance,high side,subwooferT J =25°C,includes metallization resistance110m ΩI/O PROTECTION V UVP,G Undervoltage protection limit GVDD_X 10V V UVP,hyst (1)Undervoltage protection hysteresis 250mV OTW (1)Overtemperature warning125°C Temperature drop needed below OTW temp.for OTW hyst (1)25°C OTW to be inactive after the OTW event OTE (1)Overtemperature error155°C Temperature drop needed below OTE temp.for SD OTE HYST (1)25°C to be released after the OTE event OLCP Overload protection counter 1.25ms Overcurrent limit protection,satellite Rocp =18k Ω 4.5A I OC Overcurrent limit protection,subwoofer Rocp =18k Ω8A I OCT Overcurrent response time 210ns Rocp OC programming resistor range Resistor tolerance =5%18k ΩSTATIC DIGITAL SPECIFICATIONV IH High-level input voltage 2PWM_X,M1,M2,M3,RESET V V IL Low-level input voltage 0.8I LEAKInput leakage currentStatic condition–8080µAOTW/SHUTDOWN (SD)Internal pullup resistor to DREG (3.3V)for SD and R INT_PU 26k ΩOTWInternal pullup resistor only3 3.33.6V OH High-level output voltage External pullup:4.7-k Ωresistor to 5V 4.55V V OL Low-level output voltage I O =4mA 0.20.4FANOUTDevice fanout OTW,SDNo external pullup30Devices (1)Specified by design.7TYPICAL CHARACTERISTICS,5.1MODET H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %1040G0010.010.12010.110P O – Output Power – W1T H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %1070G0020.010.12010.110P O – Output Power – W1PVDD – Supply Voltage – V 024681012141618202224262830323436P O – O u t p u t P o w e r – WG003PVDD – Supply Voltage – V510152025303540455055606570G004P O – O u t p u t P o w e r – WTAS5186ASLES156–OCTOBER 2005TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsOUTPUT POWEROUTPUT POWERFigure 1.Figure 2.OUTPUT POWEROUTPUT POWERvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 3.Figure 4.8PVDD – Supply Voltage – V 0246810121416182022242628G005P O – O u t p u t P o w e r – WPVDD – Supply Voltage – V0510152025303540455055G006P O – O u t p u t P o w e r – W20406080100120140160180200220240S y s t e m E f f i c i e n c y – %G007P O – Total Output Power – W051015202530354020406080100120140160180200220240S y s t e m P o w e r L o s s – WG008P O – Total Output Power – WTAS5186ASLES156–OCTOBER 2005TYPICAL CHARACTERISTICS,5.1MODE (continued)OUTPUT POWEROUTPUT POWERvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 5.Figure 6.SYSTEM EFFICIENCYSYSTEM POWER LOSSvsvsTOTAL OUTPUT POWERTOTAL OUTPUT POWERFigure 7.Figure 8.9T C – Case Temperature – °C 0510********35402030405060708090100110G009P O – O u t p u t P o w e r – WT C – Case Temperature – °C010203040506070802030405060708090100110G010P O – O u t p u t P o w e r – Wf – Frequency – kHz−150−140−130−120−110−100−90−80−70−60−50−40−30−20−1000246810121416182022A m p l i t u d e – d BG011TAS5186ASLES156–OCTOBER 2005TYPICAL CHARACTERISTICS,5.1MODE (continued)OUTPUT POWEROUTPUT POWERvsvsCASE TEMPERATURECASE TEMPERATUREFigure 9.Figure 10.AMPLITUDEvsFREQUENCYFigure 11.10 THEORY OF OPERATIONPOWER SUPPLIESSYSTEM POWER-UP/DOWN SEQUENCE Powering Down Error Reporting TAS5186ASLES156–OCTOBER 2005reliability,it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin on the same To facilitate system design,the TAS5186A needsside of the PCB as the TAS5186A.It is only a 12-V supply in addition to a typical 39-Vrecommended to follow the PCB layout of the power-stage supply.An internal voltage regulatorTAS5186A reference design.For additional provides suitable voltage levels for the digital andinformation on the recommended power supply and low-voltage analog circuitry.Additionally,all circuitryrequired components,see the application diagrams requiring a floating voltage supply,e.g.,the high-sidegiven in this data sheet.The 12-V supply should be gate drive,is accommodated by built-in bootstrappowered from a low-noise,low-output-impedance circuitry requiring only a few external capacitors.voltage regulator.Likewise,the 39-V power-stage supply is assumed to have low output impedance and In order to provide outstanding electrical and acousticlow noise.The power-supply sequence is not critical characteristics,the PWM signal path including gatedue to the internal power-on-reset circuit.Moreover,drive and output stage is designed as identical,the TAS5186A is fully protected against erroneous independent half-bridges.For this reason,eachpower-stage turnon due to parasitic gate charging.half-bridge has separate bootstrap pins (BST_X)andThus,voltage-supply ramp rates (dv/dt)are typically power-stage supply pins (PVDD_X).Furthermore,annoncritical.additional pin (VDD)is provided as power supply forall common circuits.Although supplied from the same12-V source,it is highly recommended to separateGVDD_X and VDD on the printed-circuit board (PCB)The TAS5186A does not require a power-up by RC filters (see application diagram for details).sequence.The outputs of the H-bridge remain in a These RC filters provide the recommendedhigh-impedance state until the gate-drive supply high-frequency isolation.Special attention should bevoltage (GVDD_X)and VDD voltage are above the paid to placing all decoupling capacitors as close toundervoltage protection (UVP)voltage threshold (see their associated pins as possible.In general,the Electrical Characteristics section of this data inductance between the power-supply pins andsheet).Although not specifically required,it is decoupling capacitors must be avoided.(Seerecommended to hold RESET in a low state while reference board documentation for additionalpowering up the rmation.)When the TAS5186A is being used with TI PWM For a properly functioning bootstrap circuit,a smallmodulators such as the TAS5086,no special ceramic capacitor must be connected from eachattention to the state of RESET is required,provided bootstrap pin (BST_X)to the power-stage output pinthat the chipset is configured as recommended.(OUT_X).When the power-stage output is low,thebootstrap capacitor is charged through an internaldiode connected between the gate-drivepower-supply pin (GVDD_X)and the bootstrap pin.The TAS5186A does not require a power-down When the power-stage output voltage is high,thesequence.The device remains fully operational as bootstrap capacitor voltage is shifted above thelong as the gate-drive supply (GVDD_X)voltage and output voltage potential and thus provides a suitableVDD voltage are above the undervoltage protection voltage supply for the high-side gate driver.In an(UVP)threshold level (see the Electrical application with PWM switching frequencies in theCharacteristics section of this data sheet).Although range 352kHz to 384kHz,it is recommended to usenot specifically required,it is a good practice to hold 33-nF ceramic capacitors,size 0603or 0805,for theRESET low during power down,thus preventing bootstrap capacitor.These 33-nF capacitors ensureaudible artifacts including pops and clicks sufficient energy storage,even during minimal PWMWhen the TAS5186A is being used with TI PWM duty cycles,to keep the high-side power stage FETmodulators such as the TAS5086,no special (LDMOS)fully started during all of the remaining partattention to the state of RESET is required,provided of the PWM cycle.In an application running at athat the chipset is configured as recommended.reduced switching frequency,generally 250kHz to192kHz,the bootstrap capacitor might need to beincreased in value.Special attention should be paidto the power-stage power supply;this includesThe SD and OTW pins are both active-low,component selection,PCB placement and routing.Asopen-drain outputs.Their function is for indicated,each half-bridge has independentprotection-mode signaling to a PWM controller or power-stage supply pins (PVDD_X).For optimalother system-control device.electrical performance,EMI compliance,and systemDevice Protection SystemOVERCURRENT (OC)PROTECTION WITH TAS5186ASLES156–OCTOBER 2005Any fault resulting in device shutdown is signaled bytwo protection systems.The first protection system the SD pin going low.Likewise,OTW goes low whencontrols the power stage in order to prevent the the device junction temperature exceeds 125°C (seeoutput current from further increasing.i.e.,it performs the following table).a current-limiting function rather than prematurely shutting down during combinations of high-level music transients and extreme speaker SDOTW DESCRIPTION load-impedance drops.If the high-current situation persists,i.e.,the power stage is being overloaded,a 00Overtemperature (OTE)or overload (OLP)or undervoltage (UVP)second protection system triggers a latching shutdown,resulting in the power stage being set in 01Overload (OLP)or undervoltage (UVP)the high-impedance (Hi-Z)state.10Overtemperature warning.Junction temperature higher than 125°C,typical For added flexibility,the OC threshold is 11Normal operation.Junction temperature lower thanprogrammable within a limited range using a single 125°C,typical external resistor connected between the OC_ADJ pinand AGND.It should be noted that asserting RESET low forces OC-Adjust Resistor ValuesMaximum Peak Current Before the SD and OTW signals high independently of faults (k Ω)OC Occurs (A)being present.It is recommended to monitor the 18 4.5(sat.),8(sub.)OTW signal using the system microcontroller and torespond to an overtemperature warning signal by,It should be noted that a properly functioning e.g.,turning down the volume to prevent furtherovercurrent detector assumes the presence of a heating of the device that would result in deviceproperly designed demodulation filter at the shutdown (OTE).To reduce external componentpower-stage output.Short-circuit protection is not count,an internal pullup resistor to 3.3V is providedprovided directly at the output pins of the power stage on both the SD and OTW outputs.Level compliancebut only on the speaker terminals (after the for 5-V logic can be obtained by adding externaldemodulation filter).It is required to follow certain pullup resistors to 5V (see the Electricalguidelines when selecting the OC threshold and an Characteristics section of this data sheet for furtherappropriate demodulation inductor.specifications).•For the lowest-cost bill of materials in terms of component selection,the OC threshold current should be limited,considering the power output The TAS5186A contains advanced protection circuitryrequirement and minimum load impedance.carefully designed to facilitate system integration andHigher-impedance loads require a lower OC ease of use,as well as safeguarding the device fromthreshold.permanent failure due to a wide range of fault•The demodulation filter inductor must retain at conditions such as short circuit,overload,andleast 5µH of inductance at twice the OC undervoltage.The TAS5186A responds to a fault bythreshold setting.immediately setting the power stage in ahigh-impedance state (Hi-Z)and asserting the SD pinMost inductors have decreasing inductance with low.In situations other than overload,the deviceincreasing temperature and increasing current automatically recovers when the fault condition has(saturation).To some degree,an increase in been removed,e.g.,the supply voltage has increasedtemperature naturally occurs when operating at high or the temperature has dropped.For highest possibleoutput currents,due to inductor core losses and the reliability,recovering from an overload fault requiresdc resistance of the inductor copper winding.A external reset of the device no sooner than 1secondthorough analysis of inductor saturation and thermal after the shutdown (see the Device Reset section ofproperties is strongly recommended.this data sheet).Setting the OC threshold too low might cause issuessuch as lack of output power and/or unexpectedshutdowns due to sensitive overload detection.CURRENT LIMITING AND OVERLOAD DETECTION In general,it is recommended to follow closely theexternal component selection and PCB layout asThe device has independent,fast-reacting currentgiven in the application section.detectors with programmable trip threshold (OCthreshold)on all high-side and low-side power-stageFETs.See the following table for OC-adjust resistorvalues.The detector outputs are closely monitored by Overtemperature ProtectionUNDERVOLTAGE PROTECTION (UVP)AND DEVICE RESET ACTIVE-BIAS CONTROL (ABC)TAS5186ASLES156–OCTOBER 2005element in the audio path,i.e.,split-cap capacitors or series capacitor,to the desired potential before The TAS5186A has a two-levelswitching is started on the PWM outputs.(For temperature-protection system that asserts anrecommended configuration,see the typical active-low warning signal (OTW)when the deviceapplication schematic included in this data sheet).junction temperature exceeds 125°C (typical),and Ifthe device junction temperature exceeds 155°CThe start-up sequence can be controlled through (typical),the device is put into thermal shutdown,sequencing the M3and RESET pins according to resulting in all half-bridge outputs being set in theTable 2and Table 3.high-impedance state (Hi-Z)and SD being assertedlow.Table 2.5.1Mode—All Output Channels ActiveM3RESET OUT_BIAS OUT_A,OUT_D,COMMENT _B,_C _E,_FPOWER-ON RESET (POR)00Hi-Z Hi-Z Hi-Z All outputsdisabled,The UVP and POR circuits of the TAS5186A fully nothing isprotect the device in any power-up/down and switching.brownout situation.While powering up,the POR 10Active Hi-Z Hi-Z OUT_BIAScircuit resets the overload circuit (OLP)and ensures enabled,allthat all circuits are fully operational when the other outputsdisabledGVDD_X and VDD supply voltages reach 10V (typical).Although GVDD_X and VDD are 11Hi-Z Active Active OUT_BIASdisabled,allindependently monitored,a supply voltage drop other outputsbelow the UVP threshold on any VDD or GVDD_Xswitching pin results in all half-bridge outputs immediately beingset in the high-impedance (Hi-Z)state and SD beingTable 3.2.1Mode—Only Output Channels A,B,asserted low.The device automatically resumesand C Active operation when all supply voltages have increasedabove the UVP threshold.M3RESET OUT_BIAS OUT_A,OUT_D,COMMENT _B,_C _E,_F00Hi-Z Hi-Z Hi-Z All outputsdisabled,When RESET is asserted low,the output FETs in all nothing ishalf-bridges are forced into a high-impedance (Hi-Z)switching.state.10Active Hi-Z Hi-Z OUT_BIASenabled,allAsserting the RESET input low removes any fault other outputsinformation to be signaled on the SD output,i.e.,SD disabledis forced high.01Hi-Z Active Hi-ZOUT_BIASdisabled,allA rising-edge transition on the RESET input allows other outputsthe device to resume operation after an overloadswitching fault.When the TAS5186A is used with the TAS5086PWM modulator,no special attention to start-up sequencing is required,provided that the chipset is configured as Audible pop noises are often associated withrecommended.single-rail,single-ended power stages at power-up orat the start of switching.This commonly knownproblem has been virtually eliminated byincorporating a proprietary active-bias control circuitryas part of the TAS5186A feature set.By the use ofonly a few passive external components (typicallyresistors),the ABC can pre-charge the dc-blocking。

13652hvfT YPICAL APPLICATIOND ESCRIPTION ChargerThe LT ®3652HV is a complete monolithic step-down bat-tery charger that operates over a 4.95V to 34V input range. The LT3652HV provides a constant-current/constant-voltage charge characteristic, with maximum charge current externally programmable up to 2A. The charger employs a 3.3V fl oat voltage feedback reference, so any desired battery fl oat voltage up to 18V can be programmed with a resistor divider.The LT3652HV employs an input voltage regulation loop, which reduces charge current if the input voltage falls below a programmed level, set with a resistor divider. When the LT3652HV is powered by a solar panel, the input regulation loop is used to maintain the panel at peak output power.The L T3652HV c an b e c onfi gured t o t erminate c harging w hen charge c urrent f alls b elow 1/10 o f t he p rogrammed m aximum (C/10). Once charging is terminated, the LT3652HV enters a low-current (85μA) standby mode. An auto-recharge feature starts a new charging cycle if the battery voltage falls 2.5% below the programmed fl oat voltage. The LT3652HV also contains a programmable safety timer, used to terminate charging after a desired time is reached. This allows top-off charging at currents less than C/10.F EATURESA PPLICATIONS nInput Supply Voltage Regulation Loop for Peak Power T racking in (MPPT) Solar Applicationsn Wide Input Voltage Range: 4.95V to 34V (40V Abs Max)n Programmable Charge Rate Up to 2An User Selectable Termination: C/10 or On-Board Termination Timern Resistor Programmable Float Voltage Up to 18V Accommodates 4-Cell Li-Ion/Polymer , 5-Cell LiFePO 4, Lead-Acid Chemistriesn Parallelable for Higher Output Current n 1MHz Fixed Frequencyn 0.5% Float Voltage Reference Accuracy n 5% Charge Current Accuracy n 2.5% C/10 Detection Accuracyn Binary-Coded Open-Collector Status PinsnSolar Powered Applications n Remote Monitoring Stations n Portable Handheld Instruments n 12V to 24V Automotive SystemsnBattery Charging from Current Limited AdapterL , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.V IN_REG Loop Servos Maximum Charge Current to Prevent AC Adapter Output from Drooping Lower Than 24V 5-Cell LiFePO 4 Charger (18V at 1.5A) with C/10 TerminationPowered by Inexpensive 24VDC/1A Unregulated Wall Adapter.SYSTEM LOADD3ADAPTER OUTPUT CURRENT (A)00.2A D A P T E R O U T P U T V O L T A G E (V )12151833302724210.61 1.23652 TA01b360.40.8 1.61.421.81A/24VDC Unregulated AdapterI vs V CharacteristicLT3652HV23652hvfP IN CONFIGURATIONA BSOLUTE MAXIMUM RATINGS Voltages:V IN ........................................................................40V V IN_REG , SHDN , CHRG , FAUL T ............V IN + 0.5V , 40V SW ........................................................................40V SW-V IN .................................................................4.5V BOOST ...................................................SW+10V , 50V BAT , SENSE .. (20V)(Note 1)ORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE LT3652HVEDD#PBF LT3652HVEDD#TRPBF LFRG 12-Lead Plastic DFN 3mm × 3mm –40°C to 125°C LT3652HVIDD#PBF LT3652HVIDD#TRPBF LFRG 12-Lead Plastic DFN 3mm × 3mm –40°C to 125°C LT3652HVEMSE#PBF LT3652HVEMSE#TRPBF 3652HV 12-Lead Plastic MSOP –40°C to 125°C LT3652HVIMSE#PBFLT3652HVIMSE#TRPBF3652HV12-Lead Plastic MSOP–40°C to 125°CConsult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.Consult LTC Marketing for information on non-standard lead based fi nish parts.For more information on lead free part marking, go to: /leadfree/ For more information on tape and reel specifi cations, go to: /tapeandreel/TOP VIEWDD PACKAGE12-LEAD (3mm × 3mm) PLASTIC DFN1211891045321SW BOOST SENSE BAT NTCV FBV IN V IN_REG SHDN CHRG FAUL T TIMER6713123456V IN V IN_REG SHDN CHRG FAUL T TIMER 121110987SW BOOST SENSE BAT NTC V FBTOP VIEW13MSE PACKAGE12-LEAD PLASTIC MSOPT JMAX = 125°C, θJA = 43°C/W , θJC = 3°C/WEXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCBT JMAX = 125°C, θJA = 43°C/W , θJC = 3°C/WEXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCBBAT-SENSE .........................................–0.5V to +0.5VNTC, TIMER, ........................................................2.5V V FB ..........................................................................5V Operating Junction Temperature Range(Note 2) .............................................–40°C to 125°C Storage Temperature Range ...................–65°C to 150°CLT3652HV33652hvfE LECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSV IN V IN Operating RangeV IN Start Voltage V BAT = 4.2 (Notes 3, 4)V BAT = 4.2 (Note 4)l l 4.957.534V V V IN(OVLO)OVLO Threshold OVLO Hysteresis V IN Rising l3435140V V V IN(UVLO)UVLO Threshold UVLO Hysteresis V IN Rising 4.60.24.95V V V FB(FL T)Float Voltage Reference (Note 6)l 3.2823.263.3 3.3183.34V V ΔV RECHARGE Recharge Reference Threshold Voltage Relative to V FB(FL T) (Note 6)82.5mV V FB(PRE)Reference Precondition Threshold V FB Rising (Note 6)2.3V V FB(PREHYST)Reference Precondition Threshold HysteresisVoltage Relative to V FB(PRE) (Note 6)70mVV IN_REG(TH)Input Regulation Reference V FB = 3V; V SENSE – V BAT = 50mV l 2.65 2.7 2.75V I IN_REG Input Regulation Reference Bias Current V IN_REG = V IN_REG(TH)l 35100nA I VINOperating Input Supply CurrentCC/CV Mode, I SW = 0Standby ModeShutdown (SHDN = 0)l 2.58515 3.5mA μA μA I BOOST BOOST Supply Current Switch On, I SW = 0,2.5 < V (BOOST – SW) < 8.520mA I BOOST/I SW BOOST Switch Drive I SW = 2A30mA/A V SW(ON)Switch-On Voltage Drop V IN – V SW , I SW = 2A350mV I SW(MAX)Switch Current Limit l 2.53A V SENSE(PRE)Precondition Sense Voltage V SENSE – V BAT ; V FB = 2V 15mVV SENSE(DC)Maximum Sense Voltage V SENSE – V BAT ; V FB = 3V (Note 7)l 95100105mV V SENSE(C/10)C/10 T rigger Sense Voltage V SENSE – V BAT , Falling l7.51012.5mV I BAT BAT Input Bias Current Charging Terminated 0.11μA I SENSE SENSE Input Bias Current Charging Terminated 0.11μA I VFB V FB Input Bias Current Charging Terminated 65nA I VFB V FB Input Bias Current CV Operation (Note 5)110nAV NTC(H)NTC Range Limit (High)V NTC Rising l 1.25 1.36 1.45V V NTC(L)NTC Range Limit (Low)V NTC Falling l 0.270.290.315V V NTC(HYST)NTC Threshold Hysteresis % of threshold 20%R NTC(DIS)NTC Disable Impedance Impedance to ground l 250500kΩI NTC NTC Bias Current V NTC = 0.8V l 47.55052.5μA V SHDN Shutdown Threshold Risingl 1.151.2 1.25V V SHDN (HYST)Shutdown Hysteresis 120mV I SHDN SHDN Input Bias Current –10nAV CHRG , V FAUL T Status Low Voltage 10mA Load l 0.4V I TIMER Charge/Discharge Current 25μA V TIMER(DIS)Timer Disable Thresholdl0.10.25VThe l denotes the specifi cations which apply over the full operating junction temperature range, otherwise specifi cations are at T A = 25°C. V IN = 20V, Boost – SW = 4V, SHDN = 2V, V FB = 3.3V, C TIMER= 0.68μF.LT3652HV43652hvfSYMBOL PARAMETERCONDITIONS MIN TYP MAX UNITSt TIMERFull Charge Cycle Timeout 3hr Precondition Timeout 22.5minTimer Accuracyl–1010%f O Operating Frequency 1MHz DCDuty Cycle RangeContinuous Operationl 1590%E LECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating junction temperature range, otherwise specifi cations are at T A = 25°C. V IN = 20V, Boost – SW = 4V, SHDN = 2V, V FB = 3.3V, C TIMER = 0.68μF.Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The L T3652HV is tested under pulsed load conditions such that T J ≅ T A . The L T3652HVE is guaranteed to meet performance specifi cations from 0°C to 85°C junction temperature. Specifi cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The L T3652HVI specifi cations are guaranteed over the full –40°C to 125°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C.Note 3: V IN minimum voltages below the start threshold are only supported if (V BOOST -V SW ) > 2V .Note 4: This parameter is valid for programmed output battery fl oat voltages ≤ 4.2V . V IN operating range minimum is 0.75V above the programmed output battery fl oat voltage (V BAT(FL T) + 0.75V). V IN Start Voltage is 3.3V above the programmed output battery fl oat voltage (V BAT(FL T) + 3.3V).Note 5: Output battery fl oat voltage (V BAT(FL T)) programming resistor divider equivalent resistance = 250k compensates for input bias current. Note 6: All V FB voltages measured through 250k series resistance.Note 7: V SENSE(DC) is reduced by thermal foldback as junction temperature approaches 125°C.LT3652HV53652hvfT YPICAL PERFORMANCE CHARACTERISTICS Switch Forward Drop (V IN – V SW ) vs TemperatureCC/CV Charging; SENSE Pin Bias Current vs V SENSEC/10 Threshold (V SENSE –V BAT ) vs TemperatureV FB Reference Voltage vs TemperatureV IN Standby Mode Current vs TemperatureSwitch Drive (I SW /I BOOST ) vs Switch CurrentT J = 25°C, unless otherwise noted.TEMPERATURE (°C)–50V F B (F L T )3.2963.2983.3003.302050753652 G01a3.304–2525100125TEMPERATURE (°C)–5065I V I N C U R R E N T (μA )70758010090050753652 G029585–2525100SWITCH CURRENT (A)I S W /I B O O S T18243036 1.6126021273315930.40.8 1.20.2 1.80.6 1.0 1.4 2.03652 G03TEMPERATURE (°C)–50320V S W (O N ) (m V )340360380480420050753652 G04440460400–2525100125V SENSE (V)–350I S E N S E (μA )–250–150–5010050–300–200–10003652 G05TEMPERATURE (°C)–508V S E N S E (C /10) (m V )9101112050753652 G06–2525100125TEMPERATURE (°C)–50V I N _R E G (T H ) (V )2.6802.6852.6902.7152.7102.7052.7002.695050753652 G012.720–2525100125V IN_REG Thresholdvs Temperature: I CHG at 50%LT3652HV63652hvfTYPICAL PERFORMANCE CHARACTERISTICSMaximum Charge Current (V SENSE –V BAT ) vs TemperatureThermal Foldback – Maximum Charge Current (V SENSE –V BAT ) vs TemperatureCC/CV Charging; BAT Pin Bias Current vs V BATT A = 25°C, unless otherwise noted.TEMPERATURE (°C)–5099.0V S E N S E (D C ) (m V )99.299.699.8100.0101.0100.4050753652 G0799.4100.6100.8100.2–2525100125TEMPERATURE (°C)V S E N S E (D C )(m V )4080206010012045658510512535135255575951153652 G08V BAT (V)–0.4I B A T (m A )0.00.40.82.21.62.01.2–0.20.20.61.01.81.43652 G09V IN_REG (V)2.65V S E N S E (D C ) (m V )208060402.67 2.692.73652 G101002.66 2.682.722.71 2.732.742.75V BAT(FL T) (V)020I R F B (μA )861012183652 G114264810121614TIME (MINUTES)EFFICIENCY (%)C H A R G E C U R R E N T (A ); P OW E R L O S S (W )0.52.02.51.51.040801003652 G123.0354575655595852060140120160180200Maximum Charge Current(V SENSE –V BAT ) vs V IN_REG VoltageV FLOAT Programming Resistor Current vs V FLOAT for 2-Resistor NetworkCharge Current, Effi ciency, and Power Loss vs Time(I CHG(MAX) = 2A; V FLOAT = 8.2V)Charger Effi ciency vs Battery Voltage (I CHG= 2A)V BAT (V)70E F F I C I E N C Y (%)7680828486887472789057911134141536810123652 G13LT3652HV73652hvfP IN FUNCTIONS V IN (Pin 1): Charger Input Supply. V IN operating range is 4.95V to 34V. V IN must be 3.3V greater than the pro-grammed output battery fl oat voltage (V BAT(FLT)) for reli-able start-up. (V IN – V BAT(FLT)) ≥ 0.75V is the minimum operating voltage, provided (V BOOST – V SW ) ≥ 2V. I VIN ~ 85μA after charge termination. This pin is typically con-nected to the cathode of a blocking diode.V IN_REG (Pin 2): Input Voltage Regulation Reference. Maxi-mum charge current is reduced when this pin is below 2.7V. Connecting a resistor divider from V IN to this pin enables programming of minimum operational V IN voltage. This is typically used to program the peak power voltage for a solar panel. The LT3652HV servos the maximum charge current required to maintain the programmed operational V IN voltage, through maintaining the voltage on V IN_REG at or above 2.7V. If the voltage regulation feature is not used, connect the pin to V IN .SHDN (Pin 3): Precision Threshold Shutdown Pin. The enable threshold is 1.2V (rising), with 120mV of input hysteresis. When in shutdown mode, all charging functions are disabled. The precision threshold allows use of the SHDN pin to incorporate UVLO functions. If the SHDN pin is pulled below 0.4V, the IC enters a low current shutdown mode where V IN current is reduced to 15μA. Typical SHDN pin input bias current is 10nA. If the shutdown function is not desired, connect the pin to V IN .CHRG (Pin 4): Open-Collector Charger Status Output; typically pulled up through a resistor to a reference volt-age. This status pin can be pulled up to voltages as high as V IN when disabled, and can sink currents up to 10mA when enabled. During a battery charging cycle, if required charge current is greater than 1/10 of the programmed maximum current (C/10), CHRG is pulled low. A tem-perature fault also causes this pin to be pulled low. After C/10 charge termination or, if the internal timer is used for termination and charge current is less than C/10, the CHRG pin remains high-impedance.FAULT (Pin 5): Open-Collector Charger Status Output; typically pulled up through a resistor to a reference volt-age. This status pin can be pulled up to voltages as high as V IN when disabled, and can sink currents up to 10mA when enabled. This pin indicates fault conditions during abattery charging cycle. A temperature fault causes this pin to be pulled low. If the internal timer is used for termina-tion, a bad battery fault also causes this pin to be pulled low. If no fault conditions exist, the FAULT pin remains high-impedance.TIMER (Pin 6): End-Of-Cycle Timer Programming Pin. If a timer-based charge termination is desired, connect a capacitor from this pin to ground. Full charge end-of-cycle time (in hours) is programmed with this capacitor following the equation: t EOC = C TIMER • 4.4 • 106A bad battery fault is generated if the battery does not achieve the precondition threshold voltage within one-eighth of t EOC , or: t PRE = C TIMER • 5.5 • 105A 0.68μF capacitor is typically used, which generates a timer EOC at three hours, and a precondition limit time of 22.5 minutes. If a timer-based termination is not desired, the timer function is disabled by connecting the TIMER pin to ground. With the timer function disabled, charging terminates when the charge current drops below a C/10 threshold, or I CHG(MAX)/10V FB (Pin 7): Battery Float Voltage Feedback Reference. The charge function operates to achieve a fi nal fl oat voltage of 3.3V on this pin. Output battery fl oat voltage (V BAT(FLT)) is programmed using a resistor divider. V BAT(FLT) can be programmed up to 18V.The auto-restart feature initiates a new charging cyclewhen the voltage at the V FB pin falls 2.5% below the float voltage reference.The V FB pin input bias current is 110nA. Using a resistor divider with an equivalent input resistance at the V FB pin of 250k compensates for input bias current error.Required resistor values to program desired V BAT(FLT) follow the equations:R1 = (V BAT(FLT) • 2.5 • 105)/3.3 (Ω) R2 = (R1 • 2.5 • 105)/(R1 - (2.5 • 105))(Ω)R1 is connected from BAT to V FB , and R2 is connected from V FBto ground.LT3652HV 83652hvfNTC (Pin 8): Battery Temperature Monitor Pin. This pin is the input to the NTC (Negative Temperature Coeffi cient) thermistor temperature monitoring circuit. This function is enabled by connecting a 10kΩ, B = 3380 NTC thermistor from the NTC pin to ground. The pin sources 50μA, and monitors the voltage across the 10kΩ thermistor. When the voltage on this pin is above 1.36 (T < 0°C) or below 0.29V (T > 40°C), charging is disabled and the CHRG and FAULT pins are both pulled low. If internal timer termina-tion is being used, the timer is paused, suspending the charging cycle. Charging resumes when the voltage on NTC returns to within the 0.29V to 1.36V active region. There is approximately 5°C of temperature hysteresis associated with each of the temperature thresholds. The temperature monitoring function remains enabled while the thermistor resistance to ground is less than 250k, so if this function is not desired, leave the NTC pin unconnected.BAT (Pin 9): Charger Output Monitor Pin. Connect a 10μF decoupling capacitance (C BAT ) to ground. Depend-ing on application requirements, larger value decoupling capacitors may be required. The charge function operates to achieve the programmed output battery fl oat voltage (V BAT(FLT)) at this pin. This pin is also the reference for the current sense voltage. Once a charge cycle is termi-nated, the input bias current of the BAT pin is reduced to < 0.1μA, to minimize battery discharge while the charger remains connected.SENSE (Pin 10): Charge Current Sense Pin. Connect the inductor sense resistor (R SENSE ) from the SENSE pin to the BAT pin. The voltage across this resistor sets the averagecharge current. The maximum charge current (I CHG(MAX)) corresponds to 100mV across the sense resistor. This resistor can be set to program maximum charge cur-rent as high as 2A. The sense resistor value follows the relation:R SENSE = 0.1/I CHG(MAX) (Ω)Once a charge cycle is terminated, the input bias current of the SENSE pin is reduced to < 0.1μA, to minimize battery discharge while the charger remains connected.BOOST (Pin 11): Bootstrapped Supply Rail for Switch D rive. This pin facilitates saturation of the switch transistor. Connect a 1μF or greater capacitor from the BOOST pin to the SW pin. Operating range of this pin is 0V to 8.5V, referenced to the SW pin. The voltage on the decoupling capacitor is refreshed through a rectifying diode, with the anode connected to either the battery output voltage or an external source, and the cathode connected to the BOOST pin.SW (Pin 12): Switch Output Pin. This pin is the output of the charger switch, and corresponds to the emitter of the switch transistor. When enabled, the switch shorts the SW pin to the V IN supply. The drive circuitry for this switch is bootstrapped above the V IN supply using the BOOST supply pin, allowing saturation of the switch for maximum effi ciency. The effective on-resistance of the boosted switch is 0.175Ω.SGND (Pin 13): Ground Reference and Backside Exposed Lead Frame Thermal Connection. Solder the exposed lead frame to the PCB ground plane.P IN FUNCTIONSLT3652HV93652hvfB LOCK DIAGRAM+–LT3652HV103652hvfA PPLICATIONS INFORMATION OverviewL T3652HV is a complete monolithic, mid-power , multi-chemistry buck battery charger , addressing high input voltage applications with solutions that require a minimum of external components. The IC uses a 1MHz constant fre-quency, average-current mode step-down architecture.The L T3652HV incorporates a 2A switch that is driven by a bootstrapped supply to maximize efficiency during charging cycles. Wide input range allows operation to full charge from voltages as high as 34V . A precision threshold shutdown pin allows incorporation of UVLO functionality using a simple resistor divider . The IC can also be put into a low-current shutdown mode, in which the input supply bias is reduced to only 15μA.The L T3652HV employs an input voltage regulation loop, which reduces charge current if a monitored input voltage falls below a programmed level. When the L T3652HV is powered by a solar panel, the input regulation loop is used to maintain the panel at peak output power .The L T3652HV automatically enters a battery precondition mode if the sensed battery voltage is very low. In this mode, the charge current is reduced to 15% of the programmed maximum, as set by the inductor sense resistor , R SENSE . Once the battery voltage reaches 70% of the fully charged float voltage, the IC automatically increases maximum charge current to the full programmed value.The L T3652HV can use a charge-current based C/10 termination scheme, which ends a charge cycle when the battery charge current falls to one tenth of the pro-grammed maximum charge current. The L T3652HV also contains an internal charge cycle control timer , for timer-based termination. When using the internal timer , the IC combines C/10 detection with a programmable time constraint, during which the charging cycle can continue beyond the C/10 level to top-off a battery. The charge cycle terminates when a specific time elapses, typically 3 hours. When the timer-based scheme is used, the IC also supports bad battery detection, which triggers a system fault if a battery stays in precondition mode for more than one eighth of the total charge cycle time.Once charging is terminated, the L T3652HV automati-cally enters a low-current standby mode where supply bias currents are reduced to 85μA. The IC continues tomonitor the battery voltage while in standby, and if that voltage falls 2.5% from the full-charge float voltage, the L T3652HV engages an automatic charge cycle restart. The IC also automatically restarts a new charge cycle after a bad battery fault once the failed battery is removed and replaced with another battery.The L T3652HV contains provisions for a battery tem-perature monitoring circuit. This feature monitors battery temperature using a thermistor during the charging cycle. If the battery temperature moves outside a safe charg-ing range of 0°C to 40°C, the IC suspends charging and signals a fault condition until the temperature returns to the safe charging range.The L T3652HV contains two digital open-collector outputs, which provide charger status and signal fault conditions. These binary-coded pins signal battery charging, standby or shutdown modes, battery temperature faults, and bad battery faults.General Operation (See Block Diagram)The L T3652HV uses average current mode control loop architecture, such that the IC servos directly to average charge current. The L T3652HV senses charger output voltage through a resistor divider via the V FB pin. The difference between the voltage on this pin and an internal 3.3V voltage reference is integrated by the voltage error amplifier (V-EA). This amplifier generates an error volt-age on its output (I TH ), which corresponds to the average current sensed across the inductor current sense resistor , R SENSE , which is connected between the SENSE and BAT pins. The I TH voltage is then divided down by a factor of 10, and imposed on the input of the current error amplifier (C-EA). The difference between this imposed voltage and the current sense resistor voltage is integrated, with the resulting voltage (V C ) used as a threshold that is compared against an internally generated ramp. The output of this comparison controls the charger’s switch.The I TH error voltage corresponds linearly to average current sensed across the inductor current sense resistor , allowing maximum charge current control by limiting the effective voltage range of I TH . A clamp limits this voltage to 1V which, in turn, limits the current sense voltage to 100mV . This sets the maximum charge current, or the current delivered while the charger is operating in con-A PPLICATIONS INFORMATIONstant-current (CC) mode, which corresponds to 100mV across R SENSE. The I TH voltage is pulled down to reduce this maximum charge current should the voltage on the V IN_REG pin falls below 2.7V (V IN_REG(TH)) or the die tem-perature approaches 125°C.If the voltage on the V FB pin is below 2.3V (V FB(PRE)), the L T3652HV engages precondition mode. D uring the precondition interval, the charger continues to operate in constant-current mode, but the maximum charge current is reduced to 15% of the maximum programmed value as set by R SENSE.When the charger output voltage approaches the float volt-age, or the voltage on the V FB pin approaches 3.3V (V FB(FL T)), the charger transitions into constant-voltage (CV) mode and charge current is reduced from the maximum value. As this occurs, the I TH voltage falls from the limit clamp and servos to lower voltages. The IC monitors the I TH volt-age as it is reduced, and detection of C/10 charge current is achieved when I TH = 0.1V. If the charger is configured for C/10 termination, this threshold is used to terminate the charge cycle. Once the charge cycle is terminated, the CHRG status pin becomes high-impedance and the charger enters low-current standby mode.The L T3652HV contains an internal charge cycle timer that terminates a successful charge cycle after a programmed amount of time. This timer is typically programmed to achieve end-of-cycle (EOC) in 3 hours, but can be con-figured for any amount of time by setting an appropriate timing capacitor value (C TIMER). When timer termination is used, the charge cycle does not terminate when C/10 is achieved. Because the CHRG status pin responds to the C/10 current level, the IC will indicate a fully-charged battery status, but the charger continues to source low currents into the battery until the programmed EOC time has elapsed, at which time the charge cycle will terminate. At EOC when the charging cycle terminates, if the battery did not achieve at least 97.5% of the full float voltage, charging is deemed unsuccessful, the L T3652HV re-initiates, and charging continues for another full timer cycle.Use of the timer function also enables bad-battery detec-tion. This fault condition is achieved if the battery does not respond to preconditioning, such that the charger remains in (or enters) precondition mode after 1/8th of the programmed charge cycle time. A bad battery fault halts the charging cycle, the CHRG status pin goes high-impedance, and the FAUL T pin is pulled low.When the L T3652HV terminates a charging cycle, whether through C/10 detection or by reaching timer EOC, the average current mode analog loop remains active, but the internal float voltage reference is reduced by 2.5%. Because the voltage on a successfully charged battery is at the full float voltage, the voltage error amp detects an over-voltage condition and I TH is pulled low. When the voltage error amp output drops below 0.3V, the IC enters standby mode, where most of the internal circuitry is dis-abled, and the V IN bias current is reduced to 85μA. When the voltage on the V FB pin drops below the reduced float reference level, the output of the voltage error amp will climb, at which point the IC comes out of standby mode and a new charging cycle is initiated.V IN Input SupplyThe L T3652HV is biased through a reverse-current block-ing element from the charger input supply to the V IN pin. This supply provides large switched currents, so a high-quality, low ESR decoupling capacitor is recommended to minimize voltage glitches on V IN. The V IN decoupling capacitor (C VIN) absorbs all input switching ripple current in the charger, so it must have an adequate ripple current rating. RMS ripple current (I CVIN(RMS)) is:I CVIN(RMS)≅ I CHG(MAX) • (V BAT / V IN)•([V IN / V BAT] – 1)1/2,where I CHG(MAX) is the maximum average charge current (100mV/R SENSE). The above relation has a maximum at V IN = 2 • V BAT, where:I CVIN(RMS) = I CHG(MAX)/2.The simple worst-case of ½ • I CHG(MAX) is commonly used for design.。

May 2008Rev 51/9BD135 - BD136BD139 - BD140Complementary low voltage transistorFeatures■Products are pre-selected in DC current gainApplication■General purposeDescriptionThese epitaxial planar transistors are mounted in the SOT -32 plastic package. They are designed for audio amplifiers and drivers utilizingcomplementary or quasi-complementary circuits. The NPN types are the BD135 and BD139, and the complementary PNP types are the BD136 and BD140.Table 1.Device summaryOrder codes Marking Package PackagingBD135BD135SOT -32TubeBD135-16BD135-16BD136BD136BD136-16BD136-16BD139BD139BD139-10BD139-10BD139-16BD139-16BD140BD140BD140-10BD140-10BD140-16BD140-16Contents BD135 - BD136 - BD139 - BD140Contents1Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82/9BD135 - BD136 - BD139 - BD140Electrical ratings3/91 Electrical ratingsTable 2.Absolute maximum ratingsSymbolParameterValueUnitNPNPNPBD135BD139BD136BD140V CBO Collector-base voltage (I E = 0)4580-45-80V V CEO Collector-emitter voltage (I B = 0)4580-45-80V V EBO Emitter-base voltage (I C = 0)5-5V I C Collector current 1.5-1.5A I CM Collector peak current 3-3A I B Base current0.5-0.5A P TOT Total dissipation at T c ≤ 25 °C 12.5W P TOT Total dissipation at T amb ≤ 25 °C 1.25W T stg Storage temperature-65 to 150°C T jMax. operating junction temperature150°CTable 3.Thermal dataSymbolParameterMax valueUnit R thj-case Thermal resistance junction-case 10°C/W R thj-amb Thermal resistance junction-ambient100°C/WElectrical characteristics BD135 - BD136 - BD139 - BD1404/92 Electrical characteristics(T case = 25 °C unless otherwise specified)Table 4.On/off statesSymbolParameterPolarityTest conditionsValueUnitMin.Typ.Max.I CBOCollector cut-off current (I E =0)NPN V CB = 30 VV CB = 30 V , T C = 125 °C 0.110µA µA PNP V CB = -30 VV CB = -30 V , T C = 125 °C -0.1-10µA µA I EBOEmitter cut-off current (I C =0)NPN V EB = 5 V 10µA PNP V EB = -5 V -10µA V CEO(sus)(1)1.Pulsed: pulse duration = 300 µs, duty cycle 1.5%Collector-emittersustaining voltage(I B =0)NPNI C = 30 mA BD135BD1394580V V PNP I C = -30 mA BD136BD140-45-80V V V CE(sat) (1)Collector-emitter saturation voltage NPN I C = 0.5 A, I B = 0.05 A 0.5V PNP I C = -0.5 A, I B = -0.05 A -0.5V V BE (1)Base-emitter voltageNPN I C = 0.5 A, V CE = 2 V 1V PNP I C = -0.5 A, V CE = -2 V -1V h FE (1)DC current gainNPNI C = 5 mA, V CE = 2 V I C = 150 mA, V CE = 2 V I C = 0.5 A, V CE = 2 V 254025250PNPI C = -5 mA, V CE = -2 V I C = -150 mA, V CE = -2 V I C = -0.5 A, V CE = -2 V 254025250h FE (1)h FE groupsNPNI C = 150 mA, V CE = 2 V BD139-10BD135-16/BD139-1663100160250PNPI C = -150 mA, V CE = -2 V BD140-10BD136-16/BD140-1663100160250BD135 - BD136 - BD139 - BD140Electrical characteristics 2.1 Electrical characteristics (curves)Figure 2.Safe operating area Figure 3.Derating5/9Package mechanical data BD135 - BD136 - BD139 - BD140 3 Package mechanical dataIn order to meet environmental requirements, ST offers these devices in ECOPACK®packages. These packages have a lead-free second level interconnect. The category ofsecond level interconnect is marked on the package and on the inner box label, incompliance with JEDEC Standard JESD97. The maximum ratings related to solderingconditions are also marked on the inner box label. ECOPACK is an ST trademark.ECOPACK specifications are available at: 6/9BD135 - BD136 - BD139 - BD140Package mechanical data7/9。