XL3003 datasheet(中文版)

5A 220KHz 36V Buck LED Constant Current Driver XL3005FeaturesWide 8V to 36V Input Voltage Range Output Current Sense Voltage is 0.21V Maximum Duty Cycle 100% Minimum Drop Out 0.3VFixed 220KHz Switching Frequency 5A Constant Output Current Capability Internal Optimize Power MOSFET High efficiencyExcellent line and load regulation Built in thermal shutdown function Built in current limit functionBuilt in output short protection function Available in TO-263 packageApplicationsBuck constant current driver Monitor LED Backlighting General purpose LED lightingGeneral DescriptionThe XL3005 is a 220 KHz fixed frequency PWM buck (step-down) LED constant current driver, capable of driving a 5A load with high efficiency, low ripple and excellent line and load regulation. Requiring a minimum number of external components, the regulator is simple to use and include internal frequency compensation and a fixed-frequency oscillator.The PWM control circuit is able to adjust the duty ratio linearly from 0 to 100%. An over current protection function is built inside. When short protection function happens, the operation frequency will be reduced from 220KHz to 60KHz. An internal compensation block is built in to minimize external component count.Figure1. Package Type of XL30055A 220KHz 36V Buck LED Constant Current Driver XL30055A 220KHz 36V Buck LED Constant Current Driver XL3005Figure4. XL3005 Typical Application Circuit5A 220KHz 36V Buck LED Constant Current Driver XL30055A 220KHz 36V Buck LED Constant Current Driver XL30055A 220KHz 36V Buck LED Constant Current Driver XL30055A 220KHz 36V Buck LED Constant Current Driver XL30055A 220KHz 36V Buck LED Constant Current Driver XL3005 Figure13. XL3005 System Parameters Test Circuit (VIN=8V~36V, IOUT=308mA)5A 220KHz 36V Buck LED Constant Current Driver XL3005 Figure15. XL3005 System Parameters Test Circuit (VIN=8V~36V, IOUT=615mA)5A 220KHz 36V Buck LED Constant Current Driver XL3005 Figure17. XL3005 System Parameters Test Circuit (VIN=8V~36V, IOUT=925mA)5A 220KHz 36V Buck LED Constant Current Driver XL3005 Figure19. XL3005 System Parameters Test Circuit (VIN=8V~36V, IOUT=1540mA)5A 220KHz 36V Buck LED Constant Current Driver XL3005 Figure21. XL3005 System Parameters Test Circuit (VIN=8V~36V, IOUT=2140mA)5A 220KHz 36V Buck LED Constant Current Driver XL3005Figure23. XL3005 System Parameters Test Circuit (PWM DIMMING)Typical System Application (LED OVP)be limited in a suitable value by choose different zener diode when the output LED open. the zener diode Figure24. XL3005 System Parameters Test Circuit (LED OVP)5A 220KHz 36V Buck LED Constant Current Driver XL30055A 220KHz 36V Buck LED Constant Current Driver XL3005 Important NoticeXLSEMI reserve the right to make modifications, enhancements, improvements, corrections or other changes without notice at any time. XLSEMI does not assume any liability arising out of the application or use of any product described herein; neither does it convey any license under its patent rights, nor the rights of others. XLSEMI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using XLSEMI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. XLSEMI warrants performance of its products to the specifications applicable at the time of sale, in accordance with the warranty in XLSEMI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent XLSEMI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.For the latest product information, go to .。

MIC3003GFLFOM Management IC with Internal CalibrationMLF and MicroLead Frame are registered trademarks of Amkor Technology, Inc.General DescriptionThe MIC3003GFL is a fiber optic module controller which enables the implementation of sophisticated, hot-pluggable fiber optic transceivers with intelligent laser control and an internally calibrated Digital Diagnostic Monitoring Interface per SFF-8472. It essentially integrates all non-data path functions of an SFP/SFP+ transceiver into a tiny (3mm x 3mm ) MLF ® package. It also works well as a microcontroller peripheral in transponders or 10Gbps transceivers. The MIC3003GFL uses the same die as the MIC3003 with all its functions, but in a smaller package and different pin out. A highly configurable automatic power control (APC) circuit controls laser bias. Bias and modulation are temperature compensated using dual DACs, an on-chip temperature sensor, and NVRAM look-up tables. A programmable internal feedback resistor provides a wide dynamic range for the APC. Controlled laser turn-on.An analog-to-digital converter converts the measured temperature, voltage, bias current, transmit power, and received power from analog to digital. An EEPOT provides front-end adjustment of RX power. Each parameter is compared against user-programmed warning and alarm thresholds. Analog comparators and DACs provide fast monitoring of received power and critical laser operating parameters. Data can be reported as either internally calibrated or externally calibrated.An interrupt output, power-on hour meter, and data-ready bits add user friendliness beyond SFF-8472. The interrupt output and data-ready bits reduce overhead in the host system. The power-on hour meter logs operating hours using an internal real-time clock and stores the result in NVRAM.In addition to the features listed above, the MIC3003 features an extended temperature range, options to mask alarms and warnings interrupt and TXFAULT, a reset signal source, and the ability to support up to four chips with the same address on the serial interface. It also supports eight-byte SMBus block writes.Communication with the MIC3003 is via an industry standard 2-wire SMBus serial interface. Nonvolatile memory is provided for serial ID, configuration, and separate OEM and user scratchpad spaces.Datasheets and support documentation can be found on Micrel’s web site at: .Features• Packaged in a ultra small (3mm x 3mm) 24-pin MLF ® package • Extended temperature range• Alarms and warnings interrupt and TXFAULT masks • Capability to support up to four devices on one SMBus • APC or constant-current laser bias• Turbo mode for APC loop start-up and shorter laser turn on time • Supports multiple laser types and bias circuit topologies • Integrated digital temperature sensor• Temperature compensation of modulation, bias, bias fault and alarm thresholds via NVRAM look-up tables • NVRAM to support GBIC/SFP serial ID function • User writable EEPROM scratchpad• Reset signal compatible with some new systems requirements • Diagnostic monitoring interface per SFF-8472 – Monitors and reports critical parameters:temperature, bias current, TX and RX optical power, and supply voltage– S/W control and monitoring of TXFAULT, RXLOS, RATESELECT, and TXDISABLE – Internal or external calibration– EEPOT for adjusting RX power measurement • Power-on hour meter • Interrupt capability• Extensive test and calibration features • 2-wire SMBus-compatible serial interface • SFP/SFP+ MSA and SFF-8472 compliant • 3.0V to 3.6V power supply range • 5V-tolerant I/OApplications• SFP/SFP+ optical transceivers• SONET/SDH transceivers and transponders • Fibre Channel transceivers • 10Gbps transceivers• Free space optical communications • Proprietary optical linksTypical ApplicationOrdering InformationPart NumberPackage Marking Junction Temp.RangePackage Type Lead FinishMIC3003GFL GFL 3003 with Pb-Free bar-line indicator–45°C to +105°C24-pin (3mm x 3mm) MLF ® Pb-Free,NiPdAuMIC3003GFLTR (1) GFL 3003 with Pb-Free bar-line indicator–45°C to +105°C24-pin (3mm x 3mm) MLF ® Pb-Free,NiPdAuNote:1. Tape and Reel.ContentsGeneral Description (1)Features (1)Pin Configuration (8)Pin Configuration (8)Pin Description (MIC3003GFL only) (8)Absolute Maximum Ratings (10)Operating Ratings (10)Electrical Characteristics (10)Electrical Characteristics (12)Electrical Characteristics (13)Serial Interface Timing Diagram (14)Serial Interface Address Maps (15)Block Diagram (18)Analog-to-Digital Converter/Signal Monitoring (18)Alarms and Warnings Interrupt Source Masking (19)Alarms and Warnings as TXFAULT Source (21)Latching of Alarms and Warnings (21)SMBus Multipart Support (21)QGOP Pin Function (21)Calibration Modes (22)A/ External Calibration (22)Voltage (22)Temperature (22)Bias Current (22)TX Power (22)RX Power (23)B/ Internal Calibration (23)Computing Internal Calibration Results (23)C/ Reading the ADC Result Registers (25)RXPOT (25)Laser Diode Bias Control (25)Laser Modulation Control (26)Power On and Laser Start-Up (27)Fault Comparators (28)SHDN and TXFIN (29)Temperature Measurement (30)Diode Faults (30)Temperature Compensation (30)Alarms and Warning Flags (32)Control and Status I/O (32)System Timing (34)Warm Resets (36)Power-On Hour Meter (36)Test and Calibration Features (37)Serial Port Operation (38)Block Writes (38)Acknowledge Polling (39)Write Protection and Data Security (39)OEM Password (39)OEM Mode and User Mode (39)Detailed Register Descriptions (40)Alarm Threshold Registers (40)Temperature High Alarm Threshold (40)Temperature Low Alarm Threshold (40)Voltage High Alarm Threshold (40)D[7] read/write (40)Bias Current High Alarm Threshold (41)Bias Current Low Alarm Threshold (41)TX Optical Power High Alarm Threshold (41)TX Optical Power Low Alarm Threshold (42)RX Optical Power High Alarm Threshold (42)RX Optical Power Low Alarm Threshold (42)Warning Threshold Registers (43)Temperature High Warning Threshold (43)Temperature Low Warning Threshold (43)Voltage High Warning Threshold (43)Voltage Low Warning Threshold (44)Bias Current High Warning Threshold (44)Bias Current Low Warning Threshold (44)TX Optical Power High Warning (44)TX Optical Power Low Warning (45)RX Optical Power High Warning Threshold (45)RX Optical Power Low Warning Threshold (45)Checksum (CHKSUM) Checksum of bytes 0 - 94 at serial address A2h (45)ADC Result Registers (46)Temperature Result (46)Voltage (46)Laser Diode Bias Current (46)Transmitted Optical Power (47)Received Optical Power (47)Control and Status (CNTRL) (47)Application Select Control Mode (ASCM) (48)Alarm Flags (50)Alarm Status Register 0 (ALARM0) (50)Alarm Status Register 1 (ALARM1) (50)Warning Flags (51)Warning Status Register 0 (WARN0) (51)Warning Status Register 1 (WARN1) (51)Extended Control and Status (ECNTRL) (52)OEM Password Entry (OEMPW) (52)Power-On Hours (POHh and POHl) (53)Data Ready Flags (DATARDY) (53)User Control Register (USRCTL) (54)RESETOUT (54)OEM Configuration Register 0 (OEMCFG0) (55)OEM Configuration Register 1 (OEMCFG1) (56)OEM Configuration Register 2 (OEMCFG2) (57)APC Setpoint 0, 1, and 2 (APCSET0, APCSET1, APCSET2) Automatic Power Control Setpoint (58)Modulation Setpoint 0, 1, and 2 (MODSET0, MODSET1, and MODSET2) Nominal V MOD Setpoint (58)I BIAS Fault Threshold (IBFLT) Bias Current Fault Threshold (59)Transmit Power Fault Threshold (TXFLT) (59)Loss-Of-Signal Threshold (LOSFLT) (59)Fault Suppression Timer (FLTTMR) Fault Suppression Interval in Increments of 0.5 ms (60)Fault Mask (FLTMSK) (60)OEM Password Setting (OEMPWSET) (61)OEM Calibration 0 (OEMCAL0) (61)OEM Calibration 1 (OEMCAL1) (63)LUT Index (LUTINDX) (64)OEM Configuration 3 (OEMCFG3) (64)BIAS DAC Setting (APCDAC) Current VBIAS Setting (65)Modulation DAC Setting (MODDAC) Current VMOD Setting (66)OEM Readback Register (OEMRD) (66)OEM Configuration 4 (OEMCFG4) (67)OEM Configuration 5 (OEMCFG5) (68)OEM Configuration 6 (OEMCFG6) (69)Power-On Hour Meter Data (POHDATA) (70)OEM Scratchpad Registers (SCRATCHn) (71)RX Power Coefficient Look-up Table (RXLUTn) (71)Calibration Constants (CALCOEFn) (72)Manufacturer ID Register (MFG_ID) Identifies Micrel as the manufacturer of the device. Always returns 2Ah (72)Device ID Register (DEV_ID) (73)Package Information (74)Figure 1. MIC3003 Block Diagram (18)Figure 2. Analog-to-Digital Converter Block Diagram (18)Figure 3. Internal Calibration RX Power Linear Approximation (25)Figure 4. RXPOT Block Diagram (25)Figure 5. APC and Modulation Control Block Diagram (26)Figure 6. Programmable Feedback Resistor (26)Figure 7. Transmitter Configurations Supported by MIC3003 (26)Figure 8. V MOD Configured as Voltage Output with Gain (27)Figure 9. MIC3003 Power-On Timing (OE = 1) (28)Figure 10. Fault Comparator Logic (28)Figure 11. Saturation Detector (29)Figure 12. RXLOS Comparator Logic (29)Figure 14. Transmitter On-Off Timing (34)Figure 15. Initialization Timing with TXDISABLE Asserted (34)Figure 16. Initialization Timing with TXDISABLE Not Asserted (34)Figure 17. Loss-of-Signal (LOS) Timing (35)Figure 19. Successfully Clearing a Fault Condition (36)Figure 20. Unsuccessful Attempt to Clear a Fault (36)Figure 21. Write Byte Protocol (38)Figure 22. Read Byte Protocol (38)Figure 23. Read_Word Protocol (38)Figure 24. Eight-Byte Block Write Protocol (39)Table 1. Serial Interface Address Map, Device Address = A0h (15)Table 2. Serial Interface Address Map, Device Address = A2 (15)Table 3. Serial Interface Address Map (Temperature Compensation Tables), Device Address = A4h (16)Table 4. Serial Interface Address Map (OEM Configuration Registers), Device Address = A6h (17)Table 5. A/D Input Signal Ranges and Resolutions (19)Table 6. V AUX Input Signal Ranges and Resolutions (19)Table 7. Alarms Interrupt Sources Masking Bits (20)Table 8. Warnings Interrupt Sources Masking Bits (20)Table 9. RESETOUT Clear Delay (21)Table 10. LSB Values of Offset Coefficients (23)Table 11. Internal Calibration Coefficient Memory Map – Part I (24)Table 12. Internal Calibration Coefficient Memory Map – Part II (24)Table 13. Shutdown State of SHDN vs. Configuration Bits (27)Table 14. Shutdown State of V BIAS vs. Configuration Bits (27)Table 15. Shutdown State of V MOD vs. Configuration Bits (27)Table 16. Temperature Compensation Look-up Tables (30)Table 17. APC Temperature Compensation Look-Up Table (31)Table 18. I MOD Temperature Compensation Look-Up Table (31)Table 19. I BIAS Comparator Temperature Compensation Look-Up Table (31)Table 20. BIAS Current High Alarm Temperature Compensation Table (31)Table 21. MIC3003 Alarm and Warning Events (33)Table 22. Test and Diagnostic Features (37)Pin Configuration24-Pin MLF® (ML)Pin Description (MIC3003GFL only)Pin Number Pin Name Pin Function1 VDDD Power supply input for digital functions.Open-drain output. Can be selected (via OEMCFG3 bit 7) to be an open-drain GPO or an active-2 QGPOlow, open-drain, pulsed reset signal output controlled by the status of bits [0-2] of byte A2h: FFh.3 GNDD Ground return for digital functions.Digital input. Receiver Rate Select input. OR’ed with soft rate select bit SRS0 to determine the4 RS0state of the RRSOUT pin. The state of this pin is always reflected in the RS0S bit.If bit 4 (IE) in the USRCTL register is set to 0 (its default value), this pin is configured as an analog5 VIN/INTinput. If IE bit is set to 1, this pin is configured as an open-drain output.Analog input: Multiplexed A/D input for monitoring supply voltage, with a 0V to 5.5V input range.Open-drain output: outputs the internally generated active-low interrupt signal /INT.6 CLK Digital input. Serial clock input.7 DATA Digital I/O, open-drain, bi-directional serial data input/output.Digital input; Active high. The transmitter is disabled when this input is high or the STXDIS bit is8 TXDISABLEset to 1. The state of this input is always reflected in the TXDIS bit.Digital Output; Open-Drain, with programmable polarity. If OEMCFG5 bit 4 is set to 0, a high level9 TXFAULTindicates a hardware fault impeding transmitter operation. If OEMCFG5 bit 4 is set to 1, a low levelindicates a hardware fault impeding transmitter operation. The state of this pin is always reflectedin the TXFLT bit.Digital Input; Transmitter Rate Select Input; OR’ed with soft rate select bit SRS1 to determine the10 RS1state of the TRSOUT pin. The state of this pin is always reflected in the RS1S bit.Analog Input. Multiplexed A/D converter input for monitoring received optical power. The input11 VRXrange is 0 to V REF. A 5-bit programmable EEPOT on this pin provides coarse calibration andranging of the RX power measurement.Pin Number Pin Name Pin Function12 SHDN/TXFINDigital output/Input; programmable polarity. When used as shutdown output (SHDN), OEMCFG3bit 2 set to 0, SHDN is asserted at the detection of a fault condition if OEMCFG4 bit 7 is set to 0. IfOEMCFG4 bit 7 is set to 1, a fault condition will not assert SHDN. When programmed as TXFIN, itis an input for external fault signals to be OR’ed with the internal fault sources to drive TXFAULT.13 VILD+Analog Input. Multiplexed A/D input for monitoring laser bias current via a sense resistor (signalinput); accommodates inputs referenced to V DD or GND (see pin 14 description).14 VILD–Analog Input. Reference terminal for the multiplexed pseudo-differential A/D converter inputs formonitoring laser bias current via a sense resistor (VILD+ is the sensing input). Tie to V DD or GNDto reference the voltage sensed on VILD+ to V DD or GND, respectively.15 VDDA Power supply input for analog functions.16 GNDA Ground return for analog functions.17 VMPDAnalog Input. Multiplexed A/D converter input for monitoring transmitted optical power via amonitor photodiode. In most applications, VMPD will be connected directly to FB. The input rangeis 0 - V REF or 0 - V REF/4 depending upon the setting of the APC configuration bits18 FBAnalog Input. Feedback voltage for the APC loop op-amp. Polarity and scale are programmablevia the APC configuration bits I OEMCFG1. Connect to V BIAS if APC is not used.19 VMODAnalog Output. Buffered DAC output to set the modulation current on the laser driver IC. Operateswith either a 0– V REF or a (V DD–V REF) – V DD output swing so as to generate either a ground-referenced or a V DD referenced programmed voltage. A simple external circuit can be used togenerate a programmable current for those drivers that require a current rather than a voltageinput.20 VMOD–Analog input. This pin is the inverting terminal of the VMOD buffer op-amp. Connect to VMOD(gain = 1) or a feedback resistor network to set a different gain value.21 VBIASAnalog output. Buffered DAC output capable of sourcing or sinking up to 10mA under control ofthe APC function to drive an external transistor or the APCSET pin of a laser diode driver for laserdiode DC bias. The output and feedback polarity are programmable to accommodate either anNPN or a PNP transistor to drive a common-anode or common-cathode laser diode.22 COMPAnalog output. Compensation terminal for the APC loop. Connect a capacitor between this pin andGNDA or V DDA with the appropriate value to tune the APC loop time constant to a desirable value.23 RRSOUT/GPO Digital Output. Open-Drain or push-pull.If OEMCFG3 bit 4 is set to 0, RRSOUT is selected. It represents the receiver rate select as per SFF. This output is controlled by the SRS0 bit OR’ed with RS0 input and is open drain only.If OEMCFG3 bit 4 is set to 1, GPO is selected. General-purpose, non-volatile output, it is controlled by the GPO configuration bits in OEMCFG3.24 RXLOS/TRSOUT Digital output. This programmable polarity, open-drain outputs has two purposes:If OEMCFG6 bit 2 = 0, indicates the loss of the received signal as indicated by a level of received optical power below the programmed RXLOS comparator threshold; may be wire-OR’ed with external signals. Normal operation is indicated by a low level when OEMCFG6 bit 3 is set to 0 and a high level when OEMCFG6 bit 3 is set to 1. RXLOS is de-asserted when VRX > LOSFLTn. The LOS bit reflects the state of RXLOS whether driven by the MIC3003 or an external circuit.If OEMCFG6 bit 2 = 1, TRSOUT is selected. This signal represents the transmitter rate select as per the SFF specification. This output is controlled by the SRS1 bit OR’ed with the RS1 input.Absolute Maximum Ratings(1)Power Supply Voltage, V DD.......................................+3.8V Voltage on CLK, DATA, TXFAULT, VIN, RXLOS, TXDISABLE, RS0, RS1.........................–0.3V to +6.0V Voltage On Any Other Pin.....................–0.3V to V DD+0.3V Power Dissipation, T A = 85°C....................................1.5W Junction Temperature (T J).......................................150°C Storage Temperature (T S).......................–65°C to +150°C Soldering (20 sec.)...................................................260ºC ESD Ratings(3)Human Body Model..................................................2kV Machine Model.......................................................300V Operating Ratings(2)Power Supply Voltage, V DDA/V DDD...........+3.0V to +3.6V Ambient Temperature Range (T A) .......–40°C to +105°C Package Thermal ResistanceMLF® (θJA).................................................60°C/WElectrical CharacteristicsFor typical values, T A = 25°C, V DDA = V DDD = +3.3V, unless otherwise noted. Bold values are guaranteed for +3.0V ≤ (V DDA = V DDD)≤ 3.6V, T(min)≤ T A≤ T(min), (8)Symbol Parameter Condition Min Typ Max Units Power SupplyCLK = DATA = V DDD= V DDA; TXDISABLE low; all DACs at full-scale; all A/D inputs at full-scale; all other pins open. 2.3 3.5 mAI DD SupplyCurrentCLK = DATA = V DDD= V DDA; TXDISABLEhigh; FLTDAC at full-scale; all A/D inputsat full-scale; all other pins open.2.33.5 mAV POR Power-on Reset Voltage All registers reset to default values;A/D conversions initiated. 2.92.98 VVUVLOUnder-Voltage Lockout Threshold Note 5 2.5 2.73 VVHYSTPower-on Reset Hysteresis Voltage 170 mVtPORPower-on Reset Time V DD > V POR, Note 4 50 µs V REF ReferenceVoltage 1.2101.2251.240 V ΔV REF/ΔV DDAVoltage Reference Line Regulation 1.7 mV/V Temperature-to-Digital Converter CharacteristicsLocal Temperature MeasurementError–40°C ≤ T A≤ +105°C, Note 6 ±1 ±3 °Ct CONV Conversion Time Note 4 60 mst SAMPLE SamplePeriod 100 ms Voltage-to-Digital Converter Characteristics (V RX, V AUX, V BIAS, V MPD, V ILD±)Voltage Measurement Error –40°C ≤ T A≤ +105°C, Note 6 ±1 ±2.0 %fst CONV Conversion Time Note 4 10 mst SAMPLE Sample Period Note 4 100 ms Notes:1. Exceeding the absolute maximum rating may damage the device.2. The device is not guaranteed to function outside its operating rating.3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.4. Guaranteed by design and/or testing of related parameters. Not 100% tested in production.5. The MIC3003 will attempt to enter its shutdown state when V DD falls below V UVLO. This operation requires time to complete. If the supply voltage fallstoo rapidly, the operation may not be completed.6. Does not include quantization error.分销商库存信息:MICRELMIC3003GFL MIC3003GFL TR。

页数：第1 页，共5 页描述221001A01是为产品XL4003制作的演示板，用于DC8V~32V输入，输出电压5V，输出电流3.4A的降压恒压应用演示，最高转换效率可以达到93%。

XL4003是开关降压型DC-DC转换芯片；固定开关频率300KHz，可减小外部元器件尺寸，方便EMC设计。

芯片具有出色的线性调整率与负载调整率，输出电压支持0.8V~30V间任意调节。

芯片内部集成过流保护、过温保护、短路保护等可靠性模块。

XL4003为标准TO252-5L封装，集成度高，外围器件少，应用灵活。

DEMO原理图VOUT=0.8*(1+R2/R1)引脚介绍页数：第2 页，共5 页物料清单性能测试转换效率页 数：第 3 页， 共 5 页转换效率： 线性调整率与负载调整率：Efficiency VS Load currentE f f i c i e n c y (%)Load current(A)Output voltage VS Output currentO u t p u t v o l t a g e (V )Output current(A)页数：第4 页，共5 页DEMO实物图PCB布局40mm顶层底层页数：第5 页，共5 页应用信息输入电容选择在连续模式中，转换器的输入电流是一组占空比约为VOUT/VIN的方波。

为了防止大的瞬态电压，必须采用针对最大RMS电流要求而选择低ESR(等效串联电阻)输入电容器。

对于大多数的应用，1个10uF的输入电容器就足够了, 它的放置位置尽可能靠近XL4003的位置上。

最大RMS电容器电流由下式给出：IRMS≈IMAX*√VOUT(VIN-VOUT)VIN其中，最大平均输出电流IMAX等于峰值电流与1/2峰值纹波电流之差，即IMAX=ILIM-△IL/2。

在未使用陶瓷电容器时，还建议在输入电容上增加一个0.1uF至1uF的陶瓷电容器以进行高频去耦。

输出电容选择在输出端应选择低ESR电容以减小输出纹波电压，一般来说，一旦电容ESR得到满足，电容就足以满足需求。

Agilent Zorbax 300-SCX DatasheetGeneral DescriptionZorbax 300-SCX is a polar bonded-phase column pack-ing used for cation exchange high-performance liquid chromatography. This packing consists of an aromatic sulfonic acid moiety covalenty bonded to a nominal 5µm Zorbax PSM 300 (300Å, porous silica micro-spheres) through Si-O-Si bonds. A trifunctional organosilane reagent is used in producing this packing to maximize bonded-phase stability with aqueous mo-bile phases. Uneven surface coverage can result in mixed mechanisms of separation and poor reproduc-ibility. Therefore, the reaction conditions used to pro-duce Zorbax 300-SCX were specifically developed to minimize stationary phase polymerization and to maximize surface coverage with a monolayer bonded-phase.Zorbax 300-SCX particles provide optimum column ef-ficiency because of their uniform spherical shape, size distribution and proprietary column loading tech-niques. Since column performance is directly related to uniform bed density, Zorbax 300-SCX is offered only in pre-packed, tested columns.Column SpecificationsTypical quality assurance performance for Zorbax 300-SCX packing packed into a 4.6 mm ID x 250 mm column is shown in Figure 1. The chromatographic performance of your column, when quality control tested with an unretained, neutral sample (toluene) and 100% organic mobile phase (Methanol), is de-scribed on the enclosed Column Performance Report. This simple QC test ensures that the column has been properly manufactured. Because of the chemical na-ture of the Zorbax 300-SCX bonded phase, some con-ditions of use may alter the original chromatographic retention properties of the packing material. There-fore, the performance guarantee of this product is lim-ited to the integrity of the packed bed as measured by the QC test.Voids or channels in the packed bed caused by set-tling or shifting of the packing will significantly reduce the chromatographic performance of an unretained compound such as the toluene peak used in the QC test. Therefore, the integrity of the packed bed can be tested at any time usng the QC test condi-tions listed on the enclosed Column Performance Re-port.Safety ConditionsAll points of connection in liquid chromatographic sys-tems are potential sources of leaks. Users of liquid chro-matographic equipment should be aware of the pos-sible toxicity or flammability of mobile phases.Because of its small particle size, dry Zorbax packings are respirable. Columns should only be opened in a well ventilated area.Operational GuidelinesThis column is shipped containing Methanol solvent. Purge with 5 to 10 column volumes of deionized water before using with mobile phases containing salts. The direction of flow is marked on the column.While generally not harmful to the column, reverse flow should be avoided except to attempt removal of inlet pluggage (see Column Care section).Maximum operating pressures for these columns is 400 bar (6000 psi).The use of a guard column is recommended to protect the 300-SCX column and extend its useful lifetime. Avoid use of this column below pH 2.0 or above pH 6.5. Zorbax 300-SCX is compatible with water and all com-mon organic solvents.Maximum operating temperature is 60° C.NOTE: Zorbax columns are designed for high stabilityFIGURE 1Zorbax 300-SCX QA Chromatogram OPERATING CONDITIONSColumn: Zorbax 300-SCX 4.6 mm ID x 250 mm (5 µm)Mobile Phase: 0.2M Sodium Phosphate, pH 3.0Flow Rate: 1.0 mL/minTemperature: Ambient (23°C)Detector: UV (254 nm)Sample Volume: 5 µLPeak Identity:Cytidine - 500 µg/mL024********Retention Time, (min.)Printed in USA 7/14/03Part No. 820625-001 EFor more information on our products, visit our Agilent Technologies home page on the World Wide Web at: /chem/suppliesFor Technical Support in the US and Canada, call 1-800-227-9770 or call your local Agilent sales office.at low pH (e.g., pH < 5). However, all silica-based packings have some solubility in pH > 6 aqueous mo-bile phases. Therefore, when using silica-based columns under conditions of pH > 6, maximum column lifetime is obtained by operation at low temperatures (< 40°C)using low buffer concentrations in the range of 0.01 to 0.02M. Column stability at pH > 6 is also enhanced by avoiding phosphate and carbonate buffers [ref.: H.A.Claessens, M.A. van Straten, and J.J. Kirkland, J.Chromatogr .(A), 728 (1996) 259].ApplicationsZorbax 300-SCX is chromatographically a classical strong cation-exchange packing. Typical applications would include those normally used in separating ba-sic, water soluble compounds. The retention of basic substances is governed by both pH and ionic strength.In general, a decrease in either or both will increase sample retention.Common buffered elements (e.g., citrate, phosphate)can be used. Mobile phase pH should be maintained in the range of 2.0 to 6.5. Since Zorbax 300-SCX is a bonded cation exchanger, organic modifiers (e.g.,methanol) can be used in combination with aqueous solutions to improve sample solubility and effect bet-ter separations. Caution should be taken when using aqueous buffers mixed with organic solvents to ensure that the salts remain solubilized. Additional informa-tion on solvent selection may be found in Chapter 10,Introduction to Modern Liquid Chromatography , Sec-ond Edition, L. R. Snyder and J. J. Kirkland, (John Wiley & Sons, 1979), and Chapter Six, Seven and Eight, Practical HPLC Method Development , Second Edition, L.R. Snyder, J.J. Kirkland, and J.L. Glajch,(John Wiley & Sons, 1997).Since buffer solutions may be relatively viscous, in-creased column efficiency can be obtained by operat-ing at an elevated temperature. Selectivity also may be improved at higher temperatures in some separations.Column CareProprietary column packing techniques produce high-performance columns with homogeneous, dense, and compacted beds. Removal of column end fittings could disturb the beds, possibly leading to reduced column performance and life. To minimize the need to open columns, guard columns and pre-columns are recom-mended to protect the analytical system from block-age by particulate matter in the mobile phase and samples.The inlet frit on these columns has a nominal porosity of 2 µm. Samples that contain particulate matter larger than 2 µm may plug the column inlet frit.Zorbax 300-SCX guard columns and hardware kit are recommended for use with such samples (see Part Numbers).If solvent flow appears to be restricted (high column back-pressure), check first to see that solvent flow is unobstructed up to the column inlet. If the column has the restriction, there may be particulate matter on the inlet frit. An initial attempt should be made toremove an inlet debris by back-flushing 25-30 mL of mobile phase through the column. If this fails to re-turn the column to near its original back-pressure, the inlet frit should be changed. To remove the frit, loosen the nut at the column inlet, taking care not to turn the end fitting itself. Then remove the fitting, taking care not to disturb the column bed. The frit should drop out when the fitting is tapped sharply on a hard surface. Install a new frit and carefully tighten the fit-ting.To clean strongly retained materials from the column,flush the column with stronger eluting solvents. High ionic strength buffered solutions (e.g., 1 M NaCIO 4,pH<4) will remove most strongly retained cationic substances. Flushing the column with 20-30 mL of dis-tilled water then 100 mL of methanol is the recom-mended procedure for removing strongly retained ma-terials of a non-ionic nature. Use caution when mixing organic solvents with buffered aqueous mobile phases to avoid precipitation of salts.Since columns have 1/16-inch terminations, a short 1/4-inch wrench should be used in assembling fittings to prevent overtightening the ferrules. Overtightening can damage the fitting and necessitate replacement.Storage RecommendationsLong term storage of silica-based, bonded phase col-umns should be in a pure organic solvent, preferably an aprotic liquid such as 100% acetonitrile. If the col-umn has been previously used with a buffered mobile phase, the buffer should first be removed by purging the column with 20-30 column volumes of a 50/50mixture of methanol or acetonitrile and water, fol-lowed by 20-30 column volumes of the pure solvent.Before storing the column, the end-fittings should be tightly capped with end-plugs to prevent the packing from drying out.Columns may be safely stored for short periods in most mobile phases. However, to protect equipment, it is desirable to remove salts from the instrument and column by purging the column with the same mobile phase without the buffer (e.g. using 60/40 ACN/H 2O to remove a 60/40 ACN/0.02 M phosphate buffered mo-bile phase). Re-equilibration is rapid with the original mobile phase when using this approach, and any dan-ger of corrosion from the salts is eliminated.Ordering InformationAgilentZorbax 300-SCX Columns (5 µm)Part No.2.1 mm ID x 50 mm 860700-7042.1 mm ID x 150 mm 883700-7043.0 mm ID x 50 mm 860700-3044.6 mm ID x 50 mm 846952-7044.6 mm ID x 150 mm 883952-7044.6 mm ID x 250 mm 880952-7049.4 mm ID x 250 mm880952-204Guard Column4.6 mm ID x 12.5 mm (4 Pack)820950-904Guard Column Hardware Kit 820888-901。

User's GuideSLWU029D–October2006–Revised August2007Contents1Demonstration Kit Configuration Options (3)2Block Diagrams (4)3Key Texas Instruments Components (5)4Software Installation (5)5Software Operation (5)6Board Setup (12)7Demo Kit Test Configuration (13)8Basic Test Procedure (23)9Optional Configurations (27)10Filter Specifications (29)11Bill of Materials and Schematics (30)List of Figures1System Block Diagram (4)2Demo Kit Block Diagram (4)3TSW3003Startup Screen (6)4Default CDCM7005SPI GUI (7)5TRF3761GUI-Main Menu (8)6TRF3761GUI-Advanced Menu (8)7DAC5687GUI (9)8Test System Block Diagram (13)9Single-Carrier Test Mode1WCDMA,Typical Performance With IF=30.72MHz,LO=2.14GHz (15)10Missing Middle-Carrier Test Mode1WCDMA,Typical Performance With IF=30.72MHz,LO=2.14GHz (16)11Four-Carrier Test Mode1WCDMA,Typical Performance With IF=153.6MHz,LO=2.14GHz (17)12ACPR Versus Output Power for1Carrier WCDMA (18)13ACPR Versus Output Power for2Carriers WCDMA (18)14ACPR Versus Output Power for3Carriers WCDMA (19)15ACPR Versus Output Power for4Carriers WCDMA (19)16Optimum ACPR for1Carrier WCDMA,-7-dB Pad (20)17Optimum ACPR for2Carrier WCDMA,-7-dB Pad (21)18Optimum ACPR for3Carrier WCDMA,-7-dB Pad (22)19Optimum ACPR for4Carrier WCDMA,-7-dB Pad (23)20Default DAC GUI With f DAC/8Tone From NCO (25)21Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments (25)22DAC GUI With Typical Settings To Minimize LO and Sideband (26)23Sideband and LO Compensated Using QMC Settings (27)24Board Modifications for External LO (28)25Jumper Settings to Disable TRF3761 (28)26Jumper Changes for External VCXO (29)List of Tables1Frequency Bands (3)2CDCM7005Register Values (7)Windows is a trademark of Microsoft Corporation.SLWU029D–October2006–Revised August2007TSW3003Demonstration Kit1 Submit Documentation Feedback 3Jumper List (12)4Input/Output Connections (12)5Demo Kit Typical Specifications (14)6Frequency Designations (24)7Bill of Materials (30)2TSW3003Demonstration Kit SLWU029D–October2006–Revised August2007Submit Documentation Feedback1Demonstration Kit Configuration Options 1.1DAC Component1.2VComm Configuration1.3VCXO1.4LO Generation Demonstration Kit Configuration OptionsThe TSW3003Demonstration(Demo)Kit can be configured in different ways to evaluate differentcomponents in different frequency bands.This section outlines the various component configurations.Based on the configuration,testing and board setup must be altered to accommodate the givencomponents and features.The TSW3003Demo Kit is built for the DAC5687,although this Demo Kit can also support the DAC5686 because the two devices are pin compatible.The procedures outlined in this document are primarily suited for the DAC5687,but can be modified easily for the DAC5686if desired.The analog quadrature modulator requires a common-mode dc voltage of approximately3.3V.In order to use the dc-offset adjustment capabilities of the DAC5687for carrier suppression,it is imperative tomaintain a dc path from the DAC output to the modulator input.The common-mode voltage for themodulator is maintained with a passive resistor network that is designed to provide the proper operation point for the DAC5687and the TRF3703modulator.By design,in order to preserve the proper dc levels, the DAC coarse gain should be kept at the maximum(15),though deviation by a few steps is generally acceptable with no degradation in performance.The CDCM7005requires a VCXO source to derive its output clock signals.The VCXO is at referencedesignator U1.The frequency of the VCXO can be changed to operate the Demo Kit with differentclocking schemes for different modulation standards or for specific customer requirements.Denote which VCXO frequency is on the board so that the CDCM7005part can be set up properly.The followingconventions are typically used:•WCDMA:Derivatives of61.44MHz(i.e.,122.88MHz,245.76MHz,491.52MHz)•GSM:Derivatives of52MHz(i.e.,104MHz,208MHz)•CDMA2K:Derivatives of78.6432(i.e.,157.2864MHz,314.5728MHz)The integrated VCO of the TRF3761outputs the RF signal used for the LO drive on the analog quadrature modulator.The RF output frequency is contingent on the LO frequency value.The default TRF3761-Htypically has a tuning range from2028to2175MHz.Other frequency bands will require the existingTRF3761to be changed to another pin-compatible part in a different frequency ing the TRF3761 internal divider or another TRF3761part to generate frequencies outside this range requires the output terminations to be changed.Contact TI for support in this situation.The RF frequency band of the VCO must be noted in order to know how to program the TRF3761and at what frequency to measure the output RF signal from the modulator.The typical bands of operation are shown in Table1.Table1.Frequency BandsUMTS PCS GSM900DCS1800 FREQUENCY2110-2170MHz1930-1990MHz935-960MHz1805-1880MHzSLWU029D–October2006–Revised August2007TSW3003Demonstration Kit3 Submit Documentation Feedback2Block Diagrams 2.1System Block Diagram2.2Demo Kit Block DiagramBlock DiagramsThe basic radio system block diagram in Figure 1demonstrates where the TSW3003Demo Kit fits in the overall transceiver.The dash-line box components found on the TSW3003Demo Kit board.Figure 1.System Block DiagramThe basic Demo Kit block diagram is shown in Figure 2.The shaded boxes illustrate the key Texas Instruments components found on the TSW3003Demo Kit board.Figure 2.Demo Kit Block DiagramTSW3003Demonstration Kit4SLWU029D–October 2006–Revised August 2007Submit Documentation Feedback3Key Texas Instruments Components 3.1CDCM70053.2DAC56873.3TRF37033.4TRF37614Software Installation5Software Operation Key Texas Instruments ComponentsThe CDCM7005clock distribution chip is used to generate and synchronize the clock outputs to thesystem.The device has five outputs which can be either LVPECL or LVCMOS and can be divided down by1,2,3,4,6,8,and16.The divide by16can be replaced with a divide by4or8with a90degreephase shift.The DAC5687is a16-bit interpolating dual digital-to-analog converter(DAC).The device incorporates a digital modulator,independent differential offset control,and I/Q amplitude control.The device is typically used in baseband mode or in low IF mode with an analog quadrature modulator.The TRF3703is a direct upconversion IQ modulator.This device accepts a differential input voltagequadrature signal at baseband or low IF frequencies and outputs a modulated RF signal based on the LO drive frequency.The TRF3761is a family of high performance,highly integrated frequency synthesizers,optimized forwireless infrastructure applications.The TRF3761includes an integrated VCO and integer-N PLL.Different members of the TRF3761family can be chosen for application specific VCO frequency ranges.This section summarizes the installation procedures for the software required to operate the Demo Kit.Once all of the software is loaded,it is recommended to reboot the computer.This software has beenverified to be functional on Win2K and WinXP.•Execute setup.exe•Reboot computer as required by the Windows™operating system.•Power up the TSW3003EVM,and plug in the USB cable.•Allow the Windows™operating system to automatically find and install the TSW3003USB drivers.•Start the TSW3003USB Vx.x software.The following describes the use of the software required to set the TSW3003Demo Kit in the baseline configuration for the CDCM7005,TRF3761,and DAC5687.The software should be configured in theorder presented below.The first step requires starting the TSW3003software.This opens a window as shown in Figure3.The tabs on the left side of the window allow selection of different GUI controllers for the and CDCM7005.The lower left portion of the screen contains links to this user's guide as well as the data sheets for the DAC5687,TRF3761,and the CDCM7005.SLWU029D–October2006–Revised August2007TSW3003Demonstration Kit5 Submit Documentation Feedback5.1CDCM7005SoftwareSoftware OperationFigure 3.TSW3003Startup ScreenBy using the provided CDCM7005serial peripheral interface (SPI)software,the user can load settings to the CDCM7005internal registers.This must be performed every time the TSW3003Demo Kit is powered up,because the CDCM7005has default settings that are loaded at power up and the settings may be slightly different than the ones required to operate the Demo Kit.Executing the program brings up the interface seen in Figure 4.The default settings are correct for a VCXO of 491.52MHz and a 10MHz reference as on The CDCM7005GUI allows register settings to be saved and can be loaded back in afterwards.This can be accomplished with the Save and Load Settings buttons near the right side of the GUI.It is recommended that any unused output clocks be tri-stated.In this case the TSW3003only usesOUT_MUX_1to drive the DAC5687.OUT_MUX_0,OUT_MUX_2,OUT_MUX_3,OUT_MUX_4should be tri-stated unless there is a need to use the other output clocks.6TSW3003Demonstration KitSLWU029D–October 2006–Revised August 2007Submit Documentation FeedbackSoftware OperationFigure4.Default CDCM7005SPI GUIThe divider parameters,M and N,are determined according to the following equation based on theinternal reference frequency and internal VCXO frequency.F REF=(F VCXO×M)/(N×P)The p parameter is the VCXO input divider and set through the FB_MUX value.The M and N countervalues need to be adjusted depending on the board configuration.The M and N counter registers aredetermined by the reference frequency and the VCXO frequency.The OUT_MUX sets the divide ratios for the individual output clocks.The OUTSEL determines whether the output clocks will be used assingle-ended CMOS or differential LVPECL.With a10-MHz reference oscillator the CDCM7005settings are shown in Table2for a variety of common VCXO frequencies.A calculator is included in theCDCM7005to calculate the M and N values based on Ref and VCXO frequencies.Table2.CDCM7005Register ValuesVCXO Freq.(MHz)491.52245.76122.8861.44 Divider M125125125125Divider N768768768768FB_MUX8421SLWU029D–October2006–Revised August2007TSW3003Demonstration Kit7 Submit Documentation Feedback Software Operation5.2TRF3761SoftwareThe TRF3761software is used to program the internal PLL chip to lock the integrated VCO onto a desired frequency output.The main menu of the program is shown in Figure5.Figure5.TRF3761GUI-Main MenuThe options in the front panel allow the user to program the desired frequency of the VCO,the desired frequency of the PFD,the reference frequency,and the prescaler selection.The software then displays the actual VCO frequency,PFD frequency and the R,N,A,and B counter values to be programmed into the TRF3761.Hitting the Send button writes these values to the TRF3761.In default mode on a default board,only the desired VCO frequency(2028MHz to2175MHz)needs to be changed.For other VCO ranges,a different member of the TRF3761family needs to be selected and other parameters may need to be changed.The Advanced Operation button will bring up another user interface as shown in Figure6.Figure6.TRF3761GUI-Advanced MenuThis menu allows control of more register settings.For details on these settings,see the TRF3761data8TSW3003Demonstration Kit SLWU029D–October2006–Revised August2007Submit Documentation Feedback5.3DAC5687Software5.4DAC5687GUI Register Descriptions5.4.1Register ControlsSoftware OperationsheetThe register of interest in this menu is the MUXOUT CONTROL which can be used to of LED D4.This mode defaults to Digital PLL Lock Detect and causes the LED D4to light up when the PLL successfully locks.Normally,these menu settings do not need to be changed.If the divider ratios are changed,the TRF3761output termination needs to be modified to accommodate the new output frequency.Otherwise,the performance may be degraded.Contact TI in this situation.By using the provided software,the user can write and read control register information to the DAC5687.Once the Demo Kit is powered on and connected properly,then the GUI shown in Figure 7is displayed with the default settings read from the device.If there is a problem with the such as the Demo Kit is not powered on or the USB cable is not connected,an error message will be displayed instructing the user to correct the problem.Once corrected,hit the Read All button to read the default settings of the device.Figure 7.DAC5687GUIFor normal operation,the user needs only to select values and switches as desired.The values are automatically sent to the device and read back to verify their configuration.•Load Regs –Loads register values from a saved file to the DAC5687and updates the GUI.•Save Regs –Saves current GUI registers settings to a text file for future use.•Read All –Reads the current registers of the DAC5687.This is used to verify settings on the front panel.•Send All –Sends the current front panel registers to the device.This is generally only used when the Demo Kit power has recycled or the device has been reset and the user wants to load the displayed settings to the device.•Load Factory Optimization –Load default LO and sideband optimized values for the default board condition.SLWU029D–October 2006–Revised August 2007TSW3003Demonstration Kit 9Submit Documentation Feedback Software Operation5.4.2Configuration Controls•Full Bypass–When set,all filtering,QMC,and NCO functions are bypassed.•FIR Bypass–Bypass all interpolation filters.QMC INCO functional.Limited to FDAC=250MHz•FIFO Bypass–When set to bypass,the internal four sample FIFO is disabled.When cleared,the FIFO is enabled.•FIR A–A side first FIR filter in high-pass mode when set,low-pass mode when cleared.•FIR B–B side first FIR filter in high-pass mode when set,low-pass mode when cleared.•Dual Clk–Only used when the PLL is disabled.When set,two differential clocks are used to input the data to the chip;CLK1/CLK1C is used to latch the input data into the chip,and CLK2/CLK2C is usedas the DAC sample clock.•Interleave–When set,interleaved input data mode is enabled;both A and B data streams are input at the DA(15:0)input pins.•Inverse Sinc–Enables inverse sinc filter.•Half Rate Input–Enables half rate input mode.Input data for the DAC A data path is input to the chip at half speed using both the DA(15:0)and DB(15:0)input pins.•Sif–Sets sif_4-pin bit.A4-pin serial interface mode is enabled when on,3-pin mode when off.The DAC5687Demo Kit is configured for a3-pin serial interface,so setting to a4-bit serial interface makes reading registers impossible with the GUI.•Inv.PLL Lock–Only used when PLL is disabled and dual clock mode is disabled.When cleared, input data is latched into the chip on rising edges of the PLLLOCK output pin.When set,input data islatched into the chip on falling edges of the PLLLOCK output pin.•PLL Freq–Sets PLL VCO center frequency to low or high center frequency.•PLL Kv–Sets PLL VCO gain to either high or low gain.•Qflag–Sets qflag bit.When set,the QFLAG input pin operates as a B sample indicator when interleaved data is enabled.When cleared,the TXENABLE rising determines the A/B timingrelationship.•2's Comp–When set,input data is interpreted as2's complement.When cleared,input data is interpreted as offset binary.•Rev A Bus–When cleared,DA input data MSB to LSB order is DA(15)=MSB and DA(0)=LSB.When set,DA input data MSB to LSB order is reversed,DA(15)=LSB and DA(0)=MSB.•Rev B Bus–When cleared,DB input data MSB to LSB order is DB(15)=MSB and DB(0)=LSB.When set,DB input data MSB to LSB order is reversed,DB(15)=LSB and DB(0)=MSB.•USB–When set,the data to DACB is inverted to generate upper side band output.•Inv.Clk I(Q)–Inverts the DAC core sample clock when set,normal when cleared.•Sync_Phstr–When set,the internal clock divider logic is initialized with a PHSTR pin low to high transition.•Sync_cm–When set,the coarse mixer is synchronized with a PHSTR low-to-high transition.•Sync_NCO–When set,the NCO phase accumulator is cleared with a phstr low-to-high transition.•Phstr Clk Div Select–Selects the clock used to latch the PHSTR input when restarting the internal clock dividers.When set,the full rate CLK2signal latches PHSTR and when cleared,the divided down input clock signal latches PHSTR.•DAC Serial Data–When set,both DAC A and DAC B input data is replaced with fixed data loaded into the16-bit serial interface DAC Static Data.–Counter Mode–Controls the internal counter that can be used as the DAC data source:{off;all 16b;7b LSBs;5b MIDs;5b MSBs}.–DAC Static Data–When DAC Serial Data is set,both DAC A and DAC B input data is replaced with fixed data loaded with this value.Range=0-65535.•Alt.PLLLOCK Output–Can be used to determine alternate outputs on the PLLLOCK pin when using the internal PLL mode.The EXTLO pin must be open when using this mode.•NCO–When set,enables NCO.–NCO Gain–Sets NCO gain resulting in a2x increase in NCO output amplitude.Except for F s/2 and F s/4mixing NCO frequencies,this selection can result in saturation for full-scale inputs.Consider using QMC gain for lower gains.10TSW3003Demonstration Kit SLWU029D–October2006–Revised August2007Submit Documentation Feedback分销商库存信息: TITSW3003EVM。

1.5A 380KHz 32V Buck LED Constant Current Driver XL3002Featuresn Wide 5V to 32V Input Voltage Range n Output Current Sense Voltage is 0.24V n Minimum Drop Out 0.3Vn Fixed 380KHz Switching Frequency n1.5A Constant Output Current Capability n Internal Optimize Power MOSFET n Excellent line and load regulation n High efficiency up to 96% n TTL shutdown capabilityn EN pin with hysteresis function n Built in thermal shutdown function n Built in current limit function n SOIC-8 packageApplicationsn MR16 LED Lamp n LED LightingGeneral DescriptionThe XL3002 is a 380 KHz fixed frequency PWM buck (step-down) DC/DC converter, capable of driving a 1.5A load with high efficiency, low ripple and excellent line and load regulation. Requiring a minimum number of external components, the regulator is simple to use and include internal frequency compensation and a fixed-frequency oscillator.The PWM control circuit is able to adjust the duty ratio linearly from 0 to 100%. An enable function, an over current protection function is built inside. An internal compensation block is built in to minimize external component count.Figure1. Package Type of XL30021.5A 380KHz 32V Buck LED Constant Current Driver XL3002 Pin ConfigurationsFigure2. Pin Configuration of XL3002 (Top View)Table 1 Pin DescriptionPin Number Pin Name Description1 CS Output constant current sense Pin (CS). The CS reference voltage is 0.24V.2 EN Enable Pin. Drive EN pin low to turn off the device, drive it high to turn it on.3 NC No connected.4 VIN Supply V oltage Input Pin. XL3002 operates from a 5V to 32V DC voltage.5,6 SW Power Switch Output Pin (SW). Output is the switch node that supplies power to the output.7,8 GND Ground Pin.Function BlockFigure3. Function Block Diagram of XL30021.5A 380KHz 32V Buck LED Constant Current Driver XL3002 Typical Application Circuit (MR16 LED Lamp)Figure4. XL3002 Typical Application Circuit (MR16 LED Lamp)Figure5. XL3002 Typical Application Circuit Efficiency1.5A 380KHz 32V Buck LED Constant Current Driver XL3002Figure6. XL3002 Efficiency VS Load current & Input voltage1.5A 380KHz 32V Buck LED Constant Current Driver XL3002Ordering InformationOrder Information Marking ID Package Type Packing Type Supplied AsXL3002E1 XL3002E1 SOIC-8 2500 Units on Tape & ReelAbsolute Maximum Ratings（Note1）Parameter Symbol Value Unit Input Voltage Vin -0.3 to 36 VCS Pin Voltage V CS-0.3 to Vin VEN Pin Voltage VEN -0.3 to Vin VSW Pin Voltage V SW-0.3 to Vin V Power Dissipation P D Internally limited mW Thermal ResistanceR JA100 ºC/W (Junction to Ambient, No Heatsink, Free Air)Operating Junction Temperature T J-40 to 125 ºC Storage Temperature T STG-65 to 150 ºC Lead Temperature (Soldering, 10 sec) T LEAD260 ºC ESD (HBM) 3000 V Note1: Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.1.5A 380KHz 32V Buck LED Constant Current Driver XL3002 XL3002 Electrical CharacteristicsT a = 25℃;unless otherwise specified.Symbol Parameter Test Condition Min. Typ. Max. Unit System parameters test circuit figure4VCS CurrentSenseV oltageVin = 8V to 32V, V out=5VIload=0.3A0.228 0.24 0.252 VEfficiency ŋVin=12V ,V out=9.6VIout=1A- 96 - %Electrical Characteristics (DC Parameters)Vin = 12V, GND=0V, Vin & GND parallel connect a 220uf/25V capacitor; Iout=500mA, T a = 25℃; the others floating unless otherwise specified, system parameters reference figure4.Parameters Symbol Test Condition Min. Typ. Max. Unit Input operation voltage Vin 5 32 V Shutdown Supply Current I STBY V EN=0V 60 200 uAQuiescent Supply Current I q V EN =2V,V FB =Vin2.5 5 mAOscillator Frequency Fosc 304 380 456 KHzEN Pin Threshold V EN High (Regulator ON)Low (Regulator OFF)1.71.1VOutput Power PMOS R DS(ON)V FB=0VI SW=1A150 250 mohm1.5A 380KHz 32V Buck LED Constant Current Driver XL3002 Schottky Diode Selection TableCurrent SurfaceMount ThroughHoleVR (The same as system maximum input voltage)20V 30V 40V 50V 60V √1N5817 1N5818 1N58191A√SS12 SS13 SS14 SS15 SS16 √1N5820 1N5821 1N5822√MBR320 MBR330 MBR340 MBR350 MBR360 √SK32 SK33 SK34 SK35 SK36√30WQ03 30WQ04 30WQ05√31DQ03 31DQ04 31DQ053A√SR302 SR303 SR304 SR305 SR3061.5A 380KHz 32V Buck LED Constant Current Driver XL3002 Package InformationSOP8 Package Mechanical Dimensions。

产品特色大幅简化离线式LED驱动器设计●单级功率因数校正(PFC)与精确恒流(CC)输出相结合●输入/输出电容和变压器体积小●一次侧反馈控制，无需光耦电路，简化了电路设计●简化初级侧PWM调光接口●符合IEC61000-3-2标准高效节能和高兼容性●大幅提升效率，可达到85%以上●减少元件数量●总谐波失真<15%且PF>0.95●前沿、后沿和数字调光器●传感器和定时器精确稳定的性能●LED负载恒流精度不低于±5%●支持LED负载热插拔●1%-100%宽范围调光，调光无闪烁先进的保护及安全特性●通过自动重启动提供短路保护●开路故障检测模式●自动热关断重启动无论在PCB板上还是在封装上，都保证高压漏极引脚与其他所有信号引脚之间满足高压爬电要求应用●LED离线固态照明说明G7617 是一款的适用于LED调光控制的离线式两级交流/直流电源控制器，是适用于25W 输出功率的可调光LED 灯具的最优之选。

G7617符合电磁兼容性(EMC) IEC61000-3-2 标准，在120V AC或230V AC输入电压下其功率因数(PF) 可达到0.95 以上。

采用先进的数控技术来检测调光器的类型和相位，为调光器提供动态阻抗的同时可调节LED发光亮度，自动检测调光器类型和相位，从而实现了业内与模拟及数字调光器最广泛的兼容性。

G7617工作于准谐振工作模式，工作效率高，可工作于前沿后沿调光模式，也可工作于R 型、R-C型或R-L型调光控制模式。

G7617 符合热插拔LED 模块的固态照明行业标准Zhaga，同时还集成了调光功能的映射选项（位于白炽灯替代灯的NEMA SSL6 调光曲线内）。

G7617 系列有两个版本：针对120V AC输入应用进行优化的G7617-00 和针对230V AC 应用进行优化的G7617-01。

订购信息应用框图图1典型应用内部框图Vcc VinVcbVT CFGASU BisenseBdrvFdrvFisensePGNDAGND C O R E图2 内部框图引脚功能描述BV SENSE V IN BI SENSE B DRV CFG ASU V CCV CBV TFV SENSEFI SENSEF DRVAGNDPGND 图3. 引脚布局BV SENSE引脚：PFC电感电压反馈点，用于感知Boost电感的磁通状态。