W3HG128M64EEU-D4ADVANCED*White Electronic Designs1GB – 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMMDESCRIPTIONThe W3HG128M64EEU is a 128Mx64 Double Data Rate2 SDRAM memory module based on 1Gb DDR2 SDRAM components. The module consists of eight 128Mx8, in FBGA package mounted on a 200 pin SO-DI MM FR4 substrate.* T his product is under development, is not qualifi ed or characterized and is subject to change or cancellation without notice.NOTE: C onsult factory for availability of:• Vendor source control options • Industrial temperature optionFEATURES200-pin, Small-Outline DIMM (SO-DIMM), RawCard "B" Fast data transfer rates: PC2-6400*, PC2-5300*,PC2-4200 and PC2-3200 Utilizes 800*, 667*, 533 and 400 Mb/s DDR2SDRAM components V CC = V CCQ = 1.8V ± 0.1V V CCSPD = 1.7V to 3.6VJEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architectureDLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrentoperation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3, 4, 5* and 6* Adjustable data-output drive strength On-Die Termination (ODT)Posted CAS# latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM 64ms: 8,192 cycle refresh Gold edge contacts Single Rank RoHS Compliant JEDEC Package option• 200 Pin (SO-D IMM)• PCB – 29.20mm (1.150") TYPOPERATING FREQUENCIESPC2-6400*PC2-5300*PC2-4200PC2-3200Clock Speed 400MHz 333MHz 266MHz 200MHz CL-t RCD -t RP6-6-65-5-54-4-43-3-3* Consult factory for availabilityW3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsPIN NAMESSYMBOLDESCRIPTION A0 - A13Address inputODT0On-Die Termination CK0, CK0#Differential Clock Inputs CK1, CK1#Differential Clock inputs CKE0Clock Enable input CS0#Chip selectRAS#, CAS#, WE#Command Inputs BA0 - BA2Bank Address Inputs DM0 - DM7Input Data Mask DQ0 - DQ63Data Input/Output DQS0 - DQS7DQS0#-DQS7#Data StrobeSCL Serial Clock for Presence Detect SA0-SA1Presence Detect Address Inputs SDA Serial Presence Detect Data V CC Power SupplyV REF SSTL_18 reference voltage V SS GroundV CCSPD Serial EEPROM Power Supply NCNo ConnectPIN CONFIGURATIONPIN#SYMBOL PIN#SYMBOL PIN#SYMBOL PIN#SYMBOL1V REF51DQS2101A1151DQ422V SS 52DM2102A0152DQ463V SS53V SS 103V CC 153DQ434DQ454V SS 104V CC 154DQ475DQ055DQ18105A10/AP 155V SS 6DQ556DQ22106BA1156V SS 7DQ157DQ19107BA0157DQ488V SS 58DQ23108RAS#158DQ529V SS 59V SS 109WE#159DQ4910DM060V SS 110CS0#160DQ5311DQS0#61DQ24111V CC 161V SS 12V SS 62DQ28112V CC 162V SS 13DQS063DQ25113CAS#163NC 14DQ664DQ29114ODT0164CK115V SS65V SS 115NC 165V SS 16DQ766V SS 116A13166CK1#17DQ267DM3117V CC 167DQS6#18V SS 68DQS3#118V CC 168V SS 19DQ369NC 119NC 169DQS620DQ1270DQS3120NC 170DM621V SS 71V SS 121V SS 171V SS 22DQ1372V SS 122V SS 172V SS 23DQ873DQ26123DQ32173DQ5024V SS74DQ30124DQ36174DQ5425DQ975DQ27125DQ33175DQ5126DM176DQ31126DQ37176DQ5527V SS 77V SS 127V SS 177V SS 28V SS 78V SS 128V SS 178V SS 29DQS1#79CKE0129DQS4#179DQ5630CK080NC 130DM4180DQ6031DQS181V CC 131DQS4181DQ5732CK0#82V CC 132V SS 182DQ6133V SS 83NC 133V SS 183V SS 34V SS 84NC 134DQ38184V SS 35DQ1085BA2135DQ34185DM736DQ1486NC 136DQ39186DQS7#37DQ1187V CC137DQ35187V SS 38DQ1588V CC 138V SS 188DQS739V SS 89A12139V SS 189DQ5840V SS 90A11140DQ44190V SS 41V SS 91A9141DQ40191DQ5942V SS 92A7142DQ45192DQ6243DQ1693A8143DQ41193V SS 44DQ2094A6144V SS 194DQ6345DQ1795V CC 145V SS 195SDA 46DQ2196V CC 146DQS5#196V SS 47V SS 97A5147DM5197SCL 48V SS 98A4148DQS5198SA049DQS2#99A3149V SS 199V CCSPD 50NC 100A2150V SS 200SA1White Electronic DesignsW3HG128M64EEU-D4ADVANCED FUNCTIONAL BLOCK DIAGRAMW3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsRECOMMENDED DC OPERATING CONDITIONSAll voltages referenced to V SSParameter Symbol Min Max Units Notes Supply VoltageV CC 1.7 1.9V -I/O Reference VoltageV REF 0.49 x V CC 0.51 x V CC V 1I/O Termination Voltage (system)V TT V REF - 40V REF + 40mV 2NOTE:1. V REF is expected to equal V CCQ /2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on V REF may not exceed±1 percent of the DC value. Peak-to-peak AC noise on V REF may not exceed ±2 percent of V REF (DC). This measurement is to be taken at the nearest V REF bypass capacitor.2. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equalto V REF and must track variations in the DC level of V REF .ABSOLUTE MAXIMUM DC CHARACTERISTICSSymbol ParameterMin Max Units V CC V CC Supply Voltage Relative to V SS -0.5 2.3V V IN , V OUT Voltage on any Pin Relative to V SS -0.5 2.3V T STG Storage Temperature-55100°C T CASE DDR2 SDRAM Device Operating Temperature*085°C T OPR Operating Temperature (Ambient)065°C I IInput Leakage Current; Any input 0V ≤ V IN ≤ V CC ; V REF input 0V ≤ V IN ≤0.95V; (All other pins not under test = 0V)Command/Address, RAS#, CAS#, WE# S#, CKE-4040µACK, CK#-2020DM-55I OZ Output Leakage Current; 0V ≤ V OUT ≤ V CC Q; DQs and ODT are disabledDQ, DQS, DQS#-55µA I VREFV REF Leakage Current; V REF = Valid V REF level-1616µA* T CASE specifi es as the temperature at the top center of the memory devices.CAPACITANCET A = 25°C, f = 100MHz, V CC = 1.8V, V REF = V SSParameterSymbol Max Unit Input Capacitance (A0-A12)C IN135pF Input Capacitance (RAS#,CAS#,WE#)C IN235pF Input Capacitance (CKE0)C IN331pF Input Capacitance (CK0, CK0#)C IN415pF Input Capacitance (CS0#)C IN531pF Input Capacitance (DQS0#-DQS17#)C IN66pF Input Capacitance (BA0-BA1)C IN735pF Data input/output Capacitance (DQ0-DQ63)C OUT 6pFNOTE:* These capacitance values are based on worst case component values in conjunction with the circuit boards associated parasitic net capacitance.W3HG128M64EEU-D4ADVANCED White Electronic DesignsDDR2 I CC SPECIFICATIONS AND CONDITIONSDDR2 SDRAM components onlyV CC = +1.8V ± 0.1VParameter Symbol Condition806665534403Units Operating one devicebank active-precharge current;I CC0t CK = t CK (I CC), t RC = t RC (I CC), t RAS = t RAS MIN (I CC); CKE is HIGH, CS# isHIGH between valid commands; Address bus inputs are SWITCHING;Data bus inputs are SWITCHING.TBD800640640mAOperating one devicebank active-read-precharge current;I CC1I OUT = 0mA; BL = 4, CL = CL(I CC), AL = 0; t CK = t CK (I CC), t RC = t RC (I CC),t RAS = t RAS MIN (I CC), t RCD = t RCD (I CC); CKE is HIGH, CS# is HIGHbetween valid commands; Address bus inputs are SWITCHING; Datapattern is same as I CC4W.TBD1,160760760mAPrecharge power-down current;I CC2PAll device banks idle; t CK = t CK (I CC); CKE is LOW; Other control andaddress bus inputs are STABLE; Data bus inputs are FLOATING.TBD564040mAPrecharge quiet standby current;I CC2QAll device banks idle; t CK = t CK (I CC); CKE is HIGH, CS# is HIGH; Othercontrol and address bus inputs are STABLE; Data bus inputs areFLOATING.TBD480328280mAPrecharge standby current;I CC2NAll device banks idle; t CK = t CK (I CC); CKE is HIGH, CS# is HIGH; Othercontrol and address bus inputs are SWITCHING; Data bus inputs areSWITCHING.TBD520360280mAActive power-down current;I CC3PAll device banks open; t CK = t CK (I CC); CKE is LOW;Other control and address bus inputs are STABLE;Data bus inputs are FLOATING.Fast PDN ExitMR[12] = 0TBD320240200mASlow PDN ExitMR[12] = 1TBD808080mAActive standby current;I CC3N All device banks open; t CK = t CK(I CC), t RAS = t RAS MAX (I CC), t RP = t RP(I CC);CKE is HIGH, CS# is HIGH between valid commands; Other control andaddress bus inputs are SWITCHING; Data bus inputs are SWITCHING.TBD560400320mAOperating burst write current;I CC4WAll device banks open, Continuous burst writes; BL = 4, CL = CL (I CC),AL = 0; t CK = t CK (I CC), t RAS = t RAS MAX (I CC), t RP = t RP (I CC); CKE isHIGH, CS# is HIGH between valid commands; Address bus inputs areSWITCHING; Data bus inputs are SWITCHING.TBD1,4401,040960mAOperating burst read current;I CC4RAll device banks open, Continuous burst reads, I OUT = 0mA; BL = 4, CL= CL (I CC), AL = 0; t CK = t CK (I CC), t RAS = t RAS MAX (I CC), t RP = t RP (I CC);CKE is HIGH, CS# is HIGH between valid commands; Address businputs are SWITCHING; Data bus inputs are SWITCHING.TBD1,6401,1601,080mABurst refresh current;I CC5t CK = t CK (I CC); Refresh command at every t RFC (I CC) interval; CKEis HIGH, CS# is HIGH between valid commands; Other control andaddress bus inputs are SWITCHING; Data bus inputs are SWITCHING.TBD2,1602,0001,920mASelf refresh current;I CC6CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputsare FLOATING; Data bus inputs are FLOATING.TBD564040mAOperating device bank interleave read current; I CC7All device banks interleaving reads, I OUT= 0mA; BL = 4, CL = CL (I CC),AL = t RCD (I CC)-1 x t CK (I CC); t CK = t CK (I CC), t RC = t RC(I CC), t RRD = t RRD(I CC),t RCD = t RCD(I CC); CKE is HIGH, CS# is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data bus inputsare SWITCHINGTBD2,7202,3602,360mANote:• I CC specifi cation is based on MICRON components. Other DRAM manufacturers specifi cation may be different.W3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsAC OPERATING CONDITIONSV CC = +1.8V ±0.1VC l o c kAC Characteristics Symbol806665534403Units NotesParameterMinMaxMin Max Min Max Min Max Clock cycle timeCL = 6t CK (6)3,0008,000------ps CL = 5t CK (5)3,0008,0003,0008,000----ps 16, 22, 36, 38CL = 4t CK (4)3,0008,0003,7508,0003,7508,0005,0008,000ps CL = 3tCK (3)--5,0008,0005,0008,0005,0008,000psCK high-level width tCH AVG 0.480.520.480.520.480.520.480.52t CK 45CK low-level width tCL AVG0.480.520.480.520.480.520.480.52tCKHalf clock periodtHP MIN (t CH,t CL)MIN (t CH,t CL)MIN (t CH,t CL)MIN (t CH,t CL)ps46C l o c k (A b s o l u t e )Absolute tCk tCK abstCKAVG+(MIN)+tJITPER (MIN)tCKAVG+(MAX)+t JITPER (MAX)tCKAVG+(MIN)+t JITPER (MIN)tCKAVG+(MAX)+t JITPER (MAX)tCKAVG+(MIN)+t JITPER (MIN)tCKAVG+(MAX)+t JITPER (MAX)tCKAVG+(MIN)+t JITPER (MIN)tCKAVG+(MAX)+tJITPER (MAX)psAbsolute CK high-level widthtCH abstCKAVG (MIN)*t CH AVG+t JIT DTY(MIN)tCKAVG (MAX)*t CH AVG+t JIT DTY(MAX)tCKAVG (MIN)*t CH AVG+t JIT DTY(MIN)tCKAVG (MAX)*t CH AVG+t JIT DTY(MAX)tCKAVG (MIN)*t CH AVG+t JIT DTY(MIN)tCKAVG (MAX)*t CH AVG+t JIT DTY(MAX)tCKAVG (MIN)*t CH AVG+t JIT DTY(MIN)tCKAVG (MAX)*t CHAVG+t JIT DTY(MAX)psAbsolute CK low-level widthtCL abstCKAVG (MIN)*tCLAVG(MIN)+t JIT DTY(MIN)t CKAVG (MAX)*tCLAVG (MAX)+t JIT DTY(MIN)t CKAVG (MIN)*t CLAVG (MIN)+t JIT DTY(MIN)t CKAVG (MAX)*t CLAVG (MAX)+t JIT DTY(MIN)t CKAVG (MIN)*t CLAVG (MIN)+t JIT DTY(MIN)t CKAVG (MAX)*t CLAVG (MAX)+t JIT DTY(MIN)t CKAVG(MIN)*t CLAVG(MIN)+tJIT DTY(MIN)tCKAVG(MAX)*t CLAVG(MAX)+t JITDTY(MIN)psC l o c k j i t t e rClock jitter - period tJIT PER-125125-125125-125125-125125ps 39Clock jitter - half period tJIT DUTY -125125-125125-125125-150150ps 40Clock jitter - cycle to cycle tJIT CC250250250250ps 41Cumulative jitter error, 2 cycles t ERR 2per -175175-175175-175175-175175ps 42Cumulative jitter error, 3 cycles t ERR 3per -225225-225225-225225-225225ps 42Cumulative jitter error, 4 cycles t ERR 4per -250250-250250-250250-250250ps 42Cumulative jitter error, 5cycles t ERR 5per-250250-250250-250250-250250ps 42, 48Cumulative jitter error, 6-10 cycles t ERR 6-10per -350350-350350-350350-350350ps 42, 48Cumulative jitter error, 11-50 cyclest ERR 11-50per -450450-450450-450450-450450ps42Note:• AC specifi cation is based on MICRON components. Other DRAM manufactures specifi cation may be different.W3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsAC OPERATING CONDITIONS (continued)V CC = +1.8V ±0.1VD a t aAC Characteristics Symbol806665534403Units Notes ParameterMin Max Min Max Min Max Min Max tQHS-340-340-400-450ps 47DQ output access time from CK/CK#tAC -450+450-450+450-500+500-600+600ps 43Data-out high-impedance window from CK/CK#tHZtAC (MAX)tAC (MAX)tAC (MAX)tAC (MAX)ps 8, 9, 43Data-out low-impedance window from CK/CK#tLZ1tAC (MIN)tAC (MAX)tAC (MIN)tAC (MAX)tAC (MIN)tAC (MAX)tAC (MIN)tAC (MAX)ps 8, 10, 43Data-out low-impedance window from CK/CK#tLZ 22*t AC(MIN)tAC (MAX)2*t AC(MIN)tAC (MAX)2*t AC(MIN)tAC (MAX)2*t AC(MIN)tAC (MAX)ps 8, 10, 43DQ and DM input setup time relative to DQS tDS a300300350400ps 7, 15,19DQ and DM input hold time relative to DQS tDH a 300300350400ps 7, 15, 19DQ and DM input setup time relative to DQS tDS b100100100150ps 7, 15, 19DQ and DM input hold time relative to DQS tDH b175175225275ps7, 15,19DQ and DM input pulse width (for each input)t DIPW0.350.350.350.35tCK37Data hold skew factortQHS340340400450ps 47DQ–DQS hold, DQS to fi rst DQ to go nonvalid, per accesstQHtHP-tQHStHP-tQHStHP-tQHStHP-tQHSps 15, 17, 47Data valid output window (DVW)t DVWt QH - tDQSQ t QH - tDQSQ t QH - tDQSQ t QH- tDQSQns15, 17D a t a S t r o b eDQS input high pulse width t DQSH 0.350.350.350.35t CK 37DQS input low pulse widthtDQSL0.350.350.350.35tCK37DQS output access time from CK/CK#t DQSCK -400+400-400+400-450+450-500+500ps40DQS falling edge to CK rising – setup time t DSS 0.20.20.20.2t CK 37DQS falling edge from CK rising – hold timetDSH0.20.20.20.2tCK37Note:• AC specifi cation is based on MICRON components. Other DRAM manufactures specifi cation may be different.W3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsAC OPERATING CONDITIONS (continued)V CC = +1.8V ±0.1VD a t a S t r o b eAC Characteristics Symbol806665534403Units Notes ParameterMinMax MinMax MinMax MinMax DQS–DQ skew, DQS to last DQ valid, per group, per accesstDQSQ 240240300350ps15, 17DQS read preamble tRPRE 0.9 1.10.9 1.10.9 1.10.9 1.1tCK33, 37, 43DQS read postamble t RPST0.40.60.40.60.40.60.40.6tCK33, 34, 37, 43DQS write preamble setup time tWPRE S 0000ps12, 13,DQS write preamble tWPRE 0.350.350.250.25tCK 37DQS write postambletWPST 0.40.60.40.60.40.60.40.6t CK 11, 37Positive DQS latching edge to associated clock edge tDQSS- 0.25 0.25- 0.25 0.25- 0.25 0.25- 0.25 0.25tCK 37Write command to fi rst DQS latching transition WL-tDQSSWL+tDQSSWL-tDQSSWL+tDQSSWL-tDQSSWL+tDQSSWL-tDQSSWL+tDQSStCK C o m m a n d a n d A d d r e s sAddress and control input pulse width for each input t IPW0.60.60.60.6tCK37Address and control input setup time t IS a 400400500600ps 6, 19Address and control input hold time tIH a 400400500600ps 6, 19Address and control input setup time t IS b200200250350ps6, 19Address and control input hold time tIH b2752753754756, 19CAS# to CAS# command delayt CCD2222tCK37ACTIVE to ACTIVE (same bank) command tRC54555555ns 31, 37ACTIVE bank a to ACTIVE bank b command t RRD (x8)7.57.57.57.5ns 25, 37ACTIVE to READ or WRITE delay tRCD 12151515ns 37Four Bank Activate period tFAW(x8)37.537.537.537.5ns28, 37ACTIVE to PRECHARGE command tRAS 4070,0004070,0004070,0004070,000ns 18, 31,37Internal READ to precharge command delay tRTP 7.57.57.57.5ns 21, 25. 37Write recovery timet WR15151515ns 25, 37Auto precharge write recovery + precharge time tDALtWR + tRPtWR + tRPtWR + tRPtWR + tRPns 20Internal WRITE to READ command delay t WTR 7.57.57.510ns 25, 37PRECHARGE command period tRP12151515ns 29, 37PRECHARGE ALL command period t RPAtRP + tCKtRP + tCKtRP + tCKtRP + tCKns29LOAD MODE command cycle timet MRD 2222tCK37Note:• AC specifi cation is based on MICRON components. Other DRAM manufactures specifi cation may be different.W3HG128M64EEU-D4ADVANCEDWhite Electronic DesignsAC OPERATING CONDITIONS (continued)V CC = +1.8V ±0.1VAC Characteristics Symbol806665534403Units Notes ParameterMinMaxMinMaxMinMaxMinMaxR e f r e s hCKE low to CK,CK# uncertainty tDELAYtIS + tCK + tIH tIS + tCK + tIH tIS + tCK + tIH tIS + tCK + tIHns 26REFRESH to ACTIVE or REFRESH to REFRESH command intervaltRFC 127.570,000127.570,000127.570,000127.570,000ns 14, 37Average periodic refresh interval (commercial)tREFI 7.87.87.87.8µs 14, 37Average periodic refresh interval (industrial)tREFI IT 3.9 3.93.93.9µs 14, 37S e l f R e f r e s hExit self refresh to non-READ command tXSNR t RFC(MIN) + 10t RFC(MIN) + 10t RFC(MIN) + 10t RFC(MIN) + 10nsExit self refresh to READ command tXSRD200200200200tCK37Exit self refresh timing reference tISXR t IS t ISt ISt ISps 6, 27O D TODT turn-on delay t AOND 22222222tCK37ODT turn-on tAOND tAC (MIN)tAC (MAX) + 700)t AC (MIN)tAC (MAX) + 700)t AC (MIN)tAC (MAX) + 1,000)t AC (MIN)tAC (MAX) + 1,000)ps23, 43ODT turn-off delay tAOFD2.52.52.52.52.52.52.52.5tCK35, 37ODT turn-off tAOFtAC (MIN)tAC (MAX + 600)t AC (MIN)tAC (MAX + 600)t AC (MIN)tAC (MAX + 600)t AC (MIN)tAC (MAX + 600)ps 24, 44ODT turn-on (power-down mode)t AONPDtAC (MIN) + 2,000 2 x tCK +tAC (MAX) + 1,000t AC (MIN) + 2,000 2 x tCK +t AC (MAX) + 1,000t AC (MIN) + 2,000 2 x tCK +t AC (MAX) + 1,000t AC (MIN) + 2,0002 x tCK +tAC (MAX)+ 1,000psODT turn-off (power-down mode)t AOFPDtAC (MIN)+ 2,000 2.5 xtCK +tAC (MAX) + 1,000tAC (MIN)+ 2,000 2.5 xtCK +tAC (MAX) + 1,000tAC (MIN)+ 2,000 2.5 xtCK +tAC (MAX) + 1,000tAC (MIN)+ 2,000 2.5 xtCK +tAC (MAX)+ 1,000psODT to power-down entry latency tANPD 3333t CK 37ODT power-down exit latency tAXPD8888tCK37ODT enable from MRS command tMOD 12121212ns37, 49P o w e r D o w nExit active power-down to READ command, MR[bit12=0]t XARD2222tCK37Exit active power-down to READ command, MR[bit12=1]tXARDS 7 - AL 7 - AL 6 - AL 6 - AL 37Exit precharge power-down to any non-READ command.t XP 2222t CK 37CKE minimum high/low timetCKE3333tCK32, 37Note:• AC specifi cation is based on MICRON components. Other DRAM manufactures specifi cations may be different.W3HG128M64EEU-D4ADVANCED* White Electronic DesignsNotes:1. All voltages referenced to VSS.2. Tests for AC timing, I CC, and electrical AC and DC characteristics may be conductedat nominal reference / supply voltage levels, but the related specifi cations anddevice operation are guaranteed for the full voltage range specifi ed. ODT is disabled for all measurements that are not ODT-specifi c.3. Outputs measured with equivalent load:4. AC timing and I CC tests may use a V IL-to-V IH swing of up to 1.0V in the testenvironment and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between V IL (AC) and V IH (AC). Slew rates less than 1.0V/ns require the timing parameters to be derated as specifi ed.5. The AC and DC input level specifi cations are as defi ned in the SSTL_18 standard(i.e., the receiver will effectively switch as a result of the signal crossing the AC inputlevel and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level).6. There are two sets of values listed for Command/Address: t ISa, t IHa and t ISb, t IHb. Thet ISa, t IHa values (for reference only) are equivalent to the baseline values of t ISb, t IHb at V REF when the slew rate is 1V/ns. The baseline values, t ISb, t IHb, are the JEDEC defi ned values, referenced from the logic trip points. t ISb is referenced from V IH (AC) for a rising signal and V IL (AC) for a falling signal, while t IHb is referenced from V IL (DC) for a rising signal and V IH (DC) for a falling signal. If the Command/Address slew rate is not equal to 1 V/ns, then the baseline values must be derated.7. The values listed are for the differential DQS strobe (DQS and DQS#) with adifferential slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed: t DSa. t DHa and t DSb, t DHb. The t DSa, t DHa values (for reference only) are equivalent to the baseline values of t DSb, t DHb at V REF when the slew rate is 2V/ns, differentially. The baseline values, t DSb, t DHb, are the JEDEC-defi ned values, referenced from the logic trip points. t DSb is referenced from V IH (AC) for a rising signal and V IL (AC) for a falling signal, while t DSb is referenced from V IL (DC) for a rising signal and V IH (DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values must be derated. If the DQS differential strobe feature is not enabled, then the DQS strobe is single-ended, the baseline values not applicable, and timing is not referenced to the logic trip points. Single-ended DQS data timing is referenced to DQS crossing V REF.8. t HZ and t LZ transitions occur in the same access time windows as valid datatransitions. These parameters are not referenced to a specifi c voltage level, butspecify when the device output is no longer driving (t HZ) or begins driving (t LZ).9. This maximum value is derived from the referenced test load. t HZ (MAX) will prevailover t DQSCK (MAX) + t RPST (MAX) condition.10. t LZ (MIN) will prevail over a t DQSCK (MIN) + t RPRE (MAX) condition11. The intent of the "Don’t Care" state after completion of the postamble is the DQS-driven signal should either be high, low or High-Z and that any signal transitionwithin the input switching region must follow valid input requirements. That is if DQS transitions high (above V IH DC(min) then it must not transition low (below V IH(DC) prior to t DQSH(min).12. This is not a device limit. The device will operate with a negative value, but systemperformance could be degraded due to bus turnaround.13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITEcommand. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was inprogress, DQS could be HIGH during this time, depending on t DQSS.14. The refresh period is 64ms (commercial) or 32ms (industrial). This equates to anaverage refresh rate of 7.8125µs (commercial) or 3.9607µs (industrial). However, a REFRESH command must be asserted at least once every 70.3µs or t RFC (MAX).To ensure all rows of all banks are properly refreshed, 8,192 REFRESH commands must be issued every 64ms.15. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS withDQ0–DQ7; x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.16. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measureddifferentially).17. The data valid window is derived by achieving other specifi cations - t HP. (t CK/2),t DQSQ, and t QH (t QH = t HP - t QHS). The data valid window derates in directproportion to the clock duty cycle and a practical data valid window can be derived.18. READs and WRITEs with auto precharge are allowed to be issued beforet RAS(MIN) is satisfi ed since t RAS lockout feature is supported in DDR2 SDRAM.19. V IL/V IH DDR2 overshoot/undershoot.20. t DAL = (nWR) + (t RP/t CK). Each of these terms, if not already an integer, should berounded up to the next integer. t CK refers to the application clock period; nWR refers with t WR programmed to four clocks would have t DAL = 4 + (15ns/3.75ns) clocks =4 + (4) clocks = 8 clocks.21. The minimum internal READ to PRECHARGE time. This is the time from the last4-bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command internally latches the READ so that data will output CL later. This parameter is only applicable when t RTP/(2x t CK) > 1, such as frequencies faster than 533 MHz when tRTP = 7.5ns. If tRTP/ (2x t CK) ≤ 1, then equation AL + BL/2 applies. tRAS (MIN) also has to be satisfi ed as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until t RAS(MIN) has been satisfi ed.22. Operating frequency is only allowed to change during self refresh mode, prechargepower-down mode, and system reset condition.23. t DAL = (nWR) + (t RP/t CK): For each of the terms above, if not already an integer,round to the next highest integer. t CK refers to the application clock period;AC Operation Condition Notes: nWR refers to the t WR parameter stored in theMR[11,10,9]. Example: For -533Mb/s at t CK = 3.75 ns with t WR programmed to four clocks. t DAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks.24. ODT turn-off time t AOF (MIN) is when the device starts to turn off ODT resistance.ODT turn off time t AOF (MAX) is when the bus is in high-Z. Both are measured from t AOFD.25. This parameter has a two clock minimum requirement at any t CK.26. t DELAY is calculated from t IS + t CK + t IH so that CKE registration LOW isguaranteed prior to CK, CK# being removed in a system RESET condition.27. t ISXR is equal to t IS and is used for CKE setup time during self refresh exit.28. No more than 4 bank ACTIVE commands may be issued in a given t FAW(min)period. t RRD(min) restriction still applies. The t FAW(min) parameter applies to all 8 bank DDR2 devices, regardless of the number of banks already open or closed. 29. t RPA timing applies when the PRECHARGE(ALL) command is issued, regardlessof the number of banks already open or closed. If a single-bank PRECHARGEcommand is issued, t RP timing applies. t RPA(MIN) applies to all 8-bank DDR2devices.30. Value is minimum pulse width, not the number of clock registrations.31. This is applicable to Read cycles only. Write cycles generally require additional timedue to t WR during auto precharge.32. t CKE (MIN) of 3 clocks means CKE must be registered on three consecutivepositive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of t IS + 2 x t CK + t IH.33. This parameter is not referenced to a specifi c voltage level, but specifi ed when thedevice output is no longer driving (t RPST) or beginning to drive (t RPRE).34. When DQS is used single-ended, the minimum limit is reduced by 100ps.35. The half-clock of t AOFD's 2.5 t CK assumes a 50/50 clock duty cycle. This half-clockvalue must be derated by the amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, t AOFD would actually be 2.5 - 0.03, or 2.47 for t AOF (MIN) and 2.5 + 0.03 or 2.53 for t AOF (MAX).36. The clock’s t CK AVG is the average clock over any 200 consecutive clocks and。
