Agilis AUC_38_series_L_to_C-Band (En)

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０ 引 言
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实验 系统 。
以太 网 ＭＡ Ｃ帧 的发 送 和接 收 由 以太 网控 制
器 实现 。 以太 网控 制器 Ｒ Ｌ ０ ９ Ｓ由 于其 优 良 Ｔ Ｓ １Ａ
关键词பைடு நூலகம்： ＭＡ 帧 检 测 ；以太 网 ； 动 程 序 Ｃ 驱
中 图 分 类 号 ： Ｐ ３ ３ 文献 标 识 码 ： Ｔ ９ Ａ 文 章 编 号 ： ｏ １５ ３ （ ０ ０ ０ － ３ －５ ｌ ｏ ＿ １ ２ １ ） ２０ ６０ ５ ０
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求 和接收 Ａ Ｐ应 答 、 Ｒ Ｒ Ｒ 为 Ａ Ｐ模 块 发 送 ＡＲ Ｐ请 求 和接 收 Ｒ Ｒ Ａ Ｐ应 答 ¨ ； 同时 ， 由器 、 路 网桥 等 中 继设 备也根 据 ＭＡ （ ｄａ ｃｅｓ ｏｔ １帧 中包 Ｃ Ｍｅ ｉ Ａ ｃｓ ｎｒ ） Ｃ ｏ 含 的地址及 协议 类 型 决定 如 何 处 理该 帧 。 因此 ， ＭＡ Ｃ帧是 Ｔ Ｐ Ｉ Ｃ ／Ｐ协 议 族 的 核 心技 术 。 目前 ， 掌 握 以太 网 ＭＡ Ｃ帧 的机 理 是理 解 整 个 以太 网的基

nRF24L01Single chip 2.4 GHz TransceiverFEATURES APPLICATIONS•True single chip GFSK transceiver •Wireless mouse, keyboard, joystick •Complete OSI Link Layer in hardware •Keyless entry•Enhanced ShockBurst™ •Wireless data communication•Auto ACK & retransmit •Alarm and security systems•Address and CRC computation •Home automation•On the air data rate 1 or 2Mbps •Surveillance•Digital interface (SPI) speed 0-8 Mbps •Automotive•125 RF channel operation •Telemetry•Short switching time enable frequency hopping •Intelligent sports equipment•Fully RF compatible with nRF24XX •Industrial sensors•5V tolerant signal input pads •Toys•20-pin package (QFN20 4x4mm)•Uses ultra low cost +/- 60 ppm crystal•Uses low cost chip inductors and 2-layer PCB•Power supply range: 1.9 to 3.6 VGENERAL DESCRIPTIONnRF24L01 is a single chip radio transceiver for the world wide 2.4 - 2.5 GHz ISMband. The transceiver consists of a fully integrated frequency synthesizer, a poweramplifier, a crystal oscillator, a demodulator, modulator and Enhanced ShockBurst™protocol engine. Output power, frequency channels, and protocol setup are easily programmable through a SPI interface. Current consumption is very low, only 9.0mAat an output power of -6dBm and 12.3mA in RX mode. Built-in Power Down andStandby modes makes power saving easily realizable.QUICK REFERENCE DATAUnit Parameter ValueMinimum supply voltage 1.9 VMaximum output power 0 dBmMaximum data rate 2000 kbpsSupply current in TX mode @ 0dBm output power 11.3 mASupply current in RX mode @ 2000 kbps 12.3 mATemperature range -40 to +85 °CSensitivity @ 1000 kbps -85 dBmSupply current in Power Down mode 900 nATable 1 nRF24L01 quick reference dataType NumberDescriptionVersionnRF24L01 20 pin QFN 4x4, RoHS & SS-00259 compliantD nRF24L01 IC Bare DiceD nRF24L01-EVKITEvaluation kit (2 test PCB, 2 configuration PCB, SW)1.0Table 2 nRF24L01 ordering informationBLOCK DIAGRAMDDD=0VD=0V=0VFigure 1 nRF24L01 with external components.PIN FUNCTIONSPin NamePin function Description1 CEDigital InputChip Enable Activates RX or TX mode2 CSN Digital InputSPI Chip Select 3SCK Digital InputSPI Clock4 MOSIDigital InputSPI Slave Data Input5 MISO Digital Output SPI Slave Data Output, with tri-state option6 IRQ Digital Output Maskable interrupt pin7 VDDPowerPower Supply (+3V DC) 8 VSS Power Ground (0V) 9 XC2 Analog Output Crystal Pin 2 10 XC1 Analog Input Crystal Pin 111 VDD_PA Power Output Power Supply (+1.8V) to Power Amplifier 12 ANT1 RF Antenna interface 1 13 ANT2 RFAntenna interface 2 14 VSS Power Ground (0V)15 VDD PowerPower Supply (+3V DC) 16 IREF Analog Input Reference current 17 VSS Power Ground (0V)18 VDD PowerPower Supply (+3V DC)19 DVDD Power Output Positive Digital Supply output for de-coupling purposes 20 VSSPowerGround (0V)Table 3 nRF24L01 pin functionPIN ASSIGNMENTVDDVSSANT2VSSCEVDD_PAANT1CSNMISO MOSI VDDIREFVSSIRQDVDDVSSXC2XC1VDDSCKFigure 2 nRF24L01 pin assignment (top view) for a QFN20 4x4 package.ELECTRICAL SPECIFICATIONSConditions: VDD = +3V, VSS = 0V, T A = - 40ºC to + 85ºCymbol Parameter (condition)NotesMin.Typ.Max. UnitsOperating conditionsVDD Supply voltage1.9 3.0 3.6 V TEMP Operating Temperature-40+27+85ºCDigital input pinV IH HIGH level input voltage 10.7VDD 5.25 VV IL LOW level input voltageVSS 0.3VDD VDigital output pinV OH HIGH level output voltage (I OH =-0.25m A ) VDD- 0.3 VDD VV OL LOW level output voltage (I OL =0.25m A) VSS 0.3 VGeneral RF conditionsf OP Operating frequency22400 2525 MHzf XTAL Crystal frequency16 MHz ∆f 1MFrequency deviation @ 1000kbps ±160 kHz ∆f 2MFrequency deviation @ 2000kbps ±320 kHz R GFSK Data rate ShockBurst™>0 2000 kbps F CHANNEL Channel spacing @ 1000kbps1 MHz F CHANNEL Channel spacing @ 2000kbps2 MHzTransmitter operationP RF Maximum Output Power30 +4 dBmP RFC RF Power Control Range 16 18 20 dB P RFCR RF Power A ccuracy ±4 dB P BW 20dB Bandwidth for Modulated Carrier(2000kbps)1800 2000 kHzP RF1 1st Adjacent Channel Transmit Power 2MHz -20 dBm P RF2 2nd Adjacent Channel Transmit Power 4MHz -50 dBm I VDD Supply current @ 0dBm output power 4 11.3 m AI VDD Supply current @ -18dBm output power 7.0m A I VDD Average Supply current @ -6dBm outputpower, Enhanced ShockBurst™50.05 m AI VDD Supply current in Standby-I mode 632 µA I VDD Supply current in power down900 nA1All digital inputs handle up to 5.25V signal inputs. Keep in mind that the VDD of the nRF24L01 must match theV IH of the driving device for output pins.2 Usable band is determined by local regulations 3Antenna load impedance = 15Ω+j88Ω 4Antenna load impedance = 15Ω+j88Ω. Effective data rate 1000kbps or 2000 kbps 5Antenna load impedance = 15Ω+j88Ω. Effective data rate 10kbps and full packets6Given for a 12pF crystal. Current when using external clock is dependent on signal swing.Receiver operationI VDD Supply current one channel 2000kbps 12.3 mAI VDD Supply current one channel 1000kbps 11.8 mARX SENS Sensitivity at 0.1%BER (@2000kbps) -82 dBm RX SENS Sensitivity at 0.1%BER (@1000kbps) -85 dBm C/I CO C/I Co-channel (@2000kbps) 778/119dB C/I1ST1st Adjacent Channel Selectivity C/I 2MHz 1/4 dB C/I2ND2nd Adjacent Channel Selectivity C/I 4MHz -21/-20 dB C/I3RD3rd Adjacent Channel Selectivity C/I 6MHz -27/-27 dB C/I CO C/I Co-channel (@1000kbps) 10911/1212dB C/I1ST1st Adjacent Channel Selectivity C/I 1MHz 8/8 dB C/I2ND2nd Adjacent Channel Selectivity C/I 2MHz -22/-21 dB C/I3RD3rd Adjacent Channel Selectivity C/I 3MHz -30/-30 dBTable 4 nRF24L01 RF specifications7Data rate is 2000kbps for the following C/I measurements8 According to ETSI EN 300 440-1 V1.3.1 (2001-09) page 279 nRF24L01 equal modulation on interfering signal10Data rate is 1000kbps for the following C/I measurements11 According to ETSI EN 300 440-1 V1.3.1 (2001-09) page 2712 nRF24L01 equal modulation on interfering signalPACKAGE OUTLINEnRF24L01 uses the QFN20 4x4 package, with matt tin plating.Package Type A A1 A3 K D/E e D2/E2 L L1 bSaw QFN20 (4x4 mm) MinTyp.Max0.800.850.950.000.020.050.20REF.0.20min4.0 BSC130.5 BSC2.502.602.700.350.400.450.15max0.180.250.30Figure 3 nRF24L01 Package Outline.13 BSC: Basic Spacing between Centers, ref. JEDEC standard 95, page 4.17-11/APackage marking:Abbreviations: B – Build Code, i.e. unique code for production sites, package type and test platform X – "X" grade, i.e. Engineering Samples (optional) YY – 2 digit Year number WW – 2 digit Week numberLL – 2 letter wafer lot number codeAbsolute Maximum RatingsSupply voltagesVDD............................- 0.3V to + 3.6V VSS..................................................0V Input voltageV I ..................................- 0.3V to 5.25V Output voltageV O .....................................VSS to VDDTotal Power DissipationP D (T A =85°C).............................60mWTemperaturesOperating Temperature…. - 40°C to + 85°C Storage Temperature….… - 40°C to + 125°CNote: Stress exceeding one or more of the limiting values may cause permanent damage to the device.ATTENTION!Electrostatic Sensitive Device Observe Precaution for handling.Glossary of Termsn R FB X2 4 L0 1 Y Y W W L LTerm DescriptionA CKAcknowledgementARTAutoRe-TransmitCE ChipEnableCLK ClockCRC Cyclic Redundancy CheckCSN ChipSelectNOTESB EnhancedShockBurst™ GFSK Gaussian Frequency Shift KeyingIRQ InterruptRequestISM Industrial-Scientific-Medical LNA LowNoiseAmplifierLSB Least Significant BitLSByte Least Significant ByteMbps Megabit per secondMCU Micro Controller UnitMISO Master In Slave OutMOSI Master Out Slave InMSB Most Significant BitMSByte Most Significant BytePCB Printed Circuit BoardPER Packet Error RatePID Packet Identity BitsPLD PayloadPRX PrimaryRXPTX PrimaryTXPWR_DWN PowerDownPWR_UP PowerUpRoHS Restriction of use of Certain Hazardous Substances RX ReceiveRX_DR Receive Data ReadySPI SerialPeripheralInterfaceTX TransmitTX_DS Transmit Data SentTable 5 GlossaryFUNCTIONAL DESCRIPTIONModes of operationThe nRF24L01 can be set in the following main modes depending on the level of the following primary I/Os and configuration registers:Mode PWR_UPregisterPRIM_RXregisterCE FIFOstateRX mode 1 1 1 -TX mode 1 0 1 Data in TX FIFOTX mode 1 0 1Î0 Stays in TX mode until packettransmission is finishedStandby-II 1 0 1 TX FIFO emptyStandby-I 1 - 0 No ongoing packet transmissionPower Down 0 - - -Table 6 nRF24L01 main modesAn overview of the nRF24L01 I/O pins in different modes is given in Table 7.Pin functions in the different modes of nRF24L01Pin Name Direction TX Mode RX Mode Standby Modes Power Down CE Input High Pulse >10µs High Low - CSN Input SPI Chip Select, active lowSCK Input SPIClock MOSI Input SPI Serial InputMISO Tri-stateOutputSPI Serial OutputIRQ Output Interrupt, active lowTable 7 Pin functions of the nRF24L01Standby ModesStandby-I mode is used to minimize average current consumption while maintaining short start up times. In this mode, part of the crystal oscillator is active. In Standby-II mode some extra clock buffers are active compared to Standby-I mode. Standby-II occurs when CE is held high on a PTX device with empty TX FIFO. The configuration word content is maintained during Standby modes. SPI interface may be activated. For start up time see Table 13.Power Down ModeIn power down nRF24L01 is disabled with minimal current consumption. When entering this mode the device is not active, but all registers values available from theSPI interface are maintained during power down and the SPI interface may be activated (CSN=0). For start up time see Table 13. The power down is controlled bythe PWR_UP bit in the CONFIG register.PRELIMINARY PRODUCT SPECIFICATIONnRF24L01 Single Chip 2.4 GHz Radio TransceiverPacket Handling MethodsnRF24L01 has the following Packet Handling Methods: • ShockBurst™ (compatible with nRF2401, nRF24E1, nRF2402 and nRF24E2 with 1Mbps data rate, see page 26) • Enhanced ShockBurst™ShockBurst™ShockBurst™ makes it possible to use the high data rate offered by nRF24L01 without the need of a costly, high-speed microcontroller (MCU) for data processing/clock recovery. By placing all high speed signal processing related to RF protocol on-chip, nRF24L01 offers the application microcontroller a simple SPI compatible interface, the data rate is decided by the interface-speed the micro controller itself sets up. By allowing the digital part of the application to run at low speed, while maximizing the data rate on the RF link, ShockBurst™ reduces the average current consumption in applications. In ShockBurst™ RX, IRQ notifies the MCU when a valid address and payload is received respectively. The MCU can then clock out the received payload from an nRF24L01 RX FIFO. In ShockBurst™ TX, nRF24L01 automatically generates preamble and CRC, see Table 12. IRQ notifies the MCU that the transmission is completed. All together, this means reduced memory demand in the MCU resulting in a low cost MCU, as well as reduced software development time. nRF24L01 has a three level deep RX FIFO (shared between 6 pipes) and a three level deep TX FIFO. The MCU can access the FIFOs at any time, in power down mode, in standby modes, and during RF packet transmission. This allows the slowest possible SPI interface compared to the average data-rate, and may enable usage of an MCU without hardware SPI.Enhanced ShockBurst™Enhanced ShockBurst™ is a packet handling method with functionality that makes bidirectional link protocol implementation easier and more efficient. In a typical bidirectional link, one will let the terminating part acknowledge received packets from the originating part in order to make it possible to detect data loss. Data loss can then be recovered by retransmission. The idea with Enhanced ShockBurst™ is to let nRF24L01 handle both acknowledgement of received packets and retransmissions of lost packets, without involvement from the microcontroller.Nordic Semiconductor ASA Revision: 1.2- Vestre Rosten 81, N-7075 Tiller, Norway-Phone +4772898900-Page 11 of 39Fax +4772898989 March 2006PRELIMINARY PRODUCT SPECIFICATIONnRF24L01 Single Chip 2.4 GHz Radio TransceiverTX3 TX2ipe 4P DataTX4 TX5Data PData PDa taTX1ipe 1PipeFigure 4: nRF24L01 in a star network configuration An nRF24L01 configured as primary RX (PRX) will be able to receive data trough 6 different data pipes, see Figure 4. A data pipe will have a unique address but share the same frequency channel. This means that up to 6 different nRF24L01 configured as primary TX (PTX) can communicate with one nRF24L01 configured as PRX, and the nRF24L01 configured as PRX will be able to distinguish between them. Data pipe 0 has a unique 40 bit configurable address. Each of data pipe 1-5 has an 8 bit unique address and shares the 32 most significant address bits. All data pipes can perform full Enhanced ShockBurst™ functionality. nRF24L01 will use the data pipe address when acknowledging a received packet. This means that nRF24L01 will transmit ACK with the same address as it receives payload at. In the PTX device data pipe 0 is used to received the acknowledgement, and therefore the receive address for data pipe 0 has to be equal to the transmit address to be able to receive the acknowledgement. See Figure 5 for addressing example.t Da a pe Pi 25Frequency Channel Nipe 3TX6Da 0 ipe ta PRXNordic Semiconductor ASA Revision: 1.2- Vestre Rosten 81, N-7075 Tiller, Norway-Phone +4772898900-Page 12 of 39Fax +4772898989 March 2006PRELIMINARY PRODUCT SPECIFICATIONnRF24L01 Single Chip 2.4 GHz Radio TransceiverFigure 5: Example on how the acknowledgement addressing is done An nRF24L01 configured as PTX with Enhanced ShockBurst™ enabled, will use the ShockBurst™ feature to send a packet whenever the microcontroller wants to. After the packet has been transmitted, nRF24L01 will switch on its receiver and expect an acknowledgement to arrive from the terminating part. If this acknowledgement fails to arrive, nRF24L01 will retransmit the same packet until it receives an acknowledgement or the number of retries exceeds the number of allowed retries given in the SETUP_RETR_ARC register. If the number of retries exceeds the number of allowed retries, this will be showed by the STATUS register bit MAX_RT which gives an interrupt. Whenever an acknowledgement is received by an nRF24L01 it will consider the last transmitted packet as delivered. It will then be cleared from the TX FIFO, and the TX_DS IRQ source will be set high. With Enhanced ShockBurst™ nRF24L01 offers the following benefits: • Highly reduced current consumption due to short time on air and sharp timing when operating with acknowledgement traffic • Lower system cost. Since the nRF24L01 handles all the high-speed link layer operations, like re-transmission of lost packet and generating acknowledgement to received packets, it is no need for hardware SPI on the system microcontroller to interface the nRF24L01. The interface can be done by using general purpose IO pins on a low cost microcontroller where the SPI is emulated in firmware. With the nRF24L01 this will be sufficient speed even when running a bi-directional link. • Greatly reduced risk of “on-air” collisions due to short time on air • Easier firmware development since the link layer is integrated on chipNordic Semiconductor ASA Revision: 1.2 - Vestre Rosten 81, N-7075 Tiller, Norway Phone +4772898900 -Page 13 of 39Fax +4772898989 March 2006PRELIMINARY PRODUCT SPECIFICATIONnRF24L01 Single Chip 2.4 GHz Radio TransceiverEnhanced ShockBurst™ Transmitting Payload:1. The configuration bit PRIM_RX has to be low. 2. When the application MCU has data to send, the address for receiving node (TX_ADDR) and payload data (TX_PLD) has to be clocked into nRF24L01 via the SPI interface. The width of TX-payload is counted from number of bytes written into the TX FIFO from the MCU. TX_PLD must be written continuously while holding CSN low. TX_ADDR does not have to be rewritten if it is unchanged from last transmit. If the PTX device shall receive acknowledge, data pipe 0 has to be configured to receive the acknowledgement. The receive address for data pipe 0 (RX_ADDR_P0) has to be equal to the transmit address (TX_ADDR) in the PTX device. For the example in Figure 5 the following address settings have to be performed for the TX5 device and the RX device: TX5 device: TX_ADDR = 0xB3B4B5B605 TX5 device: RX_ADDR_P0 = 0xB3B4B5B605 RX device: RX_ADDR_P5 = 0xB3B4B5B605 3. A high pulse on CE starts the transmission. The minimum pulse width on CE is 10 µs. 4. nRF24L01 ShockBurst™: • Radio is powered up • 16 MHz internal clock is started. • RF packet is completed (see the packet description) • Data is transmitted at high speed (1 Mbps or 2 Mbps configured by MCU). 5. If auto acknowledgement is activated (ENAA_P0=1) the radio goes into RX mode immediately. If a valid packet has been received in the valid acknowledgement time window, the transmission is considered a success. The TX_DS bit in the status register is set high and the payload is removed from TX FIFO. If a valid acknowledgement is not received in the specified time window, the payload is resent (if auto retransmit is enabled). If the auto retransmit counter (ARC_CNT) exceeds the programmed maximum limit (ARC), the MAX_RT bit in the status register is set high. The payload in TX FIFO is NOT removed. The IRQ pin will be active when MAX_RT or TX_DS is high. To turn off the IRQ pin, the interrupt source must be reset by writing to the status register (see Interrupt chapter). If no acknowledgement is received for a packet after the maximum number of retries, no further packets can be sent before the MAX_RX interrupt is cleared. The packet loss counter (PLOS_CNT) is incremented at each MAX_RT interrupt. I.e. ARC_CNT counts the number of retries that was required to get a single packet through. PLOS_CNT counts the number of packets that did not get through after maximum number of retries. 6. The device goes into Standby-I mode if CE is low. Otherwise next payload in TX FIFO will be sent. If TX FIFO is empty and CE is still high, the device will enter Standby-II mode. 7. If the device is in Standby-II mode, it will go to Standby-I mode immediately if CE is set low.Enhanced ShockBurstTM Receive Payload:1. RX is selected by setting the PRIM_RX bit in the configuration register to high. All data pipes that shall receive data must be enabled (EN_RXADDR register),Nordic Semiconductor ASA Revision: 1.2 - Vestre Rosten 81, N-7075 Tiller, Norway Phone +4772898900 Fax +4772898989 March 2006Page 14 of 39PRELIMINARY PRODUCT SPECIFICATIONnRF24L01 Single Chip 2.4 GHz Radio Transceiver2. 3. 4.5. 6. 7. 8.auto acknowledgement for all pipes running Enhanced ShockBurst™ has to be enabled (EN_AA register), and the correct payload widths must be set (RX_PW_Px registers). Addresses have to be set up as described in item 2 in the Enhanced ShockBurst™ transmit payload chapter above. Active RX mode is started by setting CE high. After 130µs nRF24L01 is monitoring the air for incoming communication. When a valid packet has been received (matching address and correct CRC), the payload is stored in the RX-FIFO, and the RX_DR bit in status register is set high. The IRQ pin will be active when RX_DR is high. RX_P_NO in status register will indicate what data pipe the payload has been received in. If auto acknowledgement is enabled, an acknowledgement is sent back. MCU sets the CE pin low to enter Standby-I mode (low current mode). MCU can clock out the payload data at a suitable rate via the SPI interface. The device is now ready for entering TX or RX mode or power down mode.Two way communication with payload in both directionsIf payload shall be sent in both directions, the PRIM_RX register must be toggled by redefining the device from PRX to PTX or vice versa. The controlling processors must handle the synchronicity between a PTX and a PRX. Data buffering in both RX FIFO and TX FIFO simultaneously is possible, but restricted to data pipes 1 to 5. The third level in TX FIFO shall only be written in RX, TX or Standby-II mode if data is stored in RX FIFOAuto Acknowledgement (RX)The auto acknowledgement function reduces the load of the external microcontroller, and may remove the need for dedicated SPI hardware in a mouse/keyboard or comparable systems, and hence reduce cost and average current consumption. Auto acknowledgement can be configured individually for each data pipe via the SPI interface. If auto acknowledgement is enabled and a valid packet (correct data pipe address and CRC) is received, the device will enter TX mode and send an acknowledgement packet. After the device has sent the acknowledgement packet, normal operation resumes, and the mode is determined by the PRIM_RX register and CE pin.Auto Re-Transmission (ART) (TX)An auto retransmission function is available. It will be used at the TX side in an auto acknowledgement system. In the SETUP_RETR register it will be possible to state how many times the data in the data register will be resent if data is not acknowledged. After each sending, the device will enter RX mode and wait a specified time period for acknowledgement. When the acknowledgement packet is received, the device will return to normal transmit function. If there is no more unsent data in the TX FIFO and the CE pin is low, the device will go into Standby-I mode. If the acknowledgement is not received, the device will go back to TX mode and resend the data. This will continue until acknowledgment is received, or a time out occursNordic Semiconductor ASA Revision: 1.2 - Vestre Rosten 81, N-7075 Tiller, Norway Phone +4772898900 Fax +4772898989 March 2006Page 15 of 39PRELIMINARY PRODUCT SPECIFICATIONnRF24L01 Single Chip 2.4 GHz Radio Transceiver(i.e. the maximum number of sending is reached). The only way to reset this is to set the PWR_UP bit low or let the auto retransmission finish. A packet loss counter will be incremented each time a packet does not succeed to reach the destination before time out. (Time out is indicated by the MAX_RT interrupt.) The packet loss counter is reset when writing to the RF channel register.Packet Identity (PID) and CRC used by Enhanced ShockBurstTMEach packet contains a two bit wide PID field to detect if the received packet is new or resent. The PID will prevent that the PRX device presents the same payload more than once to the microcontroller. This PID field is incremented at the TX side for each new packet received via the SPI interface. The PID and CRC field is used by the PRX device to determine whether a packet is resent or new. When several data is lost on the link, the PID fields may in some cases become equal to last received PID. If a packet has the same PID as the previous packet, nRF24L01 will compare the CRC sums from both packets. If they also are equal, the last received packet is considered as a copy of the previous and is discarded. 1: PRX device: The PRX device compares the received PID with the last PID. If the PID fields are different, the packet is considered to be new. If the PID is equal to last received PID, the received packet might be the same as last time. The receiver must check if the CRC is equal to the previous CRC. If the CRC is equal to the previous one, the packet is probably the same, and will be discarded. 2: PTX device: The transmitter increments the PID field each time it sends a new packet.TX side functionalityStartRX side functionalityStartNew packet from MCU?YesPID equal last PID?YesCRC equal last CRC?increment PID No No New packet is valid for MCUYes NoDiscard packet as a copyEndEndFigure 6 PID generation/detectionNordic Semiconductor ASA Revision: 1.2 - Vestre Rosten 81, N-7075 Tiller, Norway Phone +4772898900 Fax +4772898989 March 2006Page 16 of 39PRELIMINARY PRODUCT SPECIFICATIONnRF24L01 Single Chip 2.4 GHz Radio TransceiverThe length of the CRC is configurable through the SPI interface. It is important to notice that the CRC is calculated over the whole packet including address, PID and payload. No packet is accepted as correct if the CRC fails. This is an extra requirement for packet acceptance that is not illustrated in the figure above.Stationary Disturbance Detection – CDCarrier Detect (CD) is set high when an in-band RF signal is detected in RX mode, otherwise CD is low. The internal CD signal is filtered before presented to CD register. The internal CD signal must be high for at least 128µs. In Enhanced ShockBurst™ it is recommended to use the Carrier Detect functionality only when the PTX device does not succeed to get packets through, as indicated by the MAX_RT interrupt for single packets and by the packet loss counter (PLOS_CNT) if several packets are lost. If the PLOS_CNT in the PTX device indicates to high rate of packet losses, the device can be configured to a PRX device for a short time (Tstbt2a + CD-filter delay = 130µs+128µs = 258µs) to check CD. If CD was high (jam situation), the frequency channel should be changed. If CD was low (out of range), it may continue on the same frequency channel, but perform other adjustments. (A dummy write to the RF_CH will clear the PLOS_CNT.)Data PipesnRF24L01 configured as PRX can receive data addressed to 6 different data pipes in one physical frequency channel. Each data pipe has its own unique address and can be configured to have individual behavior. The data pipes are enabled with the bits in the EN_RXADDR register. By default only data pipe 0 and 1 are enabled. The address for each data pipe is configured in the RX_ADDR_Px registers. Always ensure that none of the data pipes have the exact same address. Data pipe 0 has a unique 40 bit configurable address. Data pipes 1-5 share the 32 most significant address bits and have only the LSByte unique for each data pipe. Figure 7 shows an example of how data pipes 0-5 are addressed. All pipes can have up to 40 bit address, but for pipe 1-5 only the LSByte is different, and the LSByte must be unique for all pipes.Nordic Semiconductor ASA Revision: 1.2- Vestre Rosten 81, N-7075 Tiller, Norway-Phone +4772898900-Page 17 of 39Fax +4772898989 March 2006PRELIMINARY PRODUCT SPECIFICATIONnRF24L01 Single Chip 2.4 GHz Radio TransceiverByte 4 Data pipe 0 (RX_ADDR_P0) Data pipe 1 (RX_ADDR_P1) Data pipe 2 (RX_ADDR_P2) Data pipe 3 (RX_ADDR_P3) Data pipe 4 (RX_ADDR_P4) Data pipe 5 (RX_ADDR_P5) 0xE7 0xC2 0xC2 0xC2 0xC2 0xC2 Byte 3 0xD3 0xC2 0xC2 0xC2 0xC2 0xC2 Byte 2 0xF0 0xC2 0xC2 0xC2 0xC2 0xC2 Byte 1 0x35 0xC2 0xC2 0xC2 0xC2 0xC2 Byte 0 0x77 0xC2 0xC3 0xC4 0xC5 0xC6Figure 7: Addressing data pipes 0-5 When a packet has been received at one of the data pipes and the data pipe is setup to generate acknowledgement, nRF24L01 will generate an acknowledgement with an address that equals the data pipe address where the packet was received. Some configuration settings are common to all data pipes and some are individual. The following settings are common to all data pipes: • CRC enabled/disabled (CRC always enabled when ESB is enabled) • CRC encoding scheme • RX address width • Frequency channel • RF data rate • LNA gain • RF output powerNordic Semiconductor ASA Revision: 1.2- Vestre Rosten 81, N-7075 Tiller, Norway-Phone +4772898900-Page 18 of 39Fax +4772898989 March 2006。

Agilent 34950A64-Bit Digital I/O and Counter Module User’s GuideAgilent Technologies, Inc.Printed in MalaysiaEdition 1June 2008 E0608*34980-90050* 34980-90050Notices© Agilent Technologies, Inc. 2008No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or transla-tion into a foreign language) without prior agreement and written consent from Agilent Technologies, Inc. as governedby United States and international copy-right laws.Manual Part Number34980-90050EditionFirst Edition, June 2008Printed in MalaysiaAgilent Technologies, Inc.3501 Stevens Creek BlvdSanta Clara, CA 95052 USAMicrosoft® and Windows® are U.S. regis-tered trademarks of Microsoft Corporation. Software RevisionThis guide is valid for the firmware that was installed in the instrument at the time of manufacture. However, upgrading the firmware may add or change product features. For the latest firmware and documentation, go to the product page at: /find/34980A WarrantyThe material contained in this docu-ment is provided “as is,” and is sub-ject to being changed, without notice,in future editions. Further, to the max-imum extent permitted by applicablelaw, Agilent disclaims all warranties,either express or implied, with regardto this manual and any informationcontained herein, including but notlimited to the implied warranties ofmerchantability and fitness for a par-ticular purpose. Agilent shall not beliable for errors or for incidental orconsequential damages in connectionwith the furnishing, use, or perfor-mance of this document or of anyinformation contained herein. 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It calls attention to an operat-ing procedure, practice, or the likethat, if not correctly performed oradhered to, could result in damageto the product or loss of importantdata. Do not proceed beyond aCAUTION notice until the indicatedconditions are fully understood andmet.A WARNING notice denotes ahazard. It calls attention to anoperating procedure, practice, orthe like that, if not correctly per-formed or adhered to, could resultin personal injury or death. Do notproceed beyond a WARNINGnotice until the indicated condi-tions are fully understood and met.ii A gilent 34950A 64-Bit Digital I/O and Counter Module User’s GuideAdditional Safety NoticesThe following general safety precautions must be observed during all phases of oper-ation of this instrument. Failure to comply with these precautions or with specific warnings or instructions elsewhere in this manual violates safety standards of design, manufacture, and intended use of the instrument. Agilent Technologies assumes no liability of the customer’s failure to com-ply with the requirements.GeneralDo not use this products in any manner not specified by the manufacturer. The protec-tive features of this product may be impaired if it is used in a manner not speci-fied in the operation instructions. Before Applying PowerVerify that all safety precautions are taken. Make all connections to the unit before applying power.Ground the InstrumentThis product is provided with protective earth terminals. To minimize shock hazard, the instrument must be connected to the ac power mains through a grounded power cable, with the ground wire firmly con-nected to an electrical ground (safety ground) at the power outlet. Any interrup-tion of the protective (grounding) conduc-tor or disconnection of the protective earth terminal will cause a potential shock haz-ard that could result in personal injury. Do Not Operate in an Explosive AtmosphereDo not operate the instrument in the pres-ence of flammable gases or fumes.Do Not Remove the Instrument CoverOnly qualified, service-trained personal who are aware of the hazards involved should remove instrument covers. Always disconnect the power cable and any exter-nal circuits before removing the instrument cover. Do Not Modify the InstrumentDo not install substitute parts or performany unauthorized modification to the prod-uct. Return the product to an Agilent Salesand Service Office for service and repair toensure that safety features are maintained.In Case of DamageInstruments that appear damaged or defec-tive should be made inoperative andsecured against unintended operation untilthey can be repaired by qualified servicepersonnel.Safety SymbolsWaste Electrical and ElectronicEquipment (WEEE) Directive2002/96/ECThis product complies with the WEEEDirective (2002/96/EC) marking require-ment. The affixed product label (see above)indicates that you must not discard thiselectrical/electronic product in domestichousehold waste.Product Category: With reference to theequipment types in the WEEE directiveAnnex 1, this product is classified as a“Monitoring and Control instrumentation”product.To return unwanted products, contactyour local Agilent office, or go to/environment/productfor more information.Technical SupportIf you have questions about your shipment,or if you need information about warranty,service, or technical support, contactAgilent Technologies:In the United States: (800) 829-4444In Europe: 31 20 547 2111In Japan: 0120-421-345Or go to /find/assistfor information on contacting Agilent inyour country of specific location. You canalso contact your Agilent TechnologiesRepresentative.Alternating currentFrame or chassisterminalStandby supply. Unit isnot completelydisconnected from acmains when switch is offCaution, risk of electricshockCaution, refer toaccompanying descriptionAgilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide iiiThe Declaration of Conformity(DoC) for the 34980A mainframe instrument can be found on page iii in the 34980A Mainframe User’s Guide. That DoC applies to the 34980A mainframe and all available plug-in modules.Contents34950A 64-Bit Digital I/O Module with Memory and Counter . . . . . . . . . . .. . . . . . . . . . . .1 Bank and Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .1Electrical Characteristics for Digital I/O Lines . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .2Operating Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .2Basic Digital I/O Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .3 Channel Numbering and Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .3Reading Digital Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .4Writing Digital Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .5Channel Width and Polarity, Threshold, Level, and Drive . . . . . . . . . . . .. . . . . . . . . . . .6 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .7 Setting the Handshake Line Parameters . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .8Synchronous Handshake Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .9Buffered I/O Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .14 Buffered (Memory) Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .14Deleting Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .16Buffered (Memory) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .16 Interrupt Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .18 Memory Output Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .18Memory Input Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .19 Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .20Pattern Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .21Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .22 Totalizer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .22Initiated Measurement Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .23Threshold Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .2434950A D-Sub Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .2534950T Terminal Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .2734950A 64-Bit Digital I/O Module with Memory and Counter34950A 64-Bit Digital I/O Module with Memory and CounterThe 34950A has 64-bits of general-purpose digital I/O grouped in 8-bitchannels with programmable polarity, input thresholds, and output levels.The module is segmented into two banks of four 8-bit channels. Each bankhas 64 Kb of volatile memory for pattern capture and pattern generationwith hardware interrupt capability. Up to three pins of handshaking areavailable for each bank of 32 bits.The module also has two 10 MHz frequency counter/totalizer measurementinput channels and a programmable clock output for frequencysynchronization or general clocking needs.Bank and Channel AssignmentsThe digital channels are numbered by bank; 101 through 104 and 201through 204 for banks 1 and 2 respectively. The counter/totalizer channelsare assigned channel numbers 301 and 302. The programmable clock is not34950A 64-Bit Digital I/O Module with Memory and CounterElectrical Characteristics for Digital I/O LinesThe following simplified schematic shows the interface circuitry and specifications for each of the 64 digital I/O lines:Operating ConsiderationsSee the Introduction to the Plug In Modules chapter of the 34980A Mainframe User’s Guide for detailed environmental operating conditions for the 34980A mainframe and its installed modules. That guidance sets maximum per channel current and power ratings at rated voltage for pollution degree 1 (dry) and pollution degree 2 (possible condensation) conditions, for the Digital I/O module.Active Drive:V in 0V – 5VV out (L) 0.24V < V out < 0.55V 4mA < I out < 24mA V out (H)1.6V < V out < 5V -4mA < I out < -24mAOpen Collector:V out0V – 5V-4 mA < I out < -24mA V cc (< 2V)V cc (> 2V)215 Ω < R pullup < 1 k Ω215 Ω < R pullup < 10 k ΩBasic Digital I/O Operations Basic Digital I/O OperationsChannel Numbering and WidthThe digital channels are numbered by bank; 101 through 104 and 201through 204 for banks 1 and 2 respectively.Using SCPI commands you can group digital I/O channels together toallow 16- or 32-bit operations. The first and third channels on a bank canbe control channels. Width and direction of the memory operations arecontrolled by the width and direction of the first channel on the bank(i.e., 101 or 201). In the SCPI language for the 34950A, BYTE refers to8-bit operations, WORD refers to 16-bit operations, and LWORd refers to32-bit operations.This table illustrates how the channels are numbered for each operatingconfiguration.Bank 1Bank 2ChannelBYTE (default)1011021031042012022032048-bits8-bits8-bits8-bits8-bits8-bits8-bits8-bitsWORD10110320120316-bits16-bits16-bits16-bitsLWORd10120132-bits32-bitsBasic Digital I/O OperationsReading Digital DataThe simplest way to read a digital channel is using the MEASure:DIGital?query. This query sets the channel to be an input channel and sets allother channel parameters to the default settings.For example, sending the following SCPI command to a Digital I/O moduleinstalled in slot 1 of the mainframe will read the value of the 8-bitchannel 102. An unsigned integer value is returned that represents thestate of the 8 bits on channel 102.MEAS:DIG? BYTE, (@1102)By adding parameters to the command, you can set the channel width,polarity, and threshold for read. For example, sending the following SCPIcommand you can read the 32-bit channel 201.MEAS:DIG? LWOR, (@1201)To read digital data with more control over the channel parameters,use the SCPI CONFigure and SENSe commands. The CONFigure commandsset up the digital I/O channel parameters. For example, sending thefollowing SCPI command to a Digital I/O module installed in slot 1 of themainframe, sets a 16-bit input channel (103) to use a 2.5 V inputthreshold, and normal polarity.CONF:DIG WORD, 2.5, NORM, (@1103)Once configured, the data is read using the following command.SENS:DIG:DATA:WORD? (@1103)You may also read an individual bit using the SENSe commands.This allows you to check the state of an individual bit in a channelwithout having to create an input mask. For example, the followingcommand returns the state of bit 3 in the channel 101 byte.SENS:DIG:DATA:BIT? 3, (@1101)The acceptable range for the bit parameter is based on the channel widthas shown below:•BYTE (8-bit): <bit> can range from ‘0’ to ‘7’•WORD (16-bit): <bit> can range from ‘0’ to ‘15’•LWORd (32-bit): <bit> can range from ‘0’ to ‘31’The SENSe command differs from the MEASure command in that it will notchange the direction (input or output) of the channel. If the channel isconfigured as an output, the SENSe command will return the value beingdriven.Basic Digital I/O OperationsWriting Digital DataTo write digital data, set the channel output parameters using the SOURcecommands. For example, sending the following SCPI commands to a DigitalI/O module in slot 1 sets a 32-bit channel to use normal polarity,with active drive and a ‘set’ output voltage of 4 volts.CONF:DIG:WIDT LWOR,(@1201)CONF:DIG:POL NORM,(@1201)SOUR:DIG:DRIV ACT,(@1201)SOUR:DIG:LEV 4,(@1201)The width and polarity parameters apply to both input and output operations.You can set a channel to output in either active drive or open collectorconfigurations. When set to ACTive, the module drives the digital lines for bothhigh and low. The voltage level that represents a logic ‘1’ can be set using theSOURce:DIGital:LEVel command. Output voltages can range from 0.80 V(default) to 5 V.When the channel is set to OCOLlector, lines are driven low, but set to highimpedance (Hi-Z) when asserted. In the open collector mode, multiple linescan be connected together by providing external pull-ups.When using external pull-ups in the open collector mode, the outputs willnot exceed 5 V.Once a channel has been configured, write digital data to the channel using theSOURce:DIGital:DATA command.SOUR:DIG:DATA:LWOR 26503,(@1201)You may also use a hexadecimal format to represent values in the commands.For example, to send the decimal value of 26503 in hex use the command form:SOUR:DIG:DATA:LWOR #h6787,(@1201)Writing to a channel automatically configures the channel as an output.Note that the data should match the channel width configured usingCONFigure:DIGital:DATA:WIDTh command. The data written is maskedby the configured width so that any extra bytes will be discarded.For example: sending the value 65531 to a byte wide channel will resultin the channel discarding the upper byte and outputting 251.Basic Digital I/O OperationsChannel Width and Polarity, Threshold, Level, and DriveWhen the width of a channel is set to WORD or LWORd, the channeldirection (input or output) of the channels spanned by the width iscontrolled by the channel in operation. That is, all grouped channels areautomatically set to the same input or output operation.Channel settings of polarity, threshold, level, and drive mode areunchanged when channels are combined. For example, consider thefollowing command sequence.CONF:DIG:POL NORM,(@1101)CONF:DIG:POL INV,(@1102)CONF:DIG:WIDT WORD,(@1101)This command sequence set the first 8 bits (channel 101) to normalpolarity for input and output operations, set the next 8 bits (channel 102)to inverted polarity, and then combines the bits into a 16-bit channel.When this WORD channel is used, the first eight bits will input or outputusing normal polarity but the next 8 bits will read or written usinginverted polarity.Threshold, level, and drive settings all behave in the same manner as thepolarity setting described above.HandshakingHandshakingHandshaking provides a means to synchronize the input or output ofdigital data. By default, no handshaking is used; data is input or output as the command is executed. The handshake is configured per bank.The 34950A provides a synchronous handshake mode (strobe handshake). You can use this mode with basic input and output operations. You must use this handshake mode to use buffered I/O (see “Buffered I/OOperations” on page 14).The handshake is performed using three lines on each bank. The lines are labeled H0, H1, and H2. The function of each line is set by the input or output mode in use. Since there are only three handshake lines per bank, the SCPI handshake commands are only valid for the first channel in a bank. Once handshaking is enabled, it applies to the width of the first channel in the bank.The three handshaking lines on each bank also differ slightly if you are using buffered (memory) I/O (see page 14) or unbuffered I/O operations. You can also perform unbuffered operations without any handshake. The function of each line for each mode of operation is defined in the table below.The following handshake command sets the synchronous handshaking mode for the channels in bank 1.CONF:DIG:HAND SYNC, (@1101)This form of the handshaking command also allows you to optionally set the input threshold, output drive level, and polarity of all the handshake lines. For example, the following command sets bank 2 to use synchronous handshaking, with an input threshold of 2.5 V, an output drive level of2.5 V, and normal polarity. Other parameters such as the handshake timing are set to default values (refer to the Programmer’s Reference Help file for details ).CONF:DIG:HAND SYNC, 2.5, 2.5, NORM, (@1201)H0H1H2Unbuffered Synchronous Input I/O Direction (output)Strobe (output)Not Used (Hi-Z)Unbuffered SynchronousOutputI/O Direction (output)Strobe (output)Not Used (Hi-Z)Buffered Synchronous Input Start/Stop (output)Not Used (Hi-Z)Input Strobe (input)Buffered Synchronous Output (internal clock)Start/Stop (output)Strobe (output)Not Used (Hi-Z)Buffered Synchronous Output (external clock)Start/Stop (output)Not Used (Hi-Z)Output Strobe (input)HandshakingYou can set parameters by using a sequence of commands instead of theCONFigure macro command. For example, the following command sequencesets the handshaking mode to synchronous, the output drive to opencollector, and the handshake rate to 1 MHz.CONF:DIG:HAND:MODE SYNC, (@1101)CONF:DIG:HAND:DRIV OCOL, (@1101)CONF:DIG:HAND:RATE 1000000, (@1101)Setting the Handshake Line ParametersYou can set the handshake lines’ input threshold, output drive mode, andoutput drive voltage. These settings affect all the handshake lines in thebank. Handshake line polarity can be set for each individual handshakeline.For example, you can invert the polarity of the handshake line H1 onbank 2 with the following command.CONF:DIG:HAND:POL INV, H1, (@1201)You can set the output drive mode, output voltage, and input threshold forall handshake lines in each bank. For example, the following commands setthe drive mode to active, the drive voltage to 4.5 V, and the inputthreshold to 1.0 V on bank 2.CONF:DIG:HAND:DRIV ACT, (@1201)SOUR:DIG:HAND:LEV 4.5, (@1201)SENS:DIG:HAND:THR 1, (@1202)The settings for drive mode, output drive level, and input threshold alsoapply to the bank’s interrupt line.When using external pull-ups in the open collector mode, the outputs willnot exceed 5 V.HandshakingSynchronous Handshake ModeIn the synchronous handshake mode, a strobe or clock signal is used totransfer data to or from an external device. The strobe line (H1) is anoutput and is pulsed once for each transfer.Synchronous Unbuffered InputsFor synchronous handshake unbuffered inputs the H0 line indicates thedirection of the transfer. This line is set high to indicate an inputoperation. The H0 line will remain in the high state until the 34950Adirection is changed. The H1 line is the strobe output line. The H2 line isnot used and is set to high impedance.The timing of the input operation is controlled by the T CYCLE parameterset using the CONFigure:DIGital:HANDshake:RATE command. This settingaffects strobe width, memory clock rate, as well as the setup and holdtimes. Alternatively, the reciprocal form of the commandCONFigure:DIGital:HANDshake:CTIMe can be used to specify the speed interms of time instead of a rate. T CYCLE begins when the 34950A executesone of the input commands.The timing should be set such that the device sending the data ensuresthe data lines are valid prior to T SETUP time. The trailing edge of thestrobe line indicates the 34950A will latch the data within the T HOLD time.T SETUP is 90 ns and T HOLD is 0 ns. Since T HOLD = 0 µs, the sending devicecan use the trailing edge of the strobe to initiate a change in the datalines.A synchronous unbuffered input is shown in the diagram belowFor example, the following SCPI commands set a 34950A in slot 5 to havea 16-bit input using synchronous handshake. Two data inputs are thenperformed and the strobe line is pulsed for each query. The I/O directionline is set high following the first SENSe:DIGital:DATA:WORD? query andremains high until the digital channel is reset or reconfigured.CONF:DIG:WIDT WORD, (@5101)CONF:DIG:DIR INP, (@5101)CONF:DIG:HAND SYNC, (@5101)SENS:DIG:DATA:WORD? (@5101)SENS:DIG:DATA:WORD? (@5101)HandshakingSynchronous Unbuffered OutputsFor synchronous handshake unbuffered outputs, the H0 line indicates thedirection of the transfer. This line is set low to indicate an outputoperation. The H0 line will remain in the low state until the 34950Adirection is changed. The H1 line is the strobe output line.When the 34950A executes an output command, it sets the data lines andwaits for T CYCLE/2 before asserting the strobe line. The leading edge of thestrobe indicates the data is valid. The strobe line is asserted for T CYCLE /2and then de-asserted. The H2 line is not used and is set to highimpedance.The timing of the output operation is controlled by the T CYCLE parameterset using the CONFigure:DIGital:HANDshake:RATE command. This settingaffects strobe width, memory clock rate, as well as the setup and holdtimes. Alternatively, the reciprocal form of the commandCONFigure:DIGital:HANDshake:CTIMe can be used to specify the speed interms of time instead of a rate. The timing should be set such that thedevice receiving the data can read the data lines during the T CYCLE/2 time.A synchronous unbuffered output is shown in the diagram below (defaultFor example, the following SCPI commands set a 34950A in slot 5 to havea 16-bit output using synchronous handshake. Two data outputs are thenperformed and the strobe line is pulsed for each. The I/O direction line isset low following the first SOURce:DIGital:DATA:WORD command andremains low until the digital channel is reset of reconfigured.CONF:DIG:WIDT WORD, (@5101)CONF:DIG:DIR OUTP, (@5101)CONF:DIG:HAND SYNC, (@5101)SOUR:DIG:DATA:WORD #hFFFF, (@5101)SOUR:DIG:DATA:WORD #h4DB5, (@5101)HandshakingSynchronous Buffered InputsYou can use synchronous mode handshake with buffered (memory) input operations. (Buffered operations are described in more detail beginning on page 14.) For buffered input operations, the H0 line acts as a start/stop line. This line will be set high when the memory input command is executed and will return low when the memory input operation has completed. The H1 line is not used and is set to high impedance.An external strobe input on the H2 line controls the pace of memory transfers. The sending device must ensure the data is valid before theT SETUP and stays valid until after T HOLD. T SETUP is 46 ns and T HOLD is10 ns.A synchronous buffered input using an external clock is shown in the diagram below (default handshake line polarity).For example, the following SCPI commands set a 34950A in slot 5 to have an 8-bit input using synchronous handshake with an external strobe input. The number of bytes to read into memory is set to infinite (continuous reading into memory until the memory is stopped). The memory is enabled and then triggered. The start/stop line is set high following the first byte handshake and remains high until the last byte is captured. CONF:DIG:WIDT BYTE, (@5101)CONF:DIG:DIR INP, (@5101)CONF:DIG:HAND SYNC, (@5101)SENS:DIG:MEM:SAMP:COUN 0, (@5101)SENS:DIG:MEM:ENAB ON, (@5101)SENS:DIG:MEM:STAR (@5101)HandshakingSynchronous Buffered OutputsYou can use synchronous mode handshake with buffered (memory) outputoperations. (Buffered operations are described in more detail beginning onpage 14.) For buffered output operations, the H0 line acts as a start/stopline. This line will be set high when the memory output command isexecuted by the 34950A and will return low when the memory outputoperation has completed.Synchronous memory output operations can be paced using either theinternal strobe or an external strobe.When using the internal strobe, the H1 line is the strobe output line.The timing of the output operation when using the default INTernal clockis controlled by the CONFigure:DIGital:HANDshake:RATE command.This setting affects strobe width, memory clock rate, as well as the setupand hold times. Alternatively, the reciprocal form of the commandCONFigure:DIGital:HANDshake:CTIMe can be used to specify the speed interms of time instead of a rate. The timing should be set such that thedevice receiving the data can latch the data lines during the T CYCLE time.The receiving device should detect the leading edge of the strobe line, waitfor the 34950A to set the data (T PD) and then latch the data. Latching thedata on the trailing edge of the strobe is recommended, however, you canthe data following T PD. T PD ranges from -23 to 23 ns.A synchronous buffered output using the internal clock is shown in thediagram below (default handshake line polarity).。

N9020A MXAX-Series Signal Analyzer10 Hz to 3.6, 8.4, 13.6, or 26.5 GHz Data SheetThis data sheet is a summary of the specifications and conditions for MXA signal analyzers. For the complete specifications guide, visit: /find/mxa_specificationsTable of ContentsAccelerate to marketEvery device demands decisionsthat require tradeoffs in your goals—customer specs, through-put, yield. With a highly flexible signal analyzer, you can manage and minimize those tradeoffs. Agilent’s mid-performance MXA is the ultimate accelerator as your products move from design to the marketplace. It has the flexibility to quickly adapt to your evolving test requirements—today and tomorrow. Maximize your flexibil-ity, and accelerate to market, with the Agilent MXA signal analyzer.Definitions and Conditions ...................................................3Frequency and Time Specifications ............................................4Amplitude Accuracy and Range Specifications ...................................6Dynamic Range Specifications ................................................8PowerSuite Measurement Specifications ......................................12General Specifications ......................................................13Inputs and Outputs ........................................................14IQ Analyzer ...............................................................16IQ Analyzer - Option B40 ....................................................17IQ Analyzer - Option B85/B1A/B1X ...........................................18Real-Time Spectrum Analyzer (RTSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Related Literature (20)Definitions and ConditionsSpecifications describe the performance of parameters covered by the product warranty and apply to the full temperature range of 0 to 55 °C 1, unless otherwise noted.95th percentile values indicate the breadth of the population (approx. 2 σ) of performance tolerances expected to be met in 95 percent of the cases with a 95 percent confidence, for any ambient temperature in the range of 20 to 30 °C. In addition to the statistical observations of a sample of instruments, these values include the effects of the uncertainties of external calibration references. These values are not warranted. These values are updated occasionally if a significant change in the statistically observed behavior of production instruments is observed.Typical describes additional product performance information that is not covered by the product warranty. It is performance beyond specifications that 80 percent of the units exhibit with a 95 percent confidence level over the temperature range 20 to 30 °C. Typical performance does not include measurement uncer-tainty.Nominal values indicate expected performance, or describe product performance that is useful in the application of the product, but are not covered by the prod-uct warranty.The analyzer will meet its specifications when:• It is within its calibration cycle• Under auto couple control, except when Auto Sweep Time Rules = Accy • Signal frequencies < 10 MHz, with DC coupling applied• The analyzer has been stored at an ambient temperature within the allowed operating range for at least two hours before being turned on; if it had previ-ously been stored at a temperature range inside the allowed storage range, but outside the allowed operating range• The analyzer has been turned on at least 30 minutes with Auto Align set to normal, or, if Auto Align is set to off or partial, alignments must have been run recently enough to prevent an Alert message; if the Alert condition is changed from Time and Temperature to one of the disabled duration choices, the analyzer may fail to meet specifications without informing the userFor the complete specifications guide, visit:/find/mxa_specifications1. For earlier instruments (Serial number prefix < MY/SG/US5051), the full temperature ranges from5 to 50 °C.Frequency and Time Specifications1. Horizontal resolution is span/(sweep points – 1).1. Analysis bandwidth is the instantaneous bandwidth available around a center frequency over which the input signal can be digitized for further analysis orprocessing in the time, frequency, or modulation domain.2. Sweep points = 101. Apply for instruments with S/N prefix ≥ MY/SG/US4910 or earlier instruments with Option PC2 or PC4. Otherwise, refer to theMXA specification guide.Amplitude Accuracy and Range Specifications1. DC coupling required to meet specifications below 50 MHz. With AC coupling, specifications apply at frequencies of 50 MHz and higher. Statistical observa-tions at 10 MHz with AC coupling show that most instruments meet the DC-coupled specifications, however, a small percentage of instruments are expected to have errors exceeding 0.5 dB at 10 MHz at the temperature extreme. The effect at 20 to 50 MHz is negligible but not warranted.2. Apply for instruments with S/N prefix ≥ MY/SG/US5051. For older instruments, refer to the MXA Specification Guide.Dynamic Range Specifications1. N is the LO multiplication factor.Figure 1. Nominal dynamic range – Band 0, for second and third order distortion, 20 Hz to 3.6 GHzFigure 2. Nominal dynamic range – Bands 1 to 4, for second and third order distortion, 3.6 GHz to 26.5 GHz1. Applies for instruments with serial number prefix ≥ MY/SG/US5233. Those instruments ship standard with N9020A-EP2 as the identifier. For nominal valuesat other center frequencies, refer to Figure 3. For earlier instruments, refer to the MXA specifications guide.Figure 3. Nominal phase noise at different center frequencies (Applies for instruments with SN prefix ≥ MY/SG/US5233; ships standard with N9020A-EP2)PowerSuite Measurement SpecificationsGeneral SpecificationsInputs and Outputs1. For additional specifications, please refer to the MXA Signal Analyzer Option BBA: Analog Baseband IQ Inputs Technical Overview,literature number 5989-6538EN.2. For more details, please refer to the Agilent Probe Configuration Guides, literature numbers 5968-7141EN and 5989-6162EN; probe heads are necessary toattach to your device properly and probe connectivity kits such as E2668B, E2669A. or E2675A are required.1. Option MPB installed and enabled.I/Q Analyzer1. Option MPB is installed and enabled.I/Q Analyzer (continued)Option B40 (40 MHz analysis bandwidth, Option B40 is automatically included in Option B85, B1A or B1X)1. Option MPB is installed and enabled.I/Q Analyzer (continued)Option B85/B1A/B1X (85/125/160 MHz analysis bandwidth)1. Option MPB is installed and enabled.1. For additional RTSA specifications, please refer to Option RT1/RT2 Chapter in the MXA Signal Analyzer specification guide (part number: N9020-90113)2. StM = “Signal-to-Mask”Real-Time Spectrum Analyzer (RTSA) 1Option RT1 or RT2Related LiteratureAgilent MXA signal analyzers Brochure5989-5047ENConfiguration Guide 5989-4943EN For more information or literature resources please visit the web:/find/mxacdma2000® is a registered certification mark of the Telecommunications Industry Association. Used under license./quality/find/AdvantageServices Accurate measurements throughout the life of your instruments.Agilent Advantage ServicesThree-Year Warranty/find/ThreeYearWarranty Agilent’s combination of product reliability and three-year warranty coverage is another way we help you achieve your business goals: increased confidence in uptime, reduced cost of ownership and greater convenience.For more information on AgilentTechnologies’ products, applications or services, please contact your local Agilent office. The complete list is available at:/find/contactus Americas Canada (877) 894 4414 Brazil (11) 4197 3600Mexico 01800 5064 800 United States (800) 829 4444 Asia Pacific Australia 1 800 629 485China 800 810 0189Hong Kong 800 938 693India 1 800 112 929Japan 0120 (421) 345Korea 080 769 0800Malaysia 1 800 888 848Singapore 180****8100Taiwan 0800 047 866Other AP Countries (65) 375 8100 Europe & Middle East Belgium 32 (0) 2 404 93 40 Denmark 45 45 80 12 15Finland 358 (0) 10 855 2100France 0825 010 700**0.125 €/minuteGermany 49 (0) 7031 464 6333 Ireland 1890 924 204Israel 972-3-9288-504/544Italy 39 02 92 60 8484Netherlands 31 (0) 20 547 2111Spain 34 (91) 631 3300Sweden 0200-88 22 55United Kingdom 44 (0) 118 927 6201For other unlisted countries: /find/contactusRevised: January 6, 2012Product specifications and descriptions in this document subject to change without notice.© Agilent Technologies, Inc. 2013Published in USA, July 31, 20135989-4942EN/find/mxaLAN eXtensions for Instruments puts the power of Ethernet and the Web inside your test systems. Agilent is a founding member of the LXI consortium.Agilent Channel Partnersw w w /find/channelpartners Get the best of both worlds: Agilent’s measurement expertise and product breadth, combined with channel partner convenience./find/myagilentA personalized view into the information most relevant to you.myAgilentmy Agilent。