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MEMORY存储芯片ATMEGA8A-AU中文规格书

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Low-Power AVR 8-bit Microcontroller Data Sheet SummaryIntroduction

The ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves

throughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for power

consumption versus processing speed.Features

•High-performance, Low-power AVR 8-bit Microcontroller

•Advanced RISC Architecture

–130 powerful instructions - most single-clock cycle execution

–32 x 8 general purpose working registers

–Fully static operation

–Up to 16 MIPS throughput at 16 MHz

–On-chip 2-cycle multiplier

•High Endurance Nonvolatile Memory segments

–8 KB of In-System Self-programmable Flash program memory

–512B EEPROM

–1 KB internal SRAM

–Write/erase cycles: 10,000 Flash/100,000 EEPROM

–Data retention: 20 years at 85°C/100 years at 25°C(1)

–Optional boot code section with independent lock bits

•In-system programming by on-chip boot program

•True read-while-write operation

–Programming lock for software security

•Microchip QTouch® library support

–Capacitive touch buttons, sliders and wheels

–QTouch and QMatrix acquisition

–Up to 64 sense channels

•Peripheral Features

–Two 8-bit timer/counters with separate prescaler, one compare mode

–One 16-bit timer/counter with separate prescaler, compare mode, and capture mode

–Real-time counter with separate oscillator

–Three PWM channels

–

8-channel ADC in TQFP and QFN/MLF package11.Packaging Information

11.1 32-pin 32A

TITLEDRAWING NO.REV.

32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,0.8mm lead pitch, thin profile plastic quad flat package (TQFP) C32A2010-10-20PIN 1 IDENTIFIER

0°~7°PIN 1

LC

A1A2AD1

DeE1EB

Notes:1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowableprotrusion is 0.25mm per side. Dimensions D1 and E1 are maximumplastic body size dimensions including mold mismatch.3. Lead coplanarity is 0.10mm maximum.A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 8.75 9.00 9.25

D1 6.90 7.00 7.10 Note 2

E 8.75 9.00 9.25

E1 6.90 7.00 7.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYPCOMMON DIMENSIONS(Unit of measure = mm)

SYMBOLMINNOMMAXNOTE ATmega8A

Packaging Information11.2 28-pin 28P3

2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.REV. 28P3 , 28-lead (0.300"/7.62mm Wide) Plastic Dual Inline Package (PDIP) B28P309/28/01PIN1

E1

A1

B

REFEB1

CLSEATING PLANEA

0º ~ 15º D

e

eBB2(4 PLACES)

COMMON DIMENSIONS(Unit of Measure = mm)

SYMBOLMINNOMMAXNOTE

A – – 4.5724

A1 0.508 – –

D 34.544 – 34.798 Note 1

E 7.620 – 8.255

E1 7.112 – 7.493 Note 1

B 0.381 – 0.533

B1 1.143 – 1.397

B2 0.762 – 1.143

L 3.175 – 3.429

C 0.203 – 0.356

eB – – 10.160

e 2.540 TYP Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). ATmega8A

Packaging Information11.3 32-pin 32M1-A

COMMON DIMENSIONS(Unit of Measure = mm)

SYMBOLMINNOMMAXNOTED1D

E1E

ebA3A2A1 A

D2

E20.08C

L123P

P0123

A 0.80 0.90 1.00

A1 – 0.02 0.05

A2 – 0.65 1.00

A3 0.20 REF

b 0.180.230.30

D

D1

D2 2.953.103.25

4.905.005.104.704.754.80

4.704.754.804.905.005.10

E

E1

E2 2.953.103.25

e 0.50 BSC

L 0.30 0.40 0.50

P – – 0.60

– – 12o

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. TOP VIEWSIDE VIEW

BOTTOM VIEW

0Pin 1 ID

Pin #1 Notch (0.20 R)

K0.20––KK

32M1-A, 32-pad, 5 x 5 x 1.0mm Body, Lead Pitch 0.50mm, 3.10mm Exposed Pad, Micro Lead Frame Package (MLF)32M1-A03/14/2014

F ATmega8A

Packaging Information ATmega8AErrata

合集下载

MEMORY存储芯片MT48LC32M8A2-6A G中文规格书

MEMORY存储芯片MT48LC32M8A2-6A G中文规格书

Automotive Mobile LPDDR2 SDRAMMT42L64M16D1, MT42L32M32D1

Features•Ultra low-voltage core and I/O power supplies–VDD2 = 1.14–1.30V–VDDCA/VDDQ = 1.14–1.30V–VDD1 = 1.70–1.95V•Clock frequency range–533–10 MHz (data rate range: 1066–20 Mb/s/pin)•Four-bit prefetch DDR architecture•Eight internal banks for concurrent operation•Multiplexed, double data rate, command/addressinputs; commands entered on every CK edge•Bidirectional/differential data strobe per byte ofdata (DQS/DQS#)•Programmable READ and WRITE latencies (RL/WL)•Programmable burst lengths: 4, 8, or 16•Per-bank refresh for concurrent operation•On-chip temperature sensor to control self refreshrate•Partial-array self refresh (PASR)•Deep power-down mode (DPD)•Selectable output drive strength (DS)•Clock stop capability•RoHS-compliant, “green” packagingTable 1: Key Timing ParametersSpeedGradeClock Rate(MHz)Data Rate(Mb/s/pin)RLWLtRCD/tRP1-18533106684Typical-2540080063TypicalOptionsMarking•VDD2: 1.2VL•Configuration–8 Meg x 16 x 8 banks x 1 die64M16–4 Meg x 32 x 8 banks x 1 die32M32•Device type–LPDDR2-S4, 1 die in packageD1•FBGA “green” package–134-ball FBGA (10mm x11.5mm)HE•Timing – cycle time–1.875ns @ RL = 8-18–2.5ns @ RL = 6-25•Special options–Automotive grade (Package-levelburn-in)A•Operating temperature range–From –40°C to +85°CIT–From –40°C to +105°CAT•Revision:ANote:1.For Fast tRCD/tRP, contact factory.Preliminary‡

MEMORY存储芯片TMS32C6414TBGLZWA8中文规格书

MEMORY存储芯片TMS32C6414TBGLZWA8中文规格书

TMS570LS3135,TMS570LS2135,TMS570LS2125

SPNS164C–APRIL2012–REVISEDAPRIL2015

5.9ThermalResistanceCharacteristics

Table5-2showsthethermalresistancecharacteristicsfortheQFP-PGEmechanicalpackage.

Table5-3showsthethermalresistancecharacteristicsfortheBGA-ZWTmechanicalpackage.

Table5-2.ThermalResistanceCharacteristics(PGEPackage)

°C/W

Junction-to-freeairthermalresistance,StillairusingJEDEC2S2PtestRΘJA39board

RΘJBJunction-to-boardthermalresistance26.3

RΘJCJunction-to-casethermalresistance6.7

ΨJTJunction-to-packagetop,Stillair0.10

Table5-3.ThermalResistanceCharacteristics(ZWTPackage)

°C/W

Junction-to-freeairthermalresistance,Stillair(includes5x5thermalviaRΘJA18.8clusterin2s2pPCBconnectedto1stgroundplane)

RΘJBJunction-to-boardthermalresistance14.1

RΘJCJunction-to-casethermalresistance7.1

Junction-to-packagetop,Stillair(includes5x5thermalviaclusterin2s2pΨJT0.33PCBconnectedto1stgroundplane)

MEMORY存储芯片MT40A1G8SA-062EE中文规格书

MEMORY存储芯片MT40A1G8SA-062EE中文规格书

Commands

DESELECT

The DESELT (DES) command (CS# HIGH) prevents new commands from being execu-

ted by the DRAM. Operations already in progress are not affected.

NO OPERATION

The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from

being registered during idle or wait states. Operations already in progress are not affec-

ted.

ZQ CALIBRATION LONG

The ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibra-

tion during a power-up initialization and reset sequence (see Figure 46 (page 124)).

This command may be issued at any time by the controller, depending on the system

environment. The ZQCL command triggers the calibration engine inside the DRAM. Af-

ter calibration is achieved, the calibrated values are transferred from the calibration en-

gine to the DRAM I/O, which are reflected as updated RON and ODT values.

ATMEGA8系列规格书,Datasheet资料

ATMEGA8系列规格书,Datasheet资料

ATMEGA8系列规格书,Datasheet资料

Features

High-performance, Low-power AtmelAVR 8-bit Microcontroller Advanced RISC Architecture

–130 Powerful Instructions – Most Single-clock Cycle Execution –32 × 8 General Purpose Working Registers

–Fully Static Operation

–Up to 16 MIPS Throughput at 16MHz

–On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

–8Kbytes of In-System Self-programmable Flash program memory

–512Bytes EEPROM

–1Kbyte Internal SRAM

–Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

–Data retention: 20 years at 85°C/100 years at 25°C(1)

–Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

–Programming Lock for Software Security

Peripheral Features

–Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode

–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode