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MEMORY存储芯片MT29F2G08ABAEAWP-IT_E中文规格书

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Architecture

These devices use NAND Flash electrical and command interfaces. Data, commands,

and addresses are multiplexed onto the same pins and received by I/O control circuits.

The commands received at the I/O control circuits are latched by a command register

and are transferred to control logic circuits for generating internal signals to control de-

vice operations. The addresses are latched by an address register and sent to a row de-

coder to select a row address, or to a column decoder to select a column address.

Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word

by word (x16), through a data register and a cache register.

The NAND Flash memory array is programmed and read using page-based operations

and is erased using block-based operations. During normal page operations, the data

and cache registers act as a single register. During cache operations, the data and cache

registers operate independently to increase data throughput. The status register reports

the status of die operations.

Figure 8: NAND Flash Die (LUN) Functional Block Diagram

Address register

Data register

Cache register

ECC

Status register

Command register

CE#V

CCVSS

CLE

ALE

WE#

RE#

WP#

LOCK1I/Ox

ControllogicI/Ocontrol

R/B#Row decodeColumn decode

NAND Flasharray(2 planes)

Note:1.The LOCK pin is used on the 1.8V device.

PDF: 09005aef83b83f42m69a_2gb_ecc_nand.pdf - Rev. R 04/14 ENFigure 15: Asynchronous Data Output Cycles (EDO Mode)

DOUTDOUTDOUTCE#

RE#

I/Ox

RDYtRR

tCEAtREAtRPtREHtRC

tRLOHtREA

tRHOHtRHZtCOHtCHZ

Don’t Care

Write Protect#

The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations

to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When

WP# is HIGH, PROGRAM and ERASE operations are enabled.

It is recommended that the host drive WP# LOW during power-on until VCC is stable to

prevent inadvertent PROGRAM and ERASE operations (see Device Initialization for ad-

ditional details).

WP# must be transitioned only when the target is not busy and prior to beginning a

command sequence. After a command sequence is complete and the target is ready,

WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issu-

ing a new command.

The WP# signal is always an active input, even when CE# is HIGH. This signal should

not be multiplexed with other signals.

Ready/Busy#

The ready/busy# (R/B#) signal provides a hardware method of indicating whether a tar-

get is ready or busy. A target is busy when one or more of its die (LUNs) are busy

(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each

die (LUN) contains a status register, it is possible to determine the independent status

of each die (LUN) by polling its status register instead of using the R/B# signal (see Sta-

tus Operations for details regarding die (LUN) status).

This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the

target is ready, and transitions LOW when the target is busy. The signal's open-drain2Gb: x8, x16 NAND Flash Memory

Asynchronous Interface Bus Operation

PDF: 09005aef83b83f42m69a_2gb_ecc_nand.pdf - Rev. R 04/14 ENdriver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an

interrupt pin on the system controller.

The combination of Rp and capacitive loading of the R/B# circuit determines the rise

time of the R/B# signal. The actual value used for Rp depends on the system timing re-

quirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10%

and 90% points on the R/B# waveform, the rise time is approximately two time con-

stants (TC).

TC = R × C

Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.

The fall time of the R/B# signal is determined mainly by the output impedance of the

R/B# signal and the total load capacitance. Approximate Rp values using a circuit load

of 100pF are provided in Figure 21 (page 27).

The minimum value for Rp is determined by the output drive capability of the R/B# sig-

nal, the output voltage swing, and VCC.

Rp =VCC (MAX) - VOL (MAX)

IOL + ΣILWhere ΣIL

is the sum of the input currents of all devices tied to the R/B# pin.

Figure 16: READ/BUSY# Open Drain

RpVCC

R/B#Open drain output

I

OL

VSSDevice2Gb: x8, x16 NAND Flash Memory

Asynchronous Interface Bus Operation

PDF: 09005aef83b83f42m69a_2gb_ecc_nand.pdf - Rev. R 04/14 EN

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MEMORY存储芯片MT29F2G16ABBEAHC-IT_E中文规格书

MEMORY存储芯片MT29F2G16ABBEAHC-IT_E中文规格书

ArchitectureThese devices use NAND Flash electrical and command interfaces. Data, commands,and addresses are multiplexed onto the same pins and received by I/O control circuits.The commands received at the I/O control circuits are latched by a command registerand are transferred to control logic circuits for generating internal signals to control de-vice operations. The addresses are latched by an address register and sent to a row de-coder to select a row address, or to a column decoder to select a column address.Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or wordby word (x16), through a data register and a cache register.The NAND Flash memory array is programmed and read using page-based operationsand is erased using block-based operations. During normal page operations, the dataand cache registers act as a single register. During cache operations, the data and cacheregisters operate independently to increase data throughput. The status register reportsthe status of die operations.Figure 8: NAND Flash Die (LUN) Functional Block DiagramAddress register

MEMORY存储芯片MT29F32G08FAAWP A中文规格书

MEMORY存储芯片MT29F32G08FAAWP A中文规格书

63-Ball VFBGA, x16 (Balls Down, Top View)3WP#VccNCNCDNUI/O8I/O9Vss4ALERE#NCNCVccI/O0I/O1I/O28 R/B#NCNCNCDNUVccI/O7Vss10NCNC

NCNC9NCNC

NCNC5VssCLENCNCLOCK1I/O10I/O11I/O37WE#NCNCVssI/O15I/O14I/O5I/O66CE#NC NC NC I/O13I/O12VccI/O41NCNC

NCNCABCDEFGHJKLM2NC

NCNCNote:1.For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V de-vice.4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemorySignal Assignments63-Ball VFBGA (10.5mm x 13mm)Ball A1 ID

1.0 MAX13 ±0.1Ball A1 ID

0.8 TYP10.5 ±0.10.65 ±0.05SeatingplaneA

8.8 CTR7.2 CTR0.12 A63X Ø0.45Solder ball material:SAC305 (96.5% Sn,3% Ag, 0.5% Cu).Dimensions apply tosolder balls post-reflow on Ø0.4 SMDball pads.

0.25 MIN0.8 TYP10 9 8 7 6 5 4 3 2 1ABCDEFGHJKLMBottom side saw fiducials may ormay not be covered with soldermask.Note:1.All dimensions are in millimeters.4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryPackage DimensionsPackage Dimensions 48-Pin TSOP – Type 1, CPL1.20 MAX0.15 +0.03-0.02

MEMORY存储芯片MT29F32G08AECBBH1-12中文规格书

MEMORY存储芯片MT29F32G08AECBBH1-12中文规格书

DDR2-667. It is not advised to operate DDR2-800 and DDR2-1066 devices with single-ended DQS; however, Table 33 would be used with the base values.

Table 33: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHbReference points indicated in bold; Derating values are to be used with base tDSb- and tDHb--specified values

DQ (V/ns)DQS Single-Ended Slew Rate Derated (at VREF)

2.0 V/ns1.8 V/ns1.6 V/ns1.4 V/ns1.2 V/ns1.0 V/ns0.8 V/ns0.6 V/ns0.4 V/nstDStDHtDStDHtDStDHtDStDHtDStDHtDStDHtDStDHtDStDHtDStDH

2.0130531305313053130531305314548155451654117538

1.59732973297329732973211227122241322014217

1.030–1030–1030–1030–1030–1045–1555–1865–2275–25

0.925–2425–2425–2425–2425–2440–2950–3260–3670–39

0.817–4117–4117–4117–4117–4132–4642–4952–5361–56

0.75–645–645–645–645–6420–6930–7240–7550–79

0.6–7–93–7–93–7–93–7–93–7–938–9818–10228–10538–108

MEMORY存储芯片MT29F16G08ABACAWP-IT B中文规格书

MEMORY存储芯片MT29F16G08ABACAWP-IT B中文规格书

4.BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0.BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8.5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,Write CRC = Disable.READ Operation Followed by PRECHARGE OperationThe minimum external READ command to PRECHARGE command spacing to the samebank is equal to AL + tRTP with tRTP being the internal READ command to PRECHARGEcommand delay. Note that the minimum ACT to PRE timing, tRAS, must be satisfied aswell. The minimum value for the internal READ command to PRECHARGE commanddelay is given by tRTP (MIN) = MAX (4 × nCK, 7.5ns). A new bank ACTIVATE commandmay be issued to the same bank if the following two conditions are satisfied simultane-ously:•The minimum RAS precharge time (tRP [MIN]) has been satisfied from the clock atwhich the precharge begins.•The minimum RAS cycle time (tRC [MIN]) from the previous bank activation has beensatisfied.